UT54ACS02E*

UT54ACS02E/UT54ACTS02E
Quadruple 2-Input NOR Gate
July, 2013
www.aeroflex.com/Logic
FEATURES
 m CRH CMOS Process
- Latchup immune
 High speed
 Low power consumption
 Wide power supply operating range of 3.0V to 5.5V
 Available QML Q or V processes
 14-lead flatpack
 UT54ACS02E - SMD - 5962-96514
 UT54ACTS02E - SMD - 5962-96515
PINOUT
14-Lead Flatpack
Top View
DESCRIPTION
The UT54ACS02E and UT54ACTS02E are quadruple, twoinput NOR gates. The circuits perform the Boolean functions
Y = A + B or Y = A B in positive logic.
VDD
Y1
1
14
A1
2
13
Y4
B1
3
12
B4
Y2
A2
4
5
11
10
A4
B2
VSS
6
7
9
8
B3
A3
Y3
The devices are characterized over the full HiRel temperature
range of -55C to +125C.
FUNCTION TABLE
INPUTS
OUTPUT
A
B
Y
H
X
L
X
H
L
L
L
H
LOGIC SYMBOL
LOGIC DIAGRAM
A1 (2)
B1 (3)
A2 (5)
(6)
B2
(8)
A3
(9)
B3
(11)
A4
(12)
B4
1
(1)
A1
Y1
B1
(4)
Y2
A2
Y1
Y2
B2
(10)
(13)
Y3
A3
Y3
B3
Y4
A4
B4
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
1
Y4
OPERATIONAL ENVIRONMENT1
PARAMETER
LIMIT
UNITS
Total Dose
1.0E6
rads(Si)
SEU Threshold 2
108
MeV-cm2/mg
SEL Immune
120
MeV-cm2/mg
Neutron Fluence
1.0E14
n/cm2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
-0.3 to 7.0
V
VI/O
Voltage any pin
-0.3 to VDD + 0.3
V
TSTG
Storage Temperature range
-65 to +150
C
TJ
Maximum junction temperature
+175
C
TLS
Lead temperature (soldering 5 seconds)
+300
C
JC
Thermal resistance junction to case
15.5
C/W
II
DC input current
10
mA
PD2
Maximum package power dissipation
3.2
W
o
permitted @ Tc=125 C
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
2. Per MIL-STD-883, method 1012.1, Section 3.4.1, PD = (Tj(max) - Tc(max) ) / jc
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
3.0 to 5.5
V
VIN
Input voltage any pin
0 to VDD
V
TC
Temperature range
-55 to + 125
C
2
DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS02E7
( VDD = 3.0V to 5.5V; VSS = 0V6; -55C < TC < +125C)
SYMBOL
DESCRIPTION
CONDITION
VIL
Low-level input voltage 1
VDD from 3.0V to 5.5V
VIH
High-level input voltage 1
VDD from 3.0V to 5.5V
IIN
Input leakage current
VIN = VDD or VSS
Low-level output voltage 3
IOL = 100A
VOL
MIN
MAX
UNIT
0.3 VDD
V
0.7 VDD
-1
V
1
A
0.25
V
VDD from 3.0V to 5.5V
VOH
High-level output voltage 3
IOH = -100A
VDD - 0.25
V
VDD from 3.0V to 5.5V
IOS1
Short-circuit output current 2 ,4
VO = VDD and VSS,
-200
200
mA
-100
100
mA
VDD from 4.5V to 5.5V
IOS2
Short-circuit output current 2 ,4
VO = VDD and VSS,
VDD from 3.0V to 3.6V
IOL1
Low level output current
VIN = VDD or VSS
(sink)9
VOL = 0.4V
8
mA
6
mA
-8
mA
-6
mA
VDD from 4.5V to 5.5V
IOL2
Low level output current
VIN = VDD or VSS
(sink)9
VOL = 0.4V
VDD from 3.0V to 3.6V
IOH1
High level output current
VIN = VDD or VSS
(source)9
VOH = VDD-0.4V
VDD from 4.5V to 5.5V
IOH2
High level output current
VIN = VDD or VSS
(source)9
VOH = VDD-0.4V
VDD from 3.0V to 3.6V
Ptotal1
Power dissipation 2, 8
CL = 50pF, VDD = 4.5V to 5.5V
1.8
mW/
MHz
Ptotal2
Power dissipation 2, 8
CL = 50pF, VDD = 3.0V to 3.6V
0.72
mW/
MHz
IDDQ
Quiescent Supply Current
VIN = VDD or VSS, VDD from 3.0V to 5.5V
10
A
CIN
Input capacitance 5
 = 1MHz, VDD = 0V
15
pF
Output capacitance 5
 = 1MHz, VDD = 0V
15
pF
COUT
3
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/
MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for the maximum radiation dose available for the respective device types.
8. Power dissipation specified per switching output.
9. Guaranteed by characterization, but not tested.
4
AC ELECTRICAL CHARACTERISTICS FOR THE UT54ACS02E2
(VDD = 3.0V to 5.5V; VSS = 0V 1, -55C < TC < +125C)
SYMBOL
tPLH
tPHL
PARAMETER
Input to Yn
Input to Yn
CONDITION
VDD
CL = 50pF
3.0V to 3.6V
CL = 50pF
MAXIMUM
UNIT
1
15
ns
4.5V to 5.5V
1
7
3.0V to 3.6V
1
17
4.5V to 5.5V
1
6
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for the maximum radiation dose available for the respective device types.
5
MINIMUM
ns
DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACTS02E7
( VDD = 3.0V to 5.5V; VSS = 0V6; -55C < TC < +125C)
SYMBOL
DESCRIPTION
CONDITION
MIN
MAX
UNIT
VIL1
Low-level input voltage 1
VDD from 4.5V to 5.5V
0.8
V
VIL2
Low-level input voltage 1
VDD from 3.0V to 3.6V
0.8
V
VIH1
High-level input voltage 1
VDD from 4.5V to 5.5V
0.5 VDD
V
VIH2
High-level input voltage 1
VDD from 3.0V to 3.6V
2.0
V
Input leakage current
VIN = VDD or VSS
-1
Low-level output voltage 3
IOL = 8ma
IIN
VOL1
1
A
0.4
V
0.4
V
VDD = 4.5V to 5.5V
VOL2
Low-level output voltage 3
IOL = 6ma
VDD = 3.0V to 3.6V
VOH1
High-level output voltage 3
IOH = -8ma
0.7 VDD
V
2.4
V
VDD from 4.5V to 5.5V
VOH2
High-level output voltage 3
IOH = -6ma
VDD from 3.0V to 3.6V
IOS1
Short-circuit output current 2 ,4
VO = VDD and VSS
-200
200
mA
-100
100
mA
VDD from 4.5V to 5.5V
IOS2
Short-circuit output current 2 ,4
VO = VDD and VSS
VDD from 3.0V to 3.6V
IOL1
Low level output current 9
VIN = VDD or VSS
8
mA
6
mA
-8
mA
VOL = 0.4V
VDD from 4.5V to 5.5V
IOL2
Low level output current 9
VIN = VDD or VSS
VOL = 0.4V
VDD from 3.0V to 3.6V
IOH1
High level output current 9
VIN = VDD or VSS
VOH = VDD-0.4V
VDD from 4.5V to 5.5V
6
IOH2
High level output current9
VIN = VDD or VSS
-6
mA
VOH = VDD-0.4V
VDD from 3.0V to 3.6V
Ptotal1
Power dissipation 2, 8
CL = 50pF
1
mW/
MHz
0.5
mW/
MHz
10
A
1.6
mA
15
pF
15
pF
VDD = 4.5V to 5.5V
Ptotal2
Power dissipation 2, 8
CL = 50pF
VDD = 3.0V to 3.6V
IDDQ
Quiescent Supply Current
VIN = VDD or VSS
VDD from 3.0V to 5.5V
IDDQ
Quiescent Supply Current Delta
For input under test
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or VSS
VDD = 5.5V
CIN
Input capacitance 5
 = 1MHz
VDD = 0V
COUT
Output capacitance 5
 = 1MHz
VDD = 0V
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%,
as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed
to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/
MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for the maximum radiation dose available for the respective device types.
8. Power dissipation specified per switching output.
9. Parameter guaranteed by design and characterization, but is not tested.
7
AC ELECTRICAL CHARACTERISTICS FOR THE UT54ACTS02E2
(VDD = 3.0V to 5.5V; VSS = 0V 1, -55C < TC < +125C)
SYMBOL
PARAMETER
CONDITION
VDD
tPLH
Input to Yn
CL = 50pF
3.0V to 3.6V
tPHL
Input to Yn
CL = 50pF
MAXIMUM
UNIT
1
15
ns
4.5V to 5.5V
1
9
3.0V to 3.6V
1
17
4.5V to 5.5V
1
9
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for the maximum radiation dose available for the respective device types.
8
MINIMUM
ns
Packaging
1. All exposed metallized areas are gold plated over
electroplated nickel per MIL-PRF-38535.
2. The lid is electrically connected to VSS.
3. Lead finishes are in accordance with MIL-PRF38535.
4. Dimension symbol is in accordance with MILPRF-38533.
5. Lead position and colanarity are not measured.
Figure 1. 14-lead Flatpack
9
UT54ACS02E/UT54ACTS02E: SMD
5962 * ***** ** * * *
Lead Finish: (Notes 1 & 2)
A = Solder
C = Gold
X = Optional
Package Type:
X = 14-lead ceramic bottom-brazed dual-in-line Flatpack
Class Designator:
Q = QML Class Q
V = QML Class V
Device Type:
02 = 1 rad(Si)/sec
03 = 50 to 300 rads(Si)/sec
Drawing Number:
96514 = UT54ACS02E
96515 = UT54ACTS02E
Total Dose: (Notes 3 & 4)
R = 1E5 rads(Si)
F = 3E5 rads(Si)
G = 5E5 rads(Si)
H = 1E6 rads(Si)
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact
factory.
4. Device type 02 is only offered with a TID tolerance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test
Method 1019 Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5
rads(Si), and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A.
10
Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced Hi-Rel
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