UT54ACTS74E*

UT54ACTS74E
Dual D Flip-Flops with Clear & Preset
July, 2013
Datasheet
www.aeroflex.com/Logic
PINOUTS
FEATURES
• m CRH CMOS process
- Latchup immune
• High speed
• Low power consumption
• Wide power supply operating range from 3.0V to 5.5V
• Available QML Q or V processes
• 14-lead flatpack
• UT54ACTS74E-SMD- 5962-96535
14-Lead Flatpack
TopView
DESCRIPTION
The UT54ACTS74E contains two independent D-type positive
triggered flip-flops. A low level at the Preset or Clear inputs
sets or resets the outputs regardless of the levels of the other
inputs. When Preset and Clear are inactive (high), data at the
D input meeting the setup time requirement is transferred to the
outputs on the positive-going edge of the clock pulse. Following the hold time interval, data at the D input may be changed
without affecting the levels at the outputs.
CLR1
1
14
VDD
D1
2
13
CLR2
CLK1
3
12
D2
PRE1
4
11
CLK2
Q1
5
10
PRE2
Q1
6
9
Q2
VSS
7
8
Q2
LOGIC SYMBOL
The device is characterized over full HiRel temperature range
of -55C to +125C.
PRE1
CLK1
D1
FUNCTION TABLE
INPUTS
CLR1
OUTPUT
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H1
H1
H
H

H
H
L
H
H

L
L
H
H
H
L
X
Qo
Qo
PRE2
CLK2
D2
CLR2
(4)
(3)
(2)
(1)
S
(5)
C1
D1
(6)
Q1
Q1
R
(10)
(11)
(12)
(13)
(9)
(8)
Q2
Q2
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
Note:
1. The output levels in this configuration are not guaranteed to meet the minimum levels for VOH if the lows at preset and clear are near VIL maximum.
In addition, this configuration is nonstable; that is, it will not persist when
either preset or clear returns to its inactive (high) level.
1
LOGIC DIAGRAM
PRE
CLR
Q
CLK
Q
D
2
OPERATIONAL ENVIRONMENT 1
PARAMETER
LIMIT
UNITS
Total Dose
1.0E6
rads(Si)
SEU Threshold 2
80
MeV-cm2/mg
SEL Threshold
120
MeV-cm2/mg
Neutron Fluence
1.0E14
n/cm2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
-0.3 to 7.0
V
VI/O
Voltage any pin
-0.3 to VDD +0.3
V
TSTG
Storage Temperature range
-65 to +150
C
TJ
Maximum junction temperature
+175
C
TLS
Lead temperature (soldering 5 seconds)
+300
C
JC
Thermal resistance junction to case
15.5
C/W
II
DC input current
10
mA
PD2
Maximum package power dissipation
3.2
W
o
permitted @ TC = +125 C
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these
or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
2. Per MIL-STD-883, method 1012.1, Section 3.4.1, PD = (TJ(max) - TC(max)) / JC
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
3.0 to 5.5
V
VIN
Input voltage any pin
0 to VDD
V
TC
Temperature range
-55 to + 125
C
3
DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACTS74E7
( VDD = 3.0V to 5.5V; VSS = 0V6; -55C < TC < +125C)
SYMBOL
DESCRIPTION
CONDITION
MIN
MAX
UNIT
VIL1
Low-level input voltage 1
VDD from 4.5V to 5.5V
0.8
V
VIL2
Low-level input voltage 1
VDD from 3.0V to 3.6V
0.8
V
VIH1
High-level input voltage 1
VDD from 4.5V to 5.5V
0.5 VDD
V
VIH2
High-level input voltage 1
VDD from 3.0V to 3.6V
2.0
V
Input leakage current
VIN = VDD or VSS
-1
Low-level output voltage 3
IOL = 8ma
IIN
VOL1
1
A
0.4
V
0.4
V
VDD = 4.5V to 5.5V
VOL2
Low-level output voltage 3
IOL = 6ma
VDD = 3.0V to 3.6V
VOH1
High-level output voltage 3
IOH = -8ma
0.7 VDD
V
2.4
V
VDD from 4.5V to 5.5V
VOH2
High-level output voltage 3
IOH = -6ma
VDD from 3.0V to 3.6V
IOS1
Short-circuit output current 2 ,4
VO = VDD and VSS
-200
200
mA
-100
100
mA
VDD from 4.5V to 5.5V
IOS2
Short-circuit output current 2 ,4
VO = VDD and VSS
VDD from 3.0V to 3.6V
IOL1
Low level output current 9
VIN = VDD or VSS
8
mA
6
mA
-8
mA
-6
mA
VOL = 0.4V
VDD from 4.5V to 5.5V
IOL2
Low level output current 9
VIN = VDD or VSS
VOL = 0.4V
VDD from 3.0V to 3.6V
IOH1
High level output current 9
VIN = VDD or VSS
VOH = VDD-0.4V
VDD from 4.5V to 5.5V
IOH2
High level output current 9
VIN = VDD or VSS
VOH = VDD-0.4V
VDD from 3.0V to 3.6V
4
Ptotal1
Power dissipation 2, 8
CL = 50pF
1.0
mW/
MHz
0.5
mW/
MHz
10
A
1.6
mA
15
pF
15
pF
VDD = 4.5V to 5.5V
Ptotal2
Power dissipation 2, 8
CL = 50pF
VDD = 3.0V to 3.6V
IDDQ
Quiescent Supply Current
VIN = VDD or VSS
VDD from 3.0V to 5.5V
IDDQ
Quiescent Supply Current Delta
For input under test
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or VSS
VDD = 5.5V
CIN
Input capacitance 5
 = 1MHz
VDD = 0V
COUT
Output capacitance 5
 = 1MHz
VDD = 0V
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%,
as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed
to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/
MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose  1E6 rads(Si) per MIL-STD-883 Method 1019.
8. Power dissipation specified per switching output.
9. Guaranteed by characterization, but not tested.
5
AC ELECTRICAL CHARACTERISTICS FOR THE UT54ACTS74E2
( VDD = 3.0V to 5.5V; VSS = 0V1; -55C < TC < +125C)
SYMBOL
tPHL1
tPLH1
tPHL2
tPLH2
tPHL3
tPLH3
fMAX
tSU1
tSU2
tH
tW1
tW2
PARAMETER
CLK  to Q, Q
CLK to Q, Q
PRE to Q
PRE to Q
CLR to Q
CLR to Q
Maximum clock frequency
Data setup time before CLK
CONDITION
VDD
CL = 50pF
3.0V to 3.6V
CL = 50pF
CL = 50pF
CL = 50pF
CL = 50pF
CL = 50pF
CL = 50pF
CL = 50pF
PRE or CLR inactive
Setup time before CLK 
CL = 50pF
Data hold time after CLK 
CL = 50pF
Minimum pulse width
CLK high or low
CL = 50pF
Minimum pulse width
PRE or CLR low
CL = 50pF
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose  1E6 rads(Si) per MIL-STD-883 Method 1019.
6
MINIMUM
MAXIMUM
UNIT
3
30
ns
4.5V to 5.5V
3
14
3.0V to 3.6V
3
20
4.5V to 5.5V
2
11
3.0V to 3.6V
4
30
4.5V to 5.5V
3
15
3.0V to 3.6V
3
20
4.5V to 5.5V
3
12
3.0V to 3.6V
4
30
4.5V to 5.5V
3
15
3.0V to 3.6V
3
21
4.5V to 5.5V
2
12
3.0V to 3.6V
100
4.5V to 5.5V
125
3.0V to 3.6V
4
4.5V to 5.5V
3
3.0V to 3.6V
1
4.5V to 5.5V
1
3.0V to 3.6V
0
4.5V to 5.5V
0
3.0V to 3.6V
5
4.5V to 5.5V
4
3.0V to 3.6V
5
4.5V to 5.5V
4
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
Packaging
1. All exposed metallized areas are gold plated over
electroplated nickel per MIL-PRF-38535.
2. The lid is electrically connected to VSS.
3. Lead finishes are in accordance with MIL-PRF38535.
4. Dimension symbol is in accordance with MILPRF-38533.
5. Lead position and colanarity are not measured.
Figure 1. 14-lead Flatpack
7
Ordering Information: UT54ACTS74E: SMD
5962 * ***** ** * * *
Lead Finish: (Notes 1 & 2)
A = Solder
C = Gold
X = Optional
Package Type:
X = 14-lead ceramic bottom-brazed dual-in-line Flatpack
Class Designator:
Q = QML Class Q
V = QML Class V
Device Type:
02 = 1 rad(Si)/sec
03 = 50 to 300 rads(Si)/sec
Drawing Number:
96535 = UT54ACTS74E
Total Dose: (Note 3 and 4)
R = 1E5 rads(Si)
F = 3E5 rads(Si)
G = 5E5 rads(Si)
H = 1E6 rads(Si)
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact
factory.
4. Device type 02 is only offered with a TID tolerance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test
Method 1019 Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5
rads(Si), and is tested in accordance with MIL-STD-883 Test Method 1019 Condition A.
Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced HiRel
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