REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED REV SHEET REV 15 SHEET 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 1 2 3 4 5 6 7 8 9 10 11 REV STATUS REV OF SHEETS SHEET PMIC N/A PREPARED BY Joshua Civiello STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE Thomas M. Hess DRAWING APPROVAL DATE 16-02-22 AMSC N/A REVISION LEVEL 14 MICROCIRCUIT, DIGITAL, RADIATIONHARDENED, CMOS, CONTROLLER AREA NETWORK (CAN) FD TRANSCEIVER, MONOLITHIC SILICON. SIZE CAGE CODE A 67268 SHEET DSCC FORM 2233 APR 97 13 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http://www.landandmaritime.dla.mil CHECKED BY Muhammad Akbar APPROVED BY 12 5962-15232 1 OF 31 5962-E467-15 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 R Federal stock class designator 15232 RHA designator (see 1.2.1) \ 01 V X C Device type (see 1.2.2) Device class designator (see 1.2.3) Case outline (see 1.2.4) Lead finish (see 1.2.5) / \/ Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices shall meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device types. The device types shall identify the circuit function as follows: Device type Generic number Circuit function 01 UT64CAN3330 CAN FD transceiver with low power sleep mode 02 UT64CAN3331 CAN FD transceiver with bus isolated diagnostic loopback 03 UT64CAN3332 CAN FD transceiver with local controller baud rate match 1.2.3 Device class designator. The device class designator shall be a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q, V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter X Descriptive designator See figure 1 Terminals 8 Package style Flat package 1.2.5 Lead finish. The lead finish shall be as specified in MIL-PRF-38535 for classes Q and V. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 2 1.3 Absolute maximum ratings. 1/ Supply voltage range, (VDD) ................................................................................. Voltage on any pin, (VIN) ...................................................................................... VCANH/L Voltage on CANH and CANL bus terminal pin (On-orbit) .............................. Voltage on CANH and CANL bus terminal pin (Terrestrial) ............................. Input/Output current, (IIO) DC current per pin @ TJ = 125ºC for 20 years ............. Power dissipation, PD @ TC = 125ºC................................................................... Case temperature range, (TC) ........................................................................... Storage temperature range, (TSTG) ...................................................................... Junction temperature, (TJ) ................................................................................... Thermal resistance, junction-to-case, (θJC): Case X ............................................ ESD Protection (CANH, CANL), ESDHBM ............................................................ ESD Protection (TXD, RXD, RS, ZZ, AB), ESDHBM ............................................ -0.3 V dc to +6.0 V dc 2/ -0.3 V dc to 5.5 V dc 2/ -16 V dc to +16 V dc 3/ -36 V dc to +36 V dc 3/ + 10 mA 1.67 W 4/ -55ºC to +125ºC -65ºC to +165ºC +150ºC 15ºC/W 4000 V 5/ 2000 V 5/ 1.4 Recommended operating conditions. Operating supply voltage range, (VDD)................................................................. VCANH .................................................................................................................. VCANL .................................................................................................................... Supply voltage, (VSS) ........................................................................................... Voltage on TTL, (VI/O) .......................................................................................... Differential input voltage, (VID) ............................................................................. Bias input to RS pin, (RSBIAS) .............................................................................. Bias input to RS pin for standby ...................................................................... Bias input to RS pin for slope control............................................................... Bias input to RS pin for high speed (8 Mbps) .................................................. Case operating temperature range, (TC).............................................................. +3.0 V dc to +3.6 V dc -7.0 V dc to +12 V dc -7.0 V dc to +12 V dc 0 Vdc 0 Vdc to +5.5 Vdc -6 Vdc to +6 Vdc 0.75VDD to VDD 10 kΩ to +100 kΩ VSS to 0.3 V -55ºC to +125ºC 1.5 Radiation features. Maximum total dose available (dose rate = 50 – 300 rads (Si)/s) ........................ 100 Krads (Si) 6/ Single event phenomenon (SEP): 2 No SEL occurs at effective LET, (see 4.4.4.3) ................................................. ≤ 117 MeV/(mg/cm ) 7/ _____________ 1/ 2/ 3/ 4/ 5/ 6/ 7/ Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification are not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. All voltage values in this drawing are with respect to VSS. Radiation effects can adversely affect the reliability and performance of the device during this condition. Contact a factory representative to evaluate the reliability based on the exposure to exposure to radiation Per MIL-STD-883, Method 1012.1, Section 3.4.1, PD=(TJ(max)-TC(max))/θJC) Per MIL-STD-883, Method 3015, Table 3 Devices supplied to this drawing meet all levels P, L and R of irradiation. However, these devices are only tested in accordance with MIL-STD-883, method 1019, condition A. SEL is performed at VDD = 3.6V at 125°C. Limits are guaranteed by design or process, but not production tested unless specified by the customer through the purchase order or contract. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 3 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Copies of these documents are available online at http://quicksearch.dla.mil/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. ASTM INTERNATIONAL (ASTM) ASTM Standard F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959; http://www.astm.org.) JEDEC INTERNATIONAL (JEDEC) JESD 78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA 22201; http://www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 4 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Block Diagrams. The block diagrams shall be as specified on figure 3. 3.2.4 Truth Table(s). The truth table(s) shall be as specified on figure 4. 3.2.5 Output load circuit. The output load circuit shall be as specified on figure 5. 3.2.6 Timing waveforms. The timing waveforms shall be as specified on figure 6. 3.2.7 Radiation test circuit. The radiation test circuit shall be maintained under document revision level control by the manufacturer and shall be made available to the preparing or acquiring activity upon request. 3.2.8 Functional tests. Various functional tests used to test this device are contained in the appendix A (herein). If the test patterns cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be allowed. For device classes Q and V, alternate test patterns shall be under the control of the device manufacturer’s Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon request. 3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and post-irradiation parameter limits are as specified in Table IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in Table IIA. The electrical tests for each subgroup are defined in Table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes Q and V. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 5 TABLE IA. Electrical performance characteristics. Test Supply current maintaining a dominant output Supply current receiving a dominant bus input IDD1 IDD2 IDD3 IDD4 Supply current maintaining a Recessive output IDD5 IDD6 IDD7 Supply Current Operating In Sleep Mode IDD7A IDD8 IDD9 Standby supply current IDD10 IDD11 Supply Current Under High Voltage Fault 2/ IDD12 Supply Current Operating in Auto Loopback IDD13 Supply Current Operating in Diagnostic Loopback Test conditions 1/ -55ºC < TC < +125ºC +3.0 V < VDD < +3.6 V unless otherwise specified Symbol Group A Device subgroups type Limits Unit Min Max - 18 TXD=0V, RL=∞, RS=0V, AB=0V, ����=VDD or LBK=0V ZZ TXD=0V, RL=60Ω ±1%, RS=0V, ����=VDD, LBK=0V AB=0V, ZZ TXD=VDD, RL=60Ω ±1%, RS=0V, ����=VDD or LBK=0V, AB=0V or ZZ VID=1.4V, VIC=2.5V TXD=VDD, RL=∞, RS= 0V, AB=0V or ����=VDD or LBK=0V ZZ 1,2,3 All 1,2,3 All 60 1,2,3 All 3 mA 1,2,3 All 3 mA 1,2,3 All 3 TXD=VDD, RL=60Ω ±1%, RS=0V, ����=VDD or LBK=0V, AB=0V or ZZ VID=0.0V, VIC=2.5V ����=0V, TXD=VDD, RS=0V or RL=∞, ZZ ����=0V, TXD=VDD, VDD RL=60Ω ±1%, ZZ ����=0V, RS=0V or VDD RL=60Ω ±1%, , ZZ TXD=VDD, RS=0V or VDD, VID=0.0V, VIC=2.5V RL=∞, RS=VDD, TXD=VDD, AB=0V or ����=VDD or LBK=0V ZZ RL=60Ω ±1%, RS=VDD, TXD=VDD, ����=VDD or LBK=0V AB=0V or ZZ RL=60Ω ±1%, RS=VDD, TXD=VDD, ����=VDD or LBK=0V, AB=0V or ZZ VID=0.0V, VIC=2.5V 1,2,3 All 3 01 60 TXD=VDD, RL=60Ω ±1%, RS=0V, ����=VDD or LBK=0V AB=0V or ZZ RL=∞, RS=0V, TXD=VDD, AB=0V or ����=VDD or LBK=0V, VCANH/L=+/-24V ZZ mA µA 60 1,2,3 115 1,2,3 All 1.6 mA 1,2,3 All 1.65 mA 1,2,3 All 1.6 mA All 6 mA 03 3 mA 1,2,3 RL=∞, RS=0V, TXD=0V, AB=VDD 1,2,3 IDD13A RL=60Ω ±1%, RS=0V, TXD=0V, AB=VDD 1,2,3 3 IDD13B RL=60Ω ±1%, RS=0V, TXD=0V, AB=VDD, VID=1.4V, VIC=2.5V 1,2,3 3 IDD14 RL=∞, RS=0V, TXD=0V, LBK=VDD 1,2,3 IDD14A RL=60Ω ±1%, RS=0V, TXD=0V, LBK=VDD 1,2,3 02 3 mA 3 See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 6 TABLE IA. Electrical performance characteristics - Continued. Test Bus output voltage (dominant) CANH Bus output voltage (dominant) CANL Bus output voltage (recessive) CANH Bus output voltage (recessive) CANL Differential output voltage (dominant) VCANH1 VCANL1 VCANH2 VCANL2 VODD1 VODD2 Differential output voltage (recessive) VODR1 VODR2 Short-circuit output 3/ IOSH1 IOSH2 IOSL1 IOSL2 See footnotes at end of table. Test conditions 1/ -55ºC < TC < +125ºC +3.0 V < VDD < +3.6 V unless otherwise specified Symbol TXD=0V, RS=0V, RL=60Ω ±1%, ����=VDD or LBK=0V AB=0V or ZZ TXD=0V, RS=0V, RL=60Ω ±1%, ����=VDD or LBK=0V AB=0V or ZZ TXD= VDD, RS=0V, RL=60Ω ±1%, ����=VDD or LBK=0V AB=0V or ZZ TXD=VDD, RS=0V, RL=60Ω ±1%, ����=VDD or LBK=0V AB=0V or ZZ TXD=0V, RS=0V, RL=60Ω ±1%, ����=VDD or LBK=0V AB=0V or ZZ TXD=0V, RS=0V, VTEST = -7 to ����=VDD or +12V, AB=0V or ZZ LBK=0V TXD=VDD, RS=0V, RL=60Ω ±1%, ����=VDD or LBK=0V AB=0V or ZZ TXD=VDD, RS=0V, RL=∞, AB=0V ����=VDD or LBK=0V or ZZ VCANH=-7 V, CANL=∞, TXD=0V, ����=VDD or RS=0V, AB=0V or ZZ LBK=0V VCANL=12 V, CANL=∞, TXD=0V, ����=VDD or RS=0V, AB=0V or ZZ LBK=0V VCANL=-7 V, CANH=∞, TXD=0V, ����=VDD or RS=0V, AB=0V or ZZ LBK=0V VCANL=12, CANH=∞,TXD=0V, ����=VDD or RS=0V, AB=0V or ZZ LBK=0V STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 Group A Device subgroups type Limits Unit Min Max 1,2,3 All 2.45 VDD V 1,2,3 All 0.50 1.25 V 1,2,3 All 2.0 3.0 V 1,2,3 All 2.0 3.0 V 1,2,3 All 1.5 3.0 1,2,3 All 1.2 3.0 1,2,3 All –120 12 mV 1,2,3 All –500 50 mV 1,2,3 All -250 1,2,3 All V 1 mA 1,2,3 All 1,2,3 All -1 250 SIZE 5962-15232 A REVISION LEVEL SHEET 7 TABLE IA. Electrical performance characteristics - Continued. Test Test conditions 1/ -55ºC < TC < +125ºC +3.0 V < VDD < +3.6 V unless otherwise specified Symbol Group A Device subgroups type Limits Min Unit Max Receiver Positive-going input threshold voltage Negative-going input threshold voltage Hysteresis voltage 1,2,3 All VIT– ����=VDD or LBK=0V, VIC=2.5V AB=0V or ZZ 1,2,3 All 500 VHST VHST=VIT+ – VIT– 1,2,3 All 20 VCANH or VCANL = 12V VCANH or VCANL = 12V and VDD ≤ VSS+0.3V VCANH or VCANL= –7V 1,2,3 All 500 1,2,3 All 600 1,2,3 All -610 1,2,3 All -450 4,5,6 All 50 4,5,6 All 50 4,5,6 All 25 4,5,6 All 40 100 4,5,6 All 20 50 4,5,6 All 20 50 4,5,6 All VIT+ IIR1 IIR2 Bias input current IIR3 IIR4 CANH Capacitance 4/ CH CANL Capacitance 4/ CL Differential capacitance 4/ Differential input resistance Single ended input resistance CANH Single ended input resistance CANL Percent difference between RH and RL CID RID RH RL TXD=VDD, AB=0V or ����=VDD or LBK ZZ =0V, Other bus pin (VCANH or VCANL) at 0V VCANH or VCANL= –7V and VDD ≤ VSS+0.3V CANH to VSS, VI= 0.025*Sin(2E6πt)+2.3V, ����=VDD or LBK=0V TXD=VDD, AB=0V or ZZ CANL to VSS, VI= 0.025*Sin(2E6πt)+2.3V, ����=VDD or LBK=0V TXD=VDD, AB=0V or ZZ CANH to CANL, VI = 0.025*Sin(2E6πt), ����=VDD or LBK=0V TXD=VDD, AB=0V or ZZ ����=VDD or LBK=0V AB=0V or ZZ RM 2*|(RL-RH)|/(RL+RH)*100 900 mV µA 3.0 pF kΩ % See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 8 TABLE IA. Electrical performance characteristics - Continued. Test Test conditions 1/ -55ºC < TC < +125ºC +3.0 V < VDD < +3.6 V unless otherwise specified Symbol Group A Device subgroups type Limits Unit Min Max Analog Input (RS) Input voltage for enabling Highspeed mode (8Mbps operation) Input Voltage for enabling Standby mode High-Speed mode input current Standby mode input current Cold sparing leakage current TXD=VDD, RL=60Ω ±1%, AB=0V or ����=VDD or LBK=0V ZZ TXD=VDD, RL=60Ω ±1%, AB=0V or ����=VDD or LBK=0V ZZ VRS=0V 1,2,3 All VSS 300 mV 1,2,3 All 0.75*VDD 5.5 V 1,2,3 All -500 -100 µA IRS2 VRS=0.75*VDD 30 IRS3 VRS=5.5V 1,2,3 1,2,3 All All 50 µA µA IRS4 VRS=5.5V or VRS ≤ 0.3V, VDD ≤ VSS+0.3V 1,2,3 All -20 20 µA 1,2,3 All 2.00 1,2,3 All VRS1 VRS2 IRS1 TTL I/O (TXD, ZZ, AB, RXD, LBK) Input Voltage High VIH V 0.8 V Input Voltage Low VIL Input leakage current on TXD Input leakage current on pins (ZZ, AB, LBK) Cold sparing leakage current (TXD, ZZ, AB, RXD, LBK) IIOD Vin=0V or Vin=5.5V 1,2,3 All -60 100 µA IIO Vin=0V or Vin=5.5V 1,2,3 All -10 100 µA ICS Vin=0.0V and Vin=5.5V, VDD ≤ VSS+0.3V 1,2,3 All -20 20 µA IOH=-4mA IOL=4mA 1,2,3 All 2.4 Output Low voltage on RXD VOH VOL 1,2,3 All 0.4 V Input Capacitance 3/ CIO ���� or AB or RXD or LBK TXD or ZZ to VSS, VI= 0.025*Sin(2E6πt), RS=0V 1,2,3 All 10 pF Output high voltage on RXD V See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 9 TABLE IA. Electrical performance characteristics - Continued. Test Test conditions 1/ -55ºC < TC < +125ºC +3.0 V < VDD < +3.6 V unless otherwise specified Symbol Group A Device subgroups type Limits Min Unit Max Driver AC Electronics Characteristics tPLHT1 Propagation delay time (TXD input dominant to CAN dominant 5/ tPLHT2 tPLHT3 tPHLT1 Propagation delay time, (TXD recessive to CAN recessive) 5/ tPHLT2 tPHLT3 RS=0V, RL=60Ω ±1%, AB=0V or ����=VDD or LBK=0V, VTXD ≤ 125kHz ZZ (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω) RS with 10kΩ to VSS, RL=60Ω ±1%, ����=VDD or LBK=0V, VTXD AB=0V or ZZ ≤ 125 kHz (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω) RS with 100kΩ to VSS, RL=60Ω ����=VDD or LBK= 0V, ±1%, AB=0V or ZZ VTXD ≤ 125 kHz (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω) RS=0V, RL=60Ω ±1%, AB=0V or ����=VDD or LBK=0V, VTXD ≤ 125kHz ZZ (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω) RS with 10kΩ to VSS, RL=60Ω ±1%, ����=VDD or LBK=0V, VTXD AB=0V or ZZ ≤ 125kHz (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω) RS with 100kΩ to VSS, RL=60Ω ����=VDD or LBK=0V, ±1%, AB=0V or ZZ VTXD ≤ 125kHz (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50 Ω) 9,10,11 All 85 9,10,11 All 260 ns 9,10,11 All 870 9,10,11 All 120 9,10,11 All 485 9,10,11 All 1650 ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 10 TABLE IA. Electrical performance characteristics - Continued. Test Symbol tSKPT1 Pulse skew (|tPHL – tPLH|) 5/ tSKPT2 tSKPT3 tRT1 Differential CAN signal fall time 3/ 5/ tRT2 tRT3 tFT1 Differential CAN signal fall time 3/ 5/ tFT2 tFT3 Enable time from standby deactivate to CAN dominant tENS Enable time from sleep deactivate to CAN dominant tENZ Test conditions 1/ -55ºC < TC < +125ºC +3.0 V < VDD < +3.6 V unless otherwise specified RS=0V, RL=60Ω ±1%, AB=0V or ����=VDD or LBK=0V, VTXD ≤ 125kHz ZZ (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω) RS with 10kΩ to VSS, RL=60Ω ±1%, ����=VDD or LBK=0V, VTXD AB=0V or ZZ ≤ 125kHz (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω) RS with 100kΩ to VSS, RL=60Ω ����=VDD or LBK=0V, ±1%, AB=0V or ZZ VTXD ≤ 125kHz (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO 50Ω) RS=0V, RL=60Ω ±1%, AB=0V or ����=VDD or LBK=0V, VTXD ≤ 125kHz ZZ (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω) RS with 10kΩ to VSS, RL=60Ω ±1%, ����=VDD or LBK=0V, VTXD AB=0V or ZZ ≤ 125kHz (Square wave, 50% duty cycle, tr ≤ 6 s, tf ≤ 6ns, ZO=50Ω) RS with 100kΩ to VSS, RL=60Ω ����=VDD or LBK=0V, ±1%, AB=0V or ZZ VTXD ≤ 125kHz (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω) RS=0V, RL=60Ω ±1%, AB=0V or ����=VDD or LBK=0V, VTXD ≤ 125kHz ZZ (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω) RS with 10kΩ to VSS, RL=60Ω ±1%, ����=VDD or LBK=0V, VTXD AB=0V or ZZ ≤ 125kHz (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω) RS with 100kΩ to VSS, RL=60Ω ����=VDD or LBK=0V, ±1%, AB=0V or ZZ VTXD ≤ 125kHz (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω) TXD=0V, RL=60Ω ±1%, AB=0V or ����=VDD or LBK=0V, VRS ≤ 125kHz ZZ (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω, RS ˂ 0.75*VDD) RS=0V, TXD=0V, RL=60Ω ±1%, 𝑉𝑉𝑍𝑍𝑍𝑍 ���� ≤ 50kHz (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω) STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 Group A subgroups Device type Limits Min Unit Max 9,10,11 All 75 9,10,11 All 450 9,10,11 All 1250 9,10,11 All 5 80 9,10,11 All 14 250 9,10,11 All 40 1000 9,10,11 All 20 75 9,10,11 All 30 185 9,10,11 All 40 800 9,10,11 All 1.5 µs 9,10,11 01 7 µs ns ns ns SIZE 5962-15232 A REVISION LEVEL SHEET 11 TABLE IA. Electrical performance characteristics - Continued. Test Symbol Disable time from standby assert to CAN recessive tDISS Disable time from sleep assert to CAN recessive tDISZ Test conditions 1/ -55ºC < TC < +125ºC +3.0 V < VDD < +3.6 V unless otherwise specified TXD=0V, RL=60Ω ±1%, AB=0V or ����=VDD or LBK=0V, VRS ≤ 125kHz ZZ (Square wave , 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω, RS ≥ 0.75*VDD) RS=0V, TXD=0V, RL=60Ω ±1%, 𝑉𝑉𝑍𝑍𝑍𝑍 ���� ≤ 50kHz (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω) Group A subgroups Device type Limits Min Unit Max 9,10,11 All 150 ns 9,10,11 01 100 ns 9,10,11 All 60 ns 9,10,11 All 60 ns 9,10,11 All 25 ns 9,10,11 All 5 ns 9,10,11 All 5 ns Receiver AC Electronics Characteristics Propagation delay time (CANH recessive to RXD recessive) 5/ tPLHR Propagation delay time (CANH dominant to RXD dominant) 5/ tPHLR Pulse skew tSKPR RXD output signal rise time 3/ 5/ tRR RXD output signal fall time 3/ 5/ tFR RS=0V, TXD=VDD, RL=∞ Ohms ����=VDD or LBK=0V, ±1%, AB=0V or ZZ VCANH ≤ 125kHz (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO =50Ω), VCANL=1.25V RS=0V, TXD=VDD, RL=∞ Ohms ����=VDD or LBK=0V, ±1%, AB=0V or ZZ VCANH ≤ 125kHz (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω), VCANL=1.25V tSKPR =(|tPHLR – tPLHR|) RS=0V, TXD=VDD, RL=60Ω ±1%, ����=VDD or LBK=0V, VCANH AB=0V or ZZ ≤ 125kHz (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω), VCANL=1.50V RS=0V, TXD=VDD, RL=60Ω ±1%, ����=VDD or LBK=0V, VCANH AB=0V or ZZ ≤ 125kHz (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω), VCANL=1.50V See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 12 TABLE IA. Electrical performance characteristics - Continued. Test Test conditions 1/ -55ºC < TC < +125ºC +3.0 V < VDD < +3.6 V unless otherwise specified Symbol Group A subgroups Device type Limits Min Unit Max Transceiver Loopback AC Electronics Characteristics tLOOPD1 Total loop delay, TXD to RXD, dominant 5/ tLOOPD2 tLOOPD3 tLOOPR1 Total loop delay, TXD to RXD, recessive 5/ tLOOPR2 tLOOPR3 Loopback delay, TXD to RXD 5/ tLBK Loopback delay, TXD to RXD 5/ tAB1 Loopback delay, CAN input to RXD 5/ tAB2 RS=0V, RL=60Ω ±1%, AB=0V or ����=VDD or LBK=0V, VTXD ≤ 125kHz ZZ (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω) RS with 10kΩ to VSS, RL=60Ω ����=VDD or ±1%, AB=0V or ZZ LBK=0V, VTXD ≤ 125kHz (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω) RS with 100kΩ to VSS, RL=60Ω ����=VDD or ±1%, AB=0V or ZZ LBK=0V, VTXD ≤ 125kHz (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω) RS=0V, RL=60Ω ±1%, AB=0V or ����=VDD or LBK=0V, VTXD ≤ 125kHz ZZ (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω) RS with 10kΩ to VSS, RL=60Ω ����=VDD or ±1%, AB=0V or ZZ LBK=0V, VTXD ≤ 125kHz (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω) RS with 100kΩ to VSS, RL=60Ω ����=VDD or ±1%, AB=0V or ZZ LBK=0V, VTXD ≤ 125kHz (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω) RS=0V, RL=60Ω ±1%, LBK=VDD, VTXD ≤ 125kHz (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω) RS=0V, RL=60Ω, AB=VDD, VTXD ≤ 125kHz (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω) RS=0V, TXD=VDD, RL=∞ Ohms ±1%, AB=VDD, VCANH ≤ 125kHz (Square wave, 50% duty cycle, tr ≤ 6ns, tf ≤ 6ns, ZO=50Ω) 9,10,11 All 125 9,10,11 All 800 9,10,11 All 1500 All 125 9,10,11 All 800 9,10,11 All 1650 9,10,11 02 20 ns 9,10,11 03 20 ns 9,10,11 02 60 ns 9,10,11 ns ns See footnote next page STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 13 TABLE IA. Electrical performance characteristics - Continued. 1/ 2/ 3/ 4/ 5/ Devices supplied to this drawing meet all levels M, D, P, L, and R of irradiation. However, these devices are only characterized at the “R” level. Pre and Post irradiation values are identical unless otherwise specified in Table IA. When performing post irradiation electrical measurements for any RHA level, TA = +25°C. Guaranteed by characterization for VCANH/L = +/-36 V Guaranteed by characterization This parameter is tested initially and after any design or process change which could affect this parameter, and therefore shall be guaranteed to the limits specified in Table IA. CL = 75pF or equivalent on the ATE or 15pF ±20% for bench test characterization. TABLE IB. SEP test limits . 1/ 2/ Device Type Single Event Latch-up (SEL) Test 3/ 4/ Bias VDD = 3.6 V Effective LET no SEL All LET ≤117 MeV-mg/cm 2 1/ For SEP test conditions, see 4.4.4.3 herein. 2/ Technology characterization and model verification supplemented by in-line data may be used in lieu of end-of-line testing. Test plan must be approved by TRB and qualifying activity. 3/ Worst case temperature for latch-up test TA = +125°C ±10°C. 4/ SEL is performed at bias VDD = 3.6V at 125°C. Limits are guaranteed by design or process, but not production tested unless specified by the customer through the purchase order or contract. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 14 Case outline X FIGURE 1. Case outline X STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 15 Case outline X Symbol Millimeters Min A Max 3.05 max b 0.38 0.48 c 0.102 0.152 D 6.35 6.61 e 1.27 typ. E 6.35 6.61 E2 4.32 4.58 E3 1.015 typ. L 8.25 max Q 0.66 min S1 0.92 1.32 NOTES: 1. All exposed metal and metalized areas shall be gold plated per MIL-PRF-38535. 2. The seal ring and lids are electrically connected to VSS. 3. Lead finish is in accordance with MIL-PRF-38535. 4. Package material: opaque 90% minimum alumina ceramic. 5. ESD classification mark or dot is located in the pin 1 corner within area shown. FIGURE 1. Case outline - Continued STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 16 Device type 01 Case outline X Terminal number Terminal symbol 1 2 3 4 5 6 7 8 TXD VSS VDD RXD ZZ CANL CANH RS Device type 02 Case outline X Terminal number Terminal symbol 1 2 3 4 5 6 7 8 TXD VSS VDD RXD LBK CANL CANH RS Device type 03 Case outline X Terminal number Terminal symbol 1 2 3 4 5 6 7 8 TXD VSS VDD RXD AB CANL CANH RS FIGURE 2. Terminal connections STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 17 FIGURE 3. Block Diagrams Device Type 01 (Sleep) FIGURE 3. Block Diagrams Device Type 02 (Diagnostic Loopback) - continued STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 18 FIGURE 3. Block Diagrams Device Type 03 (Auto-Baud Loopback) - continued INPUT OUTPUT MEASURED R |VID| VCANH VCANL –6.1 V –7 V L 12 V 11.1 V L –1 V –7 V L 12 V 6V L 6V –6.5 V –7 V H 500 mV 12 V 11.5 V H –7 V –1 V H 6V 6V 12 V H 6V Open Open H X 900 mV VOL 900 mV 6V VOH 500 mV Figure 4 Truth Table STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 19 Notes: 1. 50 pF including scope probe and test socket. 2. Measurement of data output occurs at the low to high or high to low transition mid-point, typically, VDD/2 FIGURE 5. Output load circuit STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 20 RS V RS V TXD CANH TXD VOD V LBK, V AB, V V IH ZZ RL t ZZR V CANH CANL RXD V RXD V V IL V CANH2 0V LBK,AB,ZZ V CANL2 V CANL ZZ 0V CL=75 pF OR EQUIV. ATE LOAD OR 15 pF ±20% BENCH TEST LOAD FIGURE 6. Timing waveforms (DC Test Configuration) FIGURE 6 Timing waveforms (Driver Voltage, Current, and Test Definition) - Continued STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 21 FIGURE 6 Timing waveforms (Bus Logic State Voltages Definitions) - continued RS TXD CANH VO 330 ±1% 60 ±1% 330 ±1% CANL VI -7 V < V TEST < +12 V + - FIGURE 6 Timing waveforms (Driver VOD) - Continued STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 22 CANH VI(CANH) V IC= +VI(CANL) VI(CANL) 2 IRXD CANL VRXD VI(CANL) FIGURE 6 Timing waveforms (Receiver Voltage and Current Definitions) - Continued I OSH RS I OS TXD 0V + VRS OR VDD - I OSL VI 15 + - s 12 V 0V 0V VI 10 s VI -7 V FIGURE 6 Timing waveforms (IOS Test Circuit and Waveforms) - Continued STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 23 FIGURE 6 Timing waveforms (Drive Test Circuit and Voltage Waveforms) - Continued RS V RS V TXD CANH TXD VOD V LBK, V AB, V ZZ V DD 50% V RS CANL RXD V RXD 60 ±1% 0V t ENS V OH 50% V OL V RXD LBK,AB,ZZ CL=75 pF OR EQUIV. ATE LOAD OR 15 pF ±20% BENCH TEST LOAD FIGURE 6 Timing waveforms (tENS and tDISS Test Circuit and Voltage Waveforms) - Continued STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 24 FIGURE 6 Timing waveforms (tENZ Test Circuit and Voltage Waveforms) - Continued FIGURE 6 Timing waveforms (Receiver Test Circuit and Voltage Waveforms) - Continued STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 25 RS V RS V TXD CANH TXD VOD V LBK, V AB, V ZZ V CANL RXD V RXD V 60 ±1% TXD t LOOPD t LOOPR V DD 50% 0V t LOOPD t LOOPR V OH 50% V OL RXD LBK,AB,ZZ CL=75 pF OR EQUIV. ATE LOAD OR 15 pF ±20% BENCH TEST LOAD FIGURE 6 Timing waveforms (tLOOP Test Circuit and Voltage Waveforms) - Continued RS V RS V TXD CANH TXD VOD V LBK, V AB, V ZZ V V t V t LBK 0V LBK RXD LBK,AB,ZZ V CL=75 pF OR EQUIV. ATE LOAD OR 15 pF ±20% BENCH TEST LOAD DD 50% TXD CANL RXD V RXD 60 ±1% V OH 50% V OL 2.3 V OD FIGURE 6 Timing waveforms (tLBK Test Circuit and Voltage Waveforms) - Continued STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 26 RS V RS V TXD CANH TXD VOD V t V V LBK, V AB, t ABI 0V ABI RXD LBK,AB,ZZ V ZZ V CL=75 pF OR EQUIV. ATE LOAD OR 15 pF ±20% BENCH TEST LOAD DD 50% TXD CANL RXD V RXD V 60 ±1% V OH 50% V OL 2.3 V OD FIGURE 6 Timing waveforms (tAB1 Test Circuit and Voltage Waveforms) - Continued RS V RS V TXD CANH TXD VOD V 60 ±1% V CANL RXD V RXD V LBK, V AB, V ZZ 1.5 V CANL 2.9 V 2.2 V CANH t LBK,AB,ZZ V AB2 t 1.5 V AB2 RXD V OH 50% V OL CL=75 pF OR EQUIV. ATE LOAD OR 15 pF ±20% BENCH TEST LOAD FIGURE 6 Timing waveforms (tAB2 Test Circuit and Voltage Waveforms) - Continued STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 27 4. VERIFICATION 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MILPRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. 4.2.1 Additional criteria for device classes Q and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table II herein. c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in MIL-PRF-38535, appendix B. 4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with MIL-PRF-38535 including groups A, B, C, D, and E inspections, and as specified herein (see 4.4.1 through 4.4.4). 4.4.1 Group A inspection. a. Tests shall be as specified in table II herein. b. For device classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device. 4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table II herein. 4.4.2.1 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. 4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 28 4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). a. End-point electrical parameters shall be as specified in table IIA herein. b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535 for the RHA level being tested. All device classes must meet the post-irradiation end-point electrical parameter limits as defined in table I at TA = +25°C ±5°C, after exposure, to the subgroups specified in table II herein. 4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883 method 1019, condition A, and as specified herein. 4.4.4.1.1 Accelerated aging test. Accelerated aging tests shall be performed on all devices requiring a RHA level greater than 5k rads(Si). The post-anneal end-point electrical parameter limits shall be as specified in table I herein and shall be the pre-irradiation end-point electrical parameter limit at 25°C ±5°C. Testing shall be performed at initial qualification and after any design or process changes which may affect the RHA response of the device. 4.4.4.2 Neutron irradiation. When specified in the purchase order or contract, Neutron irradiation test shall be conducted by 14 2 using a neutron fluence of approximately 1 x 10 neutrons/cm . 4.4.4.3 Single event phenomena (SEP). When specified in the purchase order or contract, SEP testing shall be performed on class V devices. SEP testing shall be performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as approved by the qualifying activity at initial qualification and after any design or process changes which may affect the upset or latch-up characteristics. Test four devices with zero failures. ASTM F1192 may be used as a guideline when performing SEP testing. The test conditions for SEP are as follows: a. The ion beam angle of incidence shall be between normal to the die surface and 60° to the normal, inclusive (i.e. 0° ≤ angle ≤ 60°). No shadowing of the ion beam due to fixturing or package related affects is allowed. b. The fluence shall be ≥ 100 errors or ≥ 10 ions/cm . c. The flux shall be between 10 and 10 ions/cm /s. The cross-section shall be verified to be flux independent by measuring the cross-section at two flux rates which differ by at least an order of magnitude. d. The particle range shall be ≥ 20 micron in silicon. e. The test temperature shall be the maximum rated operating temperature ±10°C for the latch-up measurements. f. Bias conditions shall be defined by the manufacturer for the latch-up measurements. 7 2 6 2 2 g. For SEP test limits, see table IB herein. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 29 TABLE IIA. Electrical test requirements. 1/ 2/ 3/ 5/ Test requirements Device class Q Device class V 1,4,7,9 1,4,7,9 Static burn-in (method 1015) Not Required Required Post burn-in interim electrical parameters Not Required Interim electrical parameters (see 4.2) Dynamic burn-in (method 1015) Final electrical parameters (see 4.2) Group A test requirements (see 4.4) Group C end-point electrical parameters (see 4.4) Group D end-point electrical parameters (see 4.4) Group E end-point electrical parameters 4/ 5/ 1,4,7,9 Required Post burn-in interim electrical parameters 1/ 2/ 3/ Subgroups (in accordance with MIL-PRF-38535, table III) 4/ Required N/A 1,4,7,9 4/ 1, 2, 3, 4, 5, 6, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 4, 5, 6, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 4, 5, 6, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 4, 5, 6, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 4, 5, 6, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 4/ 1, 2, 3, 4, 5, 6, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 4, 5, 6, 7, 8A, 1, 4, 7, 9 1, 4, 7, 9 8B, 9, 10, 11 (see 4.4) PDA applies to subgroup 1 (see 4.2.3). For device class V, PDA applies to subgroups 1 and 7 (see 4.2.3). The burn-in shall meet the requirements of 4.2.1a herein. On all class V lots, the device manufacturer shall maintain read-and-record data (as a minimum on disk) for burn-in electrical parameters (group A, subgroup 1), in accordance with MIL-PRF-38535. For pre-burn-in and interim electrical parameters, the read-and-record requirements are for delta measurements only. Delta limits shall be required only on table IA, subgroup 1. The delta values shall be computed with reference to the previous interim electrical parameters. The delta limits are specified in table IIB. The device manufacturer may, at his option, either complete subgroup 1 electrical parameter measurements, including delta measurements, within 96 hours after burn-in completion (removal of bias) or may complete subgroup 1 electrical measurements without delta measurements within 24 hours after burn-in completion (removal of bias). When the manufacturer elects to perform the subgroup 1 electrical parameter measurements without delta measurements, there is no requirement to perform the pre-burn-in electrical tests (first interim electrical parameters test in table IIA). STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 30 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes Q and V. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-prepared specification or drawing. 6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires configuration control and which SMD's are applicable to that system. DLA Land and Maritime will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-8108. 6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990, or telephone (614)692-0540. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF38535 and MIL-HDBK-1331. 6.6 Sources of supply. 6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in MIL-HDBK-103 and QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DLA Land and Maritime-VA and have agreed to this drawing. 6.7 Additional information. When applicable, a copy of the following additional data shall be maintained and available from the device manufacturer: a. RHA test conditions (SEP). b. Observed single event transient (SET). c. Occurrence of latch-up (SEL). STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-15232 A REVISION LEVEL SHEET 31 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 16-02-22 Approved sources of supply for SMD 5962-15232 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DLA Land and Maritime-VA. This information bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 2/ 5962R1523201QXC 65342 UT64CAN3330XQC 5962R1523202QXC 65342 UT64CAN3331XQC 5962R1523203QXC 65342 UT64CAN3332XQC 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed, contact the Vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Vendor CAGE number 65342 Vendor name and address Aeroflex Colorado Springs, Inc. dba Cobham Semiconductor Solutions 4350 Centennial Blvd. Colorado Springs, CO 80907-7370 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.