INFINEON TLE42994G

Low Dropout Fixed Voltage Regulator
1
TLE42994
Overview
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Output Voltage 5 V ± 2%
Ouput Current up to 150 mA
Extreme Low Current Consumption In ON State
Enable Function: Below 1 µA Current Consumption In OFF State
Early Warning
Power-on and Undervoltage Reset with Programmable Delay Time
Reset Low Down to VQ = 1 V
Adjustable Reset Threshold
Very Low Dropout Voltage
Output Current Limitation
Reverse Polarity Protection
Overtemperature Protection
Suitable for Use in Automotive Electronics
Wide Temperature Range from -40 °C up to 150 °C
Input Voltage Range from -42 V to 45 V
Green Product (RoHS compliant)
AEC Qualified
PG-DSO-8
PG-DSO-14
Description
The TLE42994G is a monolithic integrated low dropout voltage
regulator, especially designed for automotive applications that need to
be in ON state during the car’s engine is turned off. An input voltage up
to 45 V is regulated to an output voltage of 5.0 V. The component is
able to drive loads up to 150 mA. It is short-circuit protected by the
implemented current limitation and has an integrated overtemperature
shutdown. A reset signal is generated for an output voltage VQ,rt of
typically 4.65 V. This threshold can be decreased by an external
resistor divider. The power-on reset delay time can be programmed by
PG-SSOP-14
Type
Package
Marking
TLE42994G
PG-DSO-8
42994G
TLE42994GM
PG-DSO-14
42994GM
TLE42994E
PG-SSOP-14
42994E
Data Sheet
1
Rev. 1.1, 2009-05-19
TLE42994
Overview
the external delay capacitor. The additional sense comparator provides an early warning function: Any voltage
(e.g. the input voltage) can be monitored, an under-voltage condition is indicated by setting the comparator’s
output to low. The TLE42994GM (PG-DSO-14 package) and TLE42994E (PG-SSOP-14 package) include
additionally an Enable function permitting enabling/disabling the regulator. In case the regulator is disabled it
consumes less current than 1 µA.
Dimensioning Information on External Components
The input capacitor CI is recommended for compensation of line influences. The output capacitor CQ is necessary
for the stability of the control loop.
Circuit Description
The control amplifier compares a reference voltage to a voltage that is proportional to the output voltage and drives
the base of the series transistor via a buffer. Saturation control as a function of the load current prevents any
oversaturation of the power element. The component also has a number of internal circuits for protection against:
•
•
•
Overload
Overtemperature
Reverse polarity
Data Sheet
2
Rev. 1.1, 2009-05-19
TLE42994
Block Diagram
2
Block Diagram
I
Q
Current
and
Saturation
Control
BandGapReference
RSO
RRO
SO
SI
Reference
RO
Reset
Control
RADJ
D
GND
AEB03103
Figure 1
Data Sheet
Block Diagram TLE42994G (package PG-DSO-8)
3
Rev. 1.1, 2009-05-19
TLE42994
Block Diagram
TLE 4299
I
Q
Current
and
Saturation
Control
BandGapReference
EN
INH
RSO
RRO
Inhibit
Enable
Control
SO
SI
Reference
RO
Reset
Control
RADJ
D
GND
AEB03104
Figure 2
Data Sheet
Block Diagram TLE42994GM, TLE42994E (packages PG-DSO-14, PG-SSOP-14)
4
Rev. 1.1, 2009-05-19
TLE42994
Pin Configuration
3
Pin Configuration
3.1
Pin Assignment TLE42994G (PG-DSO-8)
Ι
SΙ
RADJ
D
1
2
3
4
8
7
6
5
Q
SO
RO
GND
AEP01668
Figure 3
Pin Configuration (top view)
3.2
Pin Definitions and Functions TLE42994G (PG-DSO-8)
Pin
Symbol
Function
1
I
Input
for compensating line influences, a capacitor to GND close to the IC terminals is
recommended
2
SI
Sense Input
connect the voltage to be monitored;
connect to Q if the sense comparator is not needed
3
RADJ
Reset Threshold Adjust
connect an external voltage divider to adjust reset threshold;
connect to GND for using internal threshold
4
D
Reset Delay Timing
connect a ceramic capacitor to GND for adjusting the reset delay time;
leave open if the reset function is not needed
5
GND
Ground
6
RO
Reset Output
open collector output; internally linked to the output via a 20kΩ pull-up resistor;
leave open if the reset function is not needed
7
SO
Sense Output
open collector output; internally linked to the output via a 20kΩ pull-up resistor;
leave open if the sense comparator is not needed
8
Q
Output
block to GND with a capacitor close to the IC terminals, respecting the values given
for its capacitance CQ and ESR in “Functional Range” on Page 10
Data Sheet
5
Rev. 1.1, 2009-05-19
TLE42994
Pin Configuration
3.3
Pin Assignment TLE42994GM (PG-DSO-14)
RADJ
1
14
SI
D
2
13
I
GND
3
12
GND
GND
4
11
GND
GND
5
10
GND
EN
6
9
Q
RO
7
8
SO
PinConfig_PG-DSO-14.vsd
Figure 4
Pin Configuration (top view)
3.4
Pin Definitions and Functions TLE42994GM (PG-DSO-14)
Pin
Symbol
Function
1
RADJ
Reset Threshold Adjust
connect an external voltage divider to adjust reset threshold;
connect to GND for using internal threshold
2
D
Reset Delay Timing
connect a ceramic capacitor to GND for adjusting the reset delay time;
leave open if the reset function is not needed
3, 4, 5
GND
Ground
connect all pins to PCB and heatsink area
6
EN
Enable
high signal enables the regulator;
low signal disables the regulator;
connect to I if the Enable function is not needed
7
RO
Reset Output
open collector output; internally linked to the output via a 20kΩ pull-up resistor;
leave open if the reset function is not needed
8
SO
Sense Output
open collector output; internally linked to the output via a 20kΩ pull-up resistor;
leave open if the sense comparator is not needed
9
Q
Output
block to GND with a capacitor close to the IC terminals, respecting the values given
for its capacitance CQ and ESR in the table “Functional Range” on Page 10
10, 11, 12 GND
Ground
connect all pins to PCB and heatsink area
13
I
Input
for compensating line influences, a capacitor to GND close to the IC terminals is
recommended
14
SI
Sense Input
connect the voltage to be monitored;
connect to Q if the sense comparator is not needed
Data Sheet
6
Rev. 1.1, 2009-05-19
TLE42994
Pin Configuration
3.5
Pin Assignment TLE42994E (PG-SSOP-14)
RADJ
n.c.
D
GND
EN
n.c.
RO
1
2
3
4
5
6
7
14
13
12
11
10
9
8
SI
I
n.c.
Q
n.c.
n.c.
SO
PINCONFIG_SSOP-14.VSD
Figure 5
Pin Configuration (top view)
3.6
Pin Definitions and Functions TLE42994E (PG-SSOP-14)
Pin
Symbol
Function
1
RADJ
Reset Threshold Adjust
connect an external voltage divider to adjust reset threshold;
connect to GND for using internal threshold
2, 6
n.c.
not connected
leave open or connect to GND
3
D
Reset Delay Timing
connect a ceramic capacitor to GND for adjusting the reset delay time;
leave open if the reset function is not needed
4
GND
Ground
connect all pins to PCB and heatsink area
5
EN
Enable
high signal enables the regulator;
low signal disables the regulator;
connect to I if the Enable function is not needed
7
RO
Reset Output
open collector output; internally linked to the output via a 20kΩ pull-up resistor;
leave open if the reset function is not needed
8
SO
Sense Output
open collector output; internally linked to the output via a 20kΩ pull-up resistor;
leave open if the sense comparator is not needed
9, 10, 12
n.c.
not connected
leave open or connect to GND
11
Q
Output
block to GND with a capacitor close to the IC terminals, respecting the values given
for its capacitance CQ and ESR in the table “Functional Range” on Page 10
13
I
Input
for compensating line influences, a capacitor to GND close to the IC terminals is
recommended
Data Sheet
7
Rev. 1.1, 2009-05-19
TLE42994
Pin Configuration
Pin
Symbol
Function
14
SI
Sense Input
connect the voltage to be monitored;
connect to Q if the sense comparator is not needed
PAD
–
Exposed Pad
attach the exposed pad on package bottom to the heatsink area on circuit board;
connect to GND
Data Sheet
8
Rev. 1.1, 2009-05-19
TLE42994
General Product Characteristics
4
General Product Characteristics
4.1
Absolute Maximum Ratings
Absolute Maximum Ratings 1)
-40 °C ≤ Tj ≤ 150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Max.
VI, VEN,
VSI
-40
45
V
–
VQ, VRO,
VSO
-0.3
7
V
–
VD, VRADJ -0.3
7
V
–
Tj
Tstg
-40
150
°C
–
-50
150
°C
–
VESD,HBM
-2
2
kV
Human Body
Model (HBM)2)
VESD,CDM
-500
500
V
Charge Device
Model (CDM)3)
-750
750
V
Charge Device
Model (CDM)3) at
corner pins
Input I, Enable Input EN, Sense Input SI
4.1.1
Voltage
Output Q, Reset Output RO, Sense Output SO
4.1.2
Voltage
Reset Delay D, Reset Threshold RADJ
4.1.3
Voltage
Temperature
4.1.4
Junction Temperature
4.1.5
Storage Temperature
ESD Absorption
4.1.6
ESD Absorption
4.1.7
4.1.8
1) not subject to production test, specified by design
2) ESD susceptibility Human Body Model “HBM” according to AEC-Q100-002 - JESD22-A114
3) ESD susceptibility Charged Device Model “CDM” according to ESDA STM5.3.1
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Data Sheet
9
Rev. 1.1, 2009-05-19
TLE42994
General Product Characteristics
4.2
Pos.
Functional Range
Parameter
4.2.1
Input Voltage
4.2.2
Output Capacitor’s Requirements
for Stability
4.2.3
Junction Temperature
Symbol
VI
CQ
ESR(CQ)
Tj
Limit Values
Unit
Conditions
Min.
Max.
5.5
45
V
–
22
–
µF
–1)
–
3
Ω
–2)
-40
150
°C
–
1) the minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%
2) relevant ESR value at f = 10 kHz
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
Data Sheet
10
Rev. 1.1, 2009-05-19
TLE42994
General Product Characteristics
4.3
Pos.
Thermal Resistance
Parameter
Symbol
Limit Value
Min.
Typ.
Unit
Conditions
Max.
TLE42994G (PG-DSO-8)
4.3.4
Junction to Soldering Point1)
RthJSP
RthJA
–
–
60
K/W
measured to pin 5
–
113
–
K/W
2)
4.3.6
–
185
–
K/W
Footprint only3)
4.3.7
–
142
–
K/W
300mm2 heatsink area on
PCB3)
4.3.8
–
136
–
K/W
600mm2 heatsink area on
PCB3)
–
–
30
K/W
measured to all GND pins
4.3.5
Junction to Ambient
1)
TLE42994GM (PG-DSO-14)
4.3.9
Junction to Soldering Point1)
RthJSP
RthJA
–
63
–
K/W
2)
4.3.11
–
112
–
K/W
Footprint only3)
4.3.12
–
73
–
K/W
300mm2 heatsink area on
PCB3)
4.3.13
–
65
–
K/W
600mm2 heatsink area on
PCB3)
–
10
–
K/W
–
–
47
–
K/W
2)
4.3.16
–
140
–
K/W
Footprint only3)
4.3.17
–
63
–
K/W
300mm2 heatsink area on
PCB3)
4.3.18
–
53
–
K/W
600mm2 heatsink area on
PCB3)
4.3.10
1)
Junction to Ambient
TLE42994E (PG-SSOP-14)
4.3.14
Junction to Case1)
4.3.15
Junction to Ambient1)
RthJC
RthJA
1) not subject to production test, specified by design
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu).
Data Sheet
11
Rev. 1.1, 2009-05-19
TLE42994
Block Description and Electrical Characteristics
5
Block Description and Electrical Characteristics
5.1
Voltage Regulator
The output voltage VQ is controlled by comparing a portion of it to an internal reference and driving a PNP pass
transistor accordingly. The control loop stability depends on the output capacitor CQ, the load current, the chip
temperature and the poles/zeros introduced by the integrated circuit. To ensure stable operation, the output
capacitor’s capacitance and its equivalent series resistor ESR requirements given in the table “Functional
Range” on Page 10 have to be maintained. For details see also the typical performance graph “Output
Capacitor Series Resistor ESR(CQ) versus Output Current IQ” on Page 15. As the output capacitor also has
to buffer load steps it should be sized according to the application’s needs.
An input capacitor CI is strongly recommended to compensate line influences. Connect the capacitors close to the
component’s terminals.
A protection circuitry prevents the IC as well as the application from destruction in case of catastrophic events.
These safeguards contain an output current limitation, a reverse polarity protection as well as a thermal shutdown
in case of overtemperature.
To avoid excessive power dissipation that could never be handled by the pass element and the package, the
maximum output current is decreased at input voltages above VI = 22 V.
The overtemperature shutdown circuit prevents the IC from immediate destruction under fault conditions (e.g.
output continuously short-circuited) by switching off the power stage. After the chip has cooled down, the regulator
restarts. This leads to an oscillatory behaviour of the output voltage until the fault is removed. However, junction
temperatures above 150 °C are outside the maximum ratings and therefore significantly reduce the IC’s lifetime.
The TLE42994 allows a negative supply voltage. In this fault condition, small currents are flowing into the IC,
increasing its junction temperature. This has to be considered for the thermal design, respecting that the thermal
protection circuit is not operating during reverse polarity conditions.
Supply
II
I
Q
Regulated
Output Voltage
IQ
Saturation Control
Current Limitation
C
CI
Temperature
S hutdown
BlockDiagram_VoltageRegulator.vsd
Figure 6
Data Sheet
Bandgap
Reference
E SR
}
CQ
LOAD
GND
Voltage Regulator
12
Rev. 1.1, 2009-05-19
TLE42994
Block Description and Electrical Characteristics
Electrical Characteristics Voltage Regulator
VI = 13.5 V, -40 °C ≤ Tj ≤150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
5.1.1
Output Voltage
VQ
Limit Values
Unit
Conditions
V
100 µA < IQ < 100 mA
6 V < VI < 18 V
Min.
Typ.
Max.
4.9
5.0
5.1
4.85
5.0
5.15
IQ,max
∆VQ,load
150
400
500
mA
-30
-5
–
mV
5.1.2
100 µA < IQ < 150 mA
6 V < VI < 18 V
5.1.3
Output Current Limitation
5.1.4
Load Regulation
steady-state
5.1.5
Line Regulation
steady-state
∆VQ,line
–
10
25
mV
5.1.6
Dropout Voltage1)
Vdr
–
220
500
mV
VQ = 4.8V
IQ = 1 mA to 100 mA
VI = 6 V
VI = 6 V to 32 V
IQ = 1 mA
IQ = 100 mA
Vdr = VI - VQ
5.1.7
Overtemperature Shutdown
Threshold
Tj,sd
151
–
200
°C
Tj increasing2)
5.1.8
Overtemperature Shutdown
Threshold Hysteresis
Tj,sdh
–
15
–
°C
Tj decreasing2)
fripple = 100 Hz
Vripple = 1 Vpp
IQ = 100 mA
1) measured when the output voltage VQ has dropped 100mV from the nominal value obtained at VI = 13.5V
5.1.9
Power Supply Ripple
Rejection3)
PSRR
–
66
–
dB
2) not subject to production test, specified by design
3) not subject to production test, specified by design
Data Sheet
13
Rev. 1.1, 2009-05-19
TLE42994
Block Description and Electrical Characteristics
5.2
Typical Performance Characteristics Voltage Regulator
Output Voltage VQ versus
Junction Temperature TJ
Output Current IQ versus
Input Voltage VI
01_VQ_TJ.VSD
5,20
02_IQ_VI.VSD
400
350
5,10
300
T j = -40 °C
IQ,max [mA]
V Q [V]
5,00
4,90
VI = 7 V
I Q = 5 mA
4,80
250
T j = 25 °C
T j = 150 °C
200
150
100
4,70
50
4,60
0
-40
0
40
80
120
0
160
10
20
Power Supply Ripple Rejection PSRR versus
ripple frequency fr
T j = 150 °C
0,8
T j = 25 °C
0,7
T j = 150 °C
0,6
60
∆V Q [mV]
PSRR [dB]
70
50
40
T j = 25 °C
0,5
0,4
30
I Q = 10 mA
C Q = 10 µF
0,3
20
ceramic
V I = 13.5 V
0,2
10
V ripple = 0.5 Vpp
0
0,01
T j = -40 °C
0,1
0
0,1
1
10
100
0
1000
10
20
30
40
V I [V]
f [kHz]
Data Sheet
04_DVQ_DVI.VSD
0,9
T j = -40 °C
80
50
Line Regulation ∆VQ,line versus
Input Voltage Change ∆VI
03_PSRR_FR.VSD
90
40
V I [V]
T j [°C]
100
30
14
Rev. 1.1, 2009-05-19
TLE42994
Block Description and Electrical Characteristics
5.3
Load Regulation ∆VQ,load versus
Output Current Change ∆IQ
Output Capacitor Series Resistor ESR(CQ) versus
Output Current IQ
05_DVQ_DIQ.VSD
5
06_ESR_IQ_CORRECTED.VSD
100
VI = 6 V
0
Unstable
Region
ESR(C Q) [Ω ]
10
∆V Q [mV]
-5
-10
T j = -40 °C
T j = 25 °C
-15
T j = 150 °C
C Q = 22 µF
T j = -40..150 °C
1
V I = 6..28 V
Stable
Region
0,1
-20
0,01
-25
0
50
100
0
150
I Q [mA]
50
100
150
I Q [mA]
Dropout Voltage Vdr versus
Junction Temperature Ti
07_VDR_TJ.VSD
300
I Q = 100 mA
250
V DR [mV]
200
150
I Q = 25 mA
100
I Q = 5 mA
50
0
-40
0
40
80
120
160
T j [°C]
Data Sheet
15
Rev. 1.1, 2009-05-19
TLE42994
Block Description and Electrical Characteristics
5.4
Current Consumption
Electrical Characteristics Voltage Regulator
VI = 13.5 V, -40 °C ≤ Tj ≤150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
5.4.1
Parameter
Current Consumption
Iq = II - IQ
5.4.2
Symbol
Iq
Limit Values
Min.
Typ.
Max.
–
–
1
Unit
Conditions
µA
VEN = 0 V
TLE42994GM and
TLE42994E only
Tj = 25 °C
–
65
100
µA
Enable HIGH
IQ = 100 µA
Tj = 25 °C
5.4.3
–
65
105
µA
Enable HIGH
IQ = 100 µA
Tj ≤ 85 °C
5.4.4
–
0.17
0.5
mA
Enable HIGH
IQ = 10 mA
5.4.5
–
0.7
2
mA
Enable HIGH
IQ = 50 mA
Data Sheet
16
Rev. 1.1, 2009-05-19
TLE42994
Block Description and Electrical Characteristics
5.5
Typical Performance Characteristics Current Consumption
Current Consumption Iq versus
Output Current IQ
Current Consumption Iq versus
Output Current IQ (IQ low)
08_IQ_IQ.VSD
6
09_IQ_IQ_IQ LOW.VSD
1
V I = 13.5 V
V I = 13.5 V
0,9
T j = 150 °C
T j = 150 °C
5
0,8
T j = 25 °C
T j = 25 °C
0,7
4
I q [mA]
I q [mA]
0,6
3
2
0,5
0,4
0,3
0,2
1
0,1
0
0
0
50
100
150
0
I Q [mA]
10
20
30
40
50
I Q [mA]
Current Consumption Iq versus
Input Voltage VI
10_IQ _VI.VSD
12
10
I q [mA]
8
6
R LOAD = 100 Ω
4
2
R LOAD = 50 k Ω
0
0
10
20
30
40
V I [V]
Data Sheet
17
Rev. 1.1, 2009-05-19
TLE42994
Block Description and Electrical Characteristics
5.6
Enable Function (only TLE42994GM and TLE42994E)
Electrical Characteristics Voltage Regulator
VI = 13.5 V, -40 °C ≤ Tj ≤150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
5.6.1
Enable OFF Voltage Range
5.6.2
Enable ON Voltage Range
5.6.3
Enable OFF Input Current
5.6.4
Enable ON Input Current
5.7
Symbol
VEN,OFF
VEN,ON
IEN,OFF
IEN,ON
Limit Values
Unit
Conditions
Min.
Typ.
Max.
–
–
0.8
V
–
3.5
–
–
V
–
–
0.5
2
µA
–
3
5
µA
VEN = 0 V
VEN = 5 V
Reset Function
The reset function provides several features:
Output Undervoltage Reset:
An output undervoltage condition is indicated by setting the Reset Output RO to “low”. This signal might be used
to reset a microcontroller during low supply voltage.
Power-On Reset Delay Time:
The power-on reset delay time trd allows a microcontoller and oscillator to start up. This delay time is the time frame
from exceeding the reset switching threshold VRT until the reset is released by switching the reset output “RO” from
“low” to “high”. The power-on reset delay time trd is defined by an external delay capacitor CD connected to pin D
charged by the delay capacitor charge current ID,ch starting from VD = 0 V.
If the application needs a power-on reset delay time trd different from the value given in Item 5.7.8, the delay
capacitor’s value can be derived from the specified values in Item 5.7.8 and the desired power-on delay time:
t rd, new
C D = ---------------- × 100nF
t rd
with
•
•
•
CD: capacitance of the delay capacitor to be chosen
trd,new: desired power-on reset delay time
trd: power-on reset delay time specified in this datasheet
For a precise calculation also take the delay capacitor’s tolerance into consideration.
Data Sheet
18
Rev. 1.1, 2009-05-19
TLE42994
Block Description and Electrical Characteristics
Reset Reaction Time:
The reset reaction time avoids that short undervoltage spikes trigger an unwanted reset “low” signal. The reset
reaction rime trr considers the internal reaction time trr,int and the discharge time trr,d defined by the external delay
capacitor CD (see typical performance graph for details). Hence, the total reset reaction time becomes:
t rr = t rd, int + t rr, d
with
•
•
•
trr: reset reaction time
trr,int: internal reset reaction time
trr,d: reset discharge
Optional Reset Output Pull-Up Resistor RRO,ext:
The Reset Output RO is an open collector output with an integrated pull-up resistor. If needed, an external pull-up
resistor to the output Q can be added. In Table “Electrical Characteristics Reset Function” on Page 22 a
minimum value for the external resistor RRO,ext is given.
Reset Adjust Function
The undervoltage reset switching threshold can be adjusted according to the application’s needs by connecting
an external voltage divider (RADJ1, RADJ2) at pin RADJ. For selecting the default threshold connect pin RADJ to
GND.
When dimensioning the voltage divider, take into consideration that there will be an additional current constantly
flowing through the resistors.
With a voltage divider connected, the reset switching threshold VRT,new is calculated as follows:
R ADJ, 1 + R ADJ, 2
V RT, new = ------------------------------------------ × V RADJ, th
R ADJ, 2
with
•
•
•
VRT,new: the desired new reset switching threshold
RADJ1, RADJ2: resistors of the external voltage divider
VRADJ,th: reset adjust switching threshold given in Table “Electrical Characteristics Reset Function” on
Page 22
Data Sheet
19
Rev. 1.1, 2009-05-19
TLE42994
Block Description and Electrical Characteristics
I
Q
RRO
Int.
Supply
Control
CQ
RO
ID,ch
RRO,ext
Reset
I RO
VDST
VRADJ,th
VDD
optional
Supply
OR
RADJ,1
MicroController
RADJ
I RADJ
GND
optional
ID,dch
D
BlockDiagram_ResetAdjust.vsd
RADJ,2
GND
CD
Figure 7
Data Sheet
Block Diagram Reset Function
20
Rev. 1.1, 2009-05-19
TLE42994
Block Description and Electrical Characteristics
VI
t
t < trr,total
VQ
VRT
1V
t
t rd
VD
V DU
V DRL
t
VRO
V RO,low
t rd
trr,total
trd
t rr,total
t rd
t rr,total
1V
t
Thermal
Shutdown
Figure 8
Data Sheet
Input
Voltage Dip
Undervoltage
Spike at
output
Overload
T i mi n g Di a g ra m_ Re se t . vs
Timing Diagram Reset
21
Rev. 1.1, 2009-05-19
TLE42994
Block Description and Electrical Characteristics
Electrical Characteristics Reset Function
VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
Min.
Typ.
Max.
4.5
4.65
4.8
V
VQ decreasing
Output Undervoltage Reset
5.7.1
Default Output Undervoltage Reset VRT
Switching Thresholds
Output Undervoltage Reset Threshold Adjustment
5.7.2
Reset Adjust
Switching Threshold
VRADJ,th
1.26
1.36
1.44
V
3.5 V ≤ VQ < 5 V
5.7.3
Reset Adjustment Range1)
VRT,range
3.50
–
4.65
V
–
Reset Output RO
5.7.4
Reset Output Low Voltage
VRO,low
–
0.1
0.4
V
1 V ≤ VQ ≤ VRT
no external RRO,ext
5.7.5
Reset Output Internal
Pull-up Resistor to VQ
RRO
10
20
40
kΩ
–
5.7.6
Optional Reset Output External
Pull-up Resistor to VQ
RRO,ext
5.6
–
–
kΩ
1 V ≤ VQ ≤ VRT ;
VRO ≤ 0.4 V
VD
trd
–
–
5
V
–
17
28
35
ms
CD = 100 nF
Reset Delay Timing
5.7.7
Delay Pin Output Voltage
5.7.8
Power On Reset Delay Time
Calculated Value:
trd = CD * VDU / ID,ch
5.7.9
Upper Delay
Switching Threshold
VDU
–
1.85
–
V
–
5.7.10
Lower Delay
Switching Threshold
VDL
–
0.50
–
V
–
5.7.11
Delay Capacitor
Charge Current
ID,ch
–
8.0
–
µA
VD = 1 V
5.7.12
Delay Capacitor
Reset Discharge Current
ID,dch
–
70
–
mA
VD = 1 V
5.7.13
Delay Capacitor
Discharge Time
trr,d
–
1.9
3
µs
Calculated Value:
5.7.14
Internal Reset Reaction Time
–
14
20
µs
5.7.15
Reset Reaction Time
trr,int
trr,total
trr,d = CD*(VDU VDL)/ ID,dch
CD = 100 nF
CD = 0 nF 2)
–
15.9
23
µs
Calculated Value:
trr,total = trr,int + trr,d
CD = 100 nF
1) VRT is scaled linearly, in case the Reset Switching Threshold is modified
2) parameter not subject to production test; specified by design
Data Sheet
22
Rev. 1.1, 2009-05-19
TLE42994
Block Description and Electrical Characteristics
5.8
Typical Performance Characteristics Reset
Undervoltage Reset Switching Threshold VRT
versus Junction Temperature Tj
11_VRT_TJ.VSD
5
12_TRD_TJ.VSD
30
4,9
25
4,8
20
t rd [ m s ]
V RT [V]
Power On Reset Delay Time trd versus
Junction Temperature Tj
4,7
C D = 100 nF
15
10
4,6
5
4,5
0
-40
4,4
-40
0
40
80
120
10
Internal Reset Reaction Time trr,int versus
Junction Temperature Tj
160
Delay Capacitor Discharge Time trr,d versus
Junction Temperature Tj
13_TRRINT _TJ.VSD
14_TRRD_TJ.VSD
2,5
20
2
15
1,5
t rr,d [µs]
t rr,int [µs]
110
T j [°C]
T j [°C]
25
60
160
10
1
0,5
5
0
-40
0
-40
10
60
110
160
60
110
160
T j [°C]
T j [°C]
Data Sheet
10
23
Rev. 1.1, 2009-05-19
TLE42994
Block Description and Electrical Characteristics
5.9
Early Warning Function
The additional sense comparator provides an early warning function: Any voltage (e.g. the input voltage) can be
monitored, an undervoltage condition is indicated by setting the comparator’s output to low.
Sense
Input
Voltage
VSI, High
VSI, Low
t
Sense
Output
High
Low
t
AED03049
Figure 9
Sense Timing Diagram
Electrical Characteristics Early Warning Function
VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Unit
Conditions
1.54
V
–
1.36
1.44
V
–
50
90
130
mV
VSI,hy = VSI,high - VSI,low
-1
-0.1
1
µA
–
Min.
Typ.
Max.
1.34
1.45
1.26
Sense Comparator Input
5.9.1
Sense Threshold High
5.9.2
Sense Threshold Low
5.9.3
Sense Switching Hysteresis
5.9.4
Sense Input Current
Data Sheet
VSI,high
VSI,low
VSI,hy
ISI
24
Rev. 1.1, 2009-05-19
TLE42994
Block Description and Electrical Characteristics
Electrical Characteristics Early Warning Function
VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos.
Parameter
Symbol
Limit Values
Min.
Typ.
Max.
Unit
Conditions
Sense Comparator Output
5.9.5
Sense Output Low Voltage
VSO,low
–
0.1
0.4
V
VSI < VSI,low
VI > 5.5 V
5.9.6
Sense Output Internal
Pull-up Resistor to VQ
RSO
10
20
40
kΩ
–
5.9.7
Optional Sense Output External RSO,ext
Pull-up Resistor to VQ
5.6
–
–
kΩ
VI > 5.5 V
VSO ≤ 0.4 V
no external RSO,ext
5.10
Typical Performance Characteristics Early Warning
Sense Thresholds VSI,high, VSI,low versus
Junction Temperature Tj
15_VSI_T J.VSD
1,45
V SI,high
1,4
1,35
V SI,low
V SI [V]
1,3
1,25
1,2
1,15
1,1
1,05
1
-40
10
60
110
160
T j [°C]
Data Sheet
25
Rev. 1.1, 2009-05-19
TLE42994
Package Outlines
6
Package Outlines
0.1
2)
0.41+0.1
-0.06
0.2
8
5
1
4
5 -0.2 1)
M
B
0.19 +0.06
C
8 MAX.
1.27
4 -0.21)
1.75 MAX.
0.175 ±0.07
(1.45)
0.35 x 45˚
0.64 ±0.25
6 ±0.2
A B 8x
0.2
M
C 8x
A
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Lead width can be 0.61 max. in dambar area
GPS01181
Figure 10
Data Sheet
PG-DSO-8
26
Rev. 1.1, 2009-05-19
TLE42994
Package Outlines
1.75 MAX.
C
1)
4 -0.2
B
1.27
0.64 ±0.25
0.1
2)
0.41+0.10
-0.06
6±0.2
0.2 M A B 14x
14
0.2 M C
8
1
7
1)
8.75 -0.2
8˚MAX.
0.19 +0.06
0.175 ±0.07
(1.47)
0.35 x 45˚
A
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Lead width can be 0.61 max. in dambar area
GPS01230
Figure 11
Data Sheet
PG-DSO-14
27
Rev. 1.1, 2009-05-19
TLE42994
Package Outlines
0.15 M C A-B D 14x
0.64 ±0.25
1
8
1
7
0.2
M
D 8x
Bottom View
3 ±0.2
A
14
6 ±0.2
D
Exposed
Diepad
B
0.1 C A-B 2x
14
7
8
2.65 ±0.2
0.25 ±0.05 2)
0.08 C
8˚ MAX.
C
0.65
0.1 C D
0.19 +0.06
1.7 MAX.
Stand Off
(1.45)
0 ... 0.1
0.35 x 45˚
3.9 ±0.11)
4.9 ±0.11)
Index Marking
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Does not include dambar protrusion
PG-SSOP-14-1,-2,-3-PO V02
Figure 12
PG-SSOP-14
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.
Data Sheet
28
Dimensions in mm
Rev. 1.1, 2009-05-19
TLE42994
Revision History
7
Revision History
Revision
Date
Changes
1.1
2009-05-19
Updated version Data Sheet:
Typing error corrected in Chapter 5.2 in conditions for graph “Output Capacitor
Series Resistor ESR(CQ) versus Output Current IQ” on Page 15: “10µF”
corrected to “22µF”, no change done in specification of electrical parameters
1.0
Data Sheet
2008-12-04
initial version Data Sheet
29
Rev. 1.1, 2009-05-19
Edition 2009-05-19
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2009 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
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