Dual Low Dropout Voltage Regulator TLE 4473 GV55-2 Features • • • • • • • • • • • • • • Stand-by output 190 mA; 5 V ± 2% Main output: 300 mA, 5 V tracked to the stand-by output Low quiescent current consumption Disable function separately for both outputs Wide operation range: up to 42 V Very low dropout voltage 2 independent reset circuits Watchdog Output protected against short circuit Wide temperature range: -40 °C to 150 °C Overtemperature protection Overload protection Green product (RoHS compliant) AEC qualified PG-DSO-12-11 Functional Description The TLE 4473 is a monolithic integrated voltage regulator with two low dropout outputs, a main output Q1 for loads up to 300 mA and a stand by output Q2 providing a maximum of 190 mA. The stand-by regulator transforms an input voltage VI in the range of 5.6 V ≤ VI ≤ 42 V to an output voltage of VQ2 = 5.0 V (±2%). The main output is tracked to the stand by output voltage and provides also 5 V. A versions of this device with 5 V/3.3 V and 5 V/2.6 V are also available, please refer to the data sheet TLE 4473 G V53/ TLE 4473 G V52. The Inhibit input INH1 disables the output Q1 only, whereas Inhibit input INH2 disables both, Q1 and Q2 output. The quiescent current then is 1 µA. The TLE 4473 is designed to supply microprocessor systems and sensors under the severe conditions of automotive applications and therefore is equipped with additional protection functions against overload, short circuit and overtemperature. The device operates in the wide junction temperature range of -40 °C to 150 °C. Type Package Marking TLE 4473 GV55-2 PG-DSO-12-11 (RoHS compliant) TLE4473 GV55-2 Data Sheet 1 Rev. 1.2, 2008-10-28 TLE 4473 GV55-2 The device features a reset with adjustable power on delay for each of the outputs. In addition the output for the microcontroller supply comes up with a watchdog in order to supervise a connected microcontroller Reset and Watchdog Behavior The reset output RO2 is in high-state if the voltage on the delay capacitor CD2 is greater or equal VDU2. The delay capacitor CD2 is charged with the current IDC2 for output voltages greater than the reset threshold VRT2. If the output voltage gets lower than VRT2 (‘reset condition’) a fast discharge of the delay capacitor CD2 sets in and as soon as VD2 gets lower than VDL2 the reset output RO2 is set to low-level. The time for the delay capacitor charge is the reset delay time. For the power-on case the charging process of CD2 starts from 0 V, which leads to the equation: C D2 × V DU2 t D, on = ---------------------------I DC2 (1) for the power-on reset delay time. When the voltage on the delay capacitor has reached VDU2 and reset was set to high, the watchdog circuit is enabled and discharges CD2 with the constant current IDD2. If there is no rising edge observed at the watchdog input, CD2 will be discharge down to VDL2. Then reset output RO2 will be set to low and CD2 will be charged again with the current IDC2 until VD2 reaches VDU2 and reset will be set high again. If the watchdog pulse (rising edge at watchdog input WI) occurs during the discharge period CD2 is charged again and the reset output stays high. After VD2 has reached VDU2, the periodical cycle starts again. The watchdog timing is shown in Figure 1. The maximum duration between two watchdog pulses corresponds to the minimum watchdog trigger time TWI,tr. Higher capacitances on pin D2 result in longer watchdog trigger times: T WI,tr max = 0.34 ms/nF × C D2 (2) If the output voltage Q1 decreases below VRT1 (typ. 4.65 V), the external capacitor CD1 is discharged by the reset generator of the main output. If the voltage on this capacitor drops below VDL1, a reset signal is generated on pin 2 (RO1). If the output voltage rises above the reset threshold, CD1 will be charged with the constant current IDC1. After the power-on-reset time the voltage on the capacitor reaches VDU1 and the reset output will be set high again. The value of the power-on-reset time can be set within a wide range depending of the capacitance of CD1 using the above given equation (1) analogous for Q1. Data Sheet 2 Rev. 1.2, 2008-10-28 TLE 4473 GV55-2 VW Ι t VΙ VQ t T WD, p VD2 t T WI, tr VDU2 VDL2 t WD, L VRO2 T WI, tr = (VDU2 -VDL2 ) Ι DD2 C D2 ; T WD, p = (VDU2 -VDL2 ) (Ι DC2 + Ι DD2 ) Ι DC2 x Ι DD2 C D2 ; t WD, L = t (VDU2 -VDL2 ) Ι DC2 t C D2 AED03099_4473 Figure 1 Data Sheet Watchdog Timing Schedule 3 Rev. 1.2, 2008-10-28 TLE 4473 GV55-2 TLE 4 4 7 3 GV5 5 -2 V Bat Q2 4 7 I 10 µF CI 100 nF Ove rte mp e ra tu re Sh u td o w n Ba n d g a p R e fe re n ce Ig n itio n 9 IN H 2 C u rre n t a n d Sa tu ra tio n C o n tro l, Ove rcu rre n t Pro te ctio n In h ib it µC Su p p ly 4 .7 kΩ R e se t Ge n e ra to r Wa tch d o g R O2 3 µC R e se t WI 1 Wa tch d o g (fro m µC ) D2 11 100 nF Q1 6 10 µF C u rre n t a n d Sa tu ra tio n C o n tro l, Ove rcu rre n t Pro te ctio n µC 8 IN H 1 e .g . Se n so r Su p p ly 4 .7 kΩ R e se t Ge n e ra to r e .g . Se n so r R e se t (to µC ) R O1 2 In h ib it D1 10 100 nF 12 TL E4 4 7 3 G V5 5 -2 _ BL O CKDIAG RAM .VSD Figure 2 Data Sheet GN D Block Diagram with Typical External Components 4 Rev. 1.2, 2008-10-28 TLE 4473 GV55-2 Application Information The output voltage is divided by a voltage divider and compared to an internal reference voltage. A regulation loop controls the Q2 output in order to achieve a stable output voltage at the Q2 pin. A second regulation loop controls the Q1 output. The reference voltage for the Q1 is the regulated Q2 potential (tracking regulator). Figure 2 includes the components needed for a typical application. Maintaining the stability of the regulation loops requires a capacitor of 10 µF both outputs. A maximum ESR of 5 Ω is permissible for the Q2 output, while the Q1 output requires a capacitor with a maximum ESR of 3 Ω. For both output blocking capacitors it is recommended to use tantalum types in order to stay in the permissible ESR range over the full operating temperature range. At the input of the regulator a capacitor is necessary for compensating line influences. A minimum of 100 nF (ceramic capacitor) is recommended. In addition for compensation of long input lines of several meters an electrolytic input capacitor of 47 µF … 220 µF should be placed at the input. TLE 4473 GV55-2 (P-DSO-12) Figure 3 Data Sheet 1 12 GND RO1 2 11 D2 RO2 3 10 D1 Q2 4 9 INH2 N.C. 5 8 INH1 Q1 6 7 I TL E4 4 7 3 GV5 5 -2 _ PIN OU T.VSD WI Pin Configuration (top view) 5 Rev. 1.2, 2008-10-28 TLE 4473 GV55-2 Table 1 Pin Definitions and Functions Pin No. Symbol Function 1 WI Watchdog input; input for watchdog pulses, positive edge triggered. 2 RO1 Reset and watchdog output for Q1; open collector output. Connect to pull-up resistor. 3 RO2 Reset output 2; open collector output. Connect to pull-up resistor. 4 Q2 Stand-by regulator output voltage; block to GND with a capacitor CQ2 ≥ 10 µF, ESR < 5 Ω at 10 kHz. 5 N.C. Internally not connected; connect to GND. 6 Q1 Main regulator output voltage; output voltage tracked to Q2 voltage; block to GND with a capacitor CQ1 ≥ 10 µF, ESR < 3 Ω at 10 kHz 7 I Input voltage; block to ground directly at the IC with a ceramic capacitor. 8 INH1 Inhibit input 1; low level disables Q1, integrated pull-down resistor. 9 INH2 Inhibit input 2; low level at INH2 and INH1 disables Q2 and Q1, integrated pull-down resistor. 10 D1 Reset Delay 1; connect to ground via a capacitor to set reset delay for Q1. 11 D2 Reset Delay 2; connect to ground via a capacitor to set reset delay and watchdog timing for Q2. 12 GND Ground; connect to heatslug. Heatslug Data Sheet Interconnect with PCB heatsink area and GND. 6 Rev. 1.2, 2008-10-28 TLE 4473 GV55-2 Table 2 Absolute Maximum Ratings -40 °C < Tj < 150 °C Parameter Symbol Limit Values Unit Remarks Min. Max. VI II -42 45 V – – – mA Internally limited VQ2 IQ2 -0.3 18 V – – – mA Internally limited VQ1 IQ1 -0.3 18 V – – – mA Internally limited VINH1 IINH1 -42 45 V – -2 2 mA – VINH2 IINH2 -42 45 V – -2 2 mA – VRO1 IRO1 -0.3 18 V – – – mA Internally limited VRO2 IRO2 -0.3 18 V – – – mA Internally limited VD1 ID1 -0.3 7 V – -5 5 mA – VD ID -0.3 7 V – -5 5 mA – Input I Voltage Current Stand-by Output Q2 Voltage Current Main Output Q1 Voltage Current Inhibit Input INH1 Voltage Current Inhibit Input INH2 Voltage Current Reset Output RO1 Voltage Current Reset Output RO2 Voltage Current Reset Delay D1 Voltage Current Reset Delay D2 Voltage Current Data Sheet 7 Rev. 1.2, 2008-10-28 TLE 4473 GV55-2 Table 2 Absolute Maximum Ratings (cont’d) -40 °C < Tj < 150 °C Parameter Symbol Limit Values Unit Remarks Min. Max. VRADJ IRADJ -0.3 7 V – -5 5 mA – Tj Tstg -50 150 °C – -50 150 °C – Unit Remarks Watchdog Input WI Voltage Current Temperatures Junction temperature Storage temperature Table 3 Operating Range Parameter Symbol Limit Values Min. Max. 5.6 42 V – -40 150 °C – – 4 K/W – Junction ambient Rthj-pin Rthj-a – 115 K/W PCB Heat Sink Area 0 mm2 1) Junction ambient Rthj-a – 100 K/W PCB Heat Sink Area 100 mm2 1) Junction ambient Rthj-a – 60 K/W PCB Heat Sink Area 300 mm2 1) Junction ambient Rthj-a – 48 K/W PCB Heat Sink Area 600 mm2 1) Input voltage Junction temperature VI Tj Thermal Resistances PG-DSO-12-11 Junction pin 1) Package mounted on PCB 80 × 80 × 1.5 mm3; 35µ Cu; 5µ Sn; zero airflow. Note: In the operating range the functions given in the circuit description are fulfilled. Integrated protection functions are designed to prevent IC destruction under fault conditions. Protection functions are not designed for continuous repetitive operation. Data Sheet 8 Rev. 1.2, 2008-10-28 TLE 4473 GV55-2 Table 4 Electrical Characteristics VI1 = 13.5 V; VINH1 = VINH2 = 5 V; -40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values Min. Typ. Max. Unit Test Condition Stand-by Regulator Output Q2 Output voltage VQ2 4.90 5.0 5.10 V 1 mA < IQ2 < 190 mA; 6 V < VI < 28 V Output current limitation IQ2 200 300 650 mA VQ2 = 4.5 V – 200 600 mV IQ2 = 100 mA1) Output drop voltage; VDRQ2 VDRQ1 = VI1 - VQ1 Load regulation ∆VQ2,Lo – 15 50 mV 1 mA < IQ2 < 190 mA Line regulation ∆VQ2,Li – 5 20 mV – 65 – dB IQ2 = 1 mA; 6 V < VI < 28 V fr = 100 Hz; Vr = 1 Vpp – 170 220 µA – – 245 µA – – 280 µA – 4.5 5 mA – 0.1 1 µA – 0.1 20 µA Power Supply Ripple PSRR Rejection Current Consumption Quiescent current; stand-by Iq = II - IQ2 Quiescent current; inhibited Data Sheet Iq Iq 9 IQ2 = 500 µA; Tj = 25 °C; VINH1 < VINH1 OFF (Q1 off) IQ2 = 500 µA; Tj = 85 °C; VINH1 < VINH1 OFF (Q1 off) IQ2 = 500 µA; VINH1 < VINH1 OFF (Q1 off) IQ2 = 100 mA; VINH1 < VINH1 OFF (Q1 off) VINH1 = VINH2 = 0 V; Tj < 85 °C VINH1 = VINH2 = 0 V Rev. 1.2, 2008-10-28 TLE 4473 GV55-2 Table 4 Electrical Characteristics (cont’d) VI1 = 13.5 V; VINH1 = VINH2 = 5 V; -40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values Unit Test Condition Min. Typ. Max. – – 2.3 V 0.65 – – V -1 3.2 6 µA Inhibit Input INH2 Turn-on Voltage Turn-off Voltage H-input current VINH2 ON VINH2 OFF IINH2 ON VQ2 on VQ2 off VINH2 = 5.0 V (see Page 13) L-input current IINH2 OFF -1 0.1 1 µA 0 V < VINH2 < 0.8 V Watchdog and Reset Timing D2 IDC2 IDD2 VDU2 6.5 9.0 14.0 µA 2.0 3.5 5.0 µA VD2 = 1 V VD2 = 1 V 1.5 1.85 2.4 V – Lower timing threshold VDL2 0.3 0.45 0.6 V – Saturation Voltage VD2,SAT TWI,tr – – 100 mV 34 42 51 ms VQ2 < VRT2 CD2 = 100 nF TRD2 Trr 15 20 25 ms – – 5.0 µs CD2 = 100 nF CD2 = 100 nF VRT2 VRT2/VQ2 VR2HEAD 4.55 4.65 4.8 V – 90 93 96 % – 200 350 500 mV VQ2 - VRT2 Reset output sink current IRO2 1.0 – – mA Reset output low voltage VRO2L – 0.15 0.3 V Reset high voltage VRO2H 4.5 – – V VQ2 = 5 V, VD2 = 0 V; VRO2 = 0.3 V VQ2 ≥ 1 V; IRO2 = 1 mA RRO2,ext = 4.7 kΩ Charge current Discharge current Upper timing threshold Watchdog trigger time Reset delay time Reset reaction time Reset Output RO2 Reset switching threshold Reset threshold headroom Data Sheet 10 Rev. 1.2, 2008-10-28 TLE 4473 GV55-2 Table 4 Electrical Characteristics (cont’d) VI1 = 13.5 V; VINH1 = VINH2 = 5 V; -40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values Min. Typ. Unit Test Condition Max. Main (Tracked) Regulator Output Q1 Output voltage VQ1 5.125 V 1 mA < IQ1 < 200 mA; 6 V < VI < 28 V Output voltage tracking accuracy -25 ∆VQ = VQ2 - VQ1 5 25 mV 1 mA < IQ1 < 200 mA; 6 V < VI < 28 V Output voltage tracking accuracy -25 ∆VQ = VQ2 - VQ1 5 25 mV 1 mA < IQ1 < 300 mA; 8 V < VI < 28 V Output current limitation IQ1 350 500 – mA VQ1 = 4.5 V Output drop voltage VDRQ1 = VI - VQ1 VDRQ1 – 300 600 mV IQ1 = 200 mA1) Load regulation ∆VQ1,Lo – 5 50 mV 5 mA < IQ1 < 300 mA Line regulation ∆VQ1,Li – 5 25 mV – 65 – dB IQ1 = 5 mA; 6 V < VI < 28 V fr = 100 Hz; Vr = 1 Vpp Iq – 10 20 mA Iq – 250 500 µA – – 2.3 V 0.7 – – V H-input current VINH1 ON VINH1 OFF IINH1 ON -1 3.5 5 µA 3.0 V < VINH1 < 5 V; (see Page 14) L-input current IINH1 OFF -1 0.1 1 µA 0 V < VINH1 < 0.8 V Power Supply Ripple PSRR Rejection 4.875 5.0 Current Consumption Quiescent current; Iq = II - IQ1 - IQ2 Quiescent current; Iq = II - IQ1 - IQ2 IQ1 = 300 mA; IQ2 = 500 µA; VQ1 and VQ2 on IQ2 = IQ1 = 500 µA; VQ1 and VQ2 on Inhibit Input INH1 Turn-on Voltage Turn-off Voltage Data Sheet 11 VQ1 on VQ1 off Rev. 1.2, 2008-10-28 TLE 4473 GV55-2 Table 4 Electrical Characteristics (cont’d) VI1 = 13.5 V; VINH1 = VINH2 = 5 V; -40 °C < Tj < 150 °C; unless otherwise specified Parameter Symbol Limit Values Unit Test Condition Min. Typ. Max. IDC1 VDU1 4.0 8.0 14.0 µA VD1 = 1 V 1.6 1.8 2.2 V – Lower timing threshold VDL2 0.3 0.4 0.6 V – Saturation Voltage VD1,SAT TRD1 Trr – – 100 mV 14 20 30 ms – – 10 µs VQ1 < VRT1 CD1 = 100 nF CD1 = 100 nF VRT1 VRT1/VQ1 VR1HEAD 4.5 4.65 4.8 V – 90 93 96 % – 200 350 500 mV VQ1 - VRT1 Reset output sink current IRO1 1.0 – – mA Reset output low voltage VRO1L – 0.15 0.3 V Reset output high voltage VRO1H 4.5 – – V VQ1 = 5.0 V; VQ2 = 5.0 V; VD1 = 0 V; VRO1 = 0.3 V VQ1 ≥ 1 V IRO1 = 1 mA RRO1,ext = 4.7 kΩ Reset Timing D1 Charge current Upper timing threshold Reset delay time Reset reaction time Reset Output RO1 Reset switching threshold Reset threshold headroom 1) Drop voltage = VI - VQ (measured when the output voltage has dropped 100 mV from the nominal value obtained at 13.5 V input) Data Sheet 12 Rev. 1.2, 2008-10-28 TLE 4473 GV55-2 Typical Performance Characteristics Output Voltage VQ2 versus Input Voltage VI VQ2 Output Voltage VQ2 versus Junction Temperature TJ AED03353.VSD 8 V VQ2 RLoad = 50 Ω VINH2 = 5 V 7 AED03352.VSD 5.15 V 5.10 6 5 5.05 4 5.00 3 2 4.95 1 0 0 1 2 3 4 5 6 4.90 -40 V 8 0 40 80 °C VI Tj Reset Thresholds VRT1, VRT2 versus Junction Temperature TJ VRT1, VRT2 INH2 Input Current versus Inhibit Voltage AED03354.VSD 4.80 V 160 IINH2 AED03351.VSD 8 µA 7 4.75 6 5 4.70 4 4.65 3 2 4.60 1 4.55 -40 0 40 80 °C 0 160 Tj Data Sheet 0 1 2 3 4 5 6 V 8 VINH2 13 Rev. 1.2, 2008-10-28 TLE 4473 GV55-2 INH1 Input Current versus Inhibit Voltage IINH1 AED03350.VSD 8 µA 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 V 8 VINH1 Data Sheet 14 Rev. 1.2, 2008-10-28 TLE 4473 GV55-2 5˚±3˚ -0.035 7.5 ±0.1 1) 0.25 +0.075 2.6 MAX. B 0.8 (Mold) (1.55) 6.4 ±0.1 1) A (Body) 0 +0.1 STANDOFF 2.35 ±0.1 Package Outline 10.3 ±0.3 0.1 0.25 B 5x 1 = 5 CAB 7 (4.4 Mold) 12 M (1.8 Mold) 12x 0.25 0.4 +0.13 5.1 ±0.1 (Metal) 7 12 1.6 ±0.1 (Metal) 4.2 ±0.1 (Metal) 1 Index Marking 1 6 7.8 ±0.1 6 1 Heatslug (Heatslug) GPS09349 Figure 4 1) Does not include plastic or metal protrusion of 0.15 max. per side PG-DSO-12-11 (Plastic Dual Small Outline) Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Dimensions in mm SMD = Surface Mounted Device Data Sheet 15 Rev. 1.2, 2008-10-28 TLE 4473 GV55-2 Revision History Version Date Changes Rev. 1.2 2008-10-28 Modification according to PCN No. 2007-117-A: • “Watchdog and Reset Timing D2” on Page 10: Lower timing threshold VDL2: Max limit change to 0.6V (was 0.5V) and typ. limit change to 0.45V (was 0.4V). The change does not impact watchdog or reset timing limits Rev. 1.1 2007-12-19 Modification according to PCN No. 2007-117-A: • Page 9: Quiescent current Iq; inhibited (VINH1 = VINH2 = 0 V; Tj < 150 °C): Max. limit changed to 20µA (was 15µA). Rev 1.0 Data Sheet 2006-12-21 Initial version final datasheet 16 Rev. 1.2, 2008-10-28 Edition 2008-10-28 Published by Infineon Technologies AG 81726 München, Germany © Infineon Technologies AG 2008. All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. 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