L9230 SPI CONTROLLED H-BRIDGE PRELIMINARY DATA ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ OPERATING SUPPLY VOLTAGE 5V TO 28V TYPICAL RDSon = 150 mΩ FOR EACH OUTPUT TRANSISTOR (AT 25°C) CONTINOUS DC LOAD CURRENT 5A (Tcase < 100 °C) OUTPUT CURRENT LIMITATION AT TYP. 6A SHORT CIRCUIT SHUT DOWN FOR OUTPUT CURRENTS OVER 8A LOGIC- INPUTS TTL/CMOS-COMPATIBLE OPERATING-FREQUENCY UP TO 30 kHz OVER TEMPERATURE PROTECTION SHORT CIRCUIT PROTECTION UNDERVOLTAGE DISABLE FUNCTION DIAGNOSTIC BY SPI OR STATUS-FLAG (CONFIGURABLE) ENABLE AND DISABLE INPUT SO20 POWER PACKAGE PowerSO20 BARE-DIE ORDERING NUMBERS: L9230 L9230-DIE1 The H-Bridge is protected against over temperature and short circuits and has an under voltage lockout for all the supply voltages ”VS” (Main DC power supply). All malfunctions cause the output stages to go tristate. DESCRIPTION The H-Bridge contains integrated free-wheel diodes. In case of free-wheeling condition, the lowside transistor is switched on in parallel of its diode to reduce the current injected into the substrate. The L9230 is an SPI controlled H-Bridge, designed for the control of DC and stepper motors in safety critical applications and under extreme environmental conditions. Switching in parallel is only allowed, if the voltagelevel of the according output-stage is below the ground-level.In this case it must be ensured, that the upper transistor is switched off. ■ BLOCK DIAGRAM VS UNDERVOLTAGE VS INTERNAL 5V SUPPLY IN1 IN2 GATE CONTROL 1 OVERCURRENT HIGH-SIDE DI OUT1 GATE CONTROL 2 EN OUT2 LOGIC DMS SF/SCK OVER TEMPERATURE OVERCURRENT LOW-SIDE SS SI SO MAXIMUM CURRENT LIMITATION GND D01AT470A March 2003 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/25 L9230 PIN FUNCTION N° Pin Description 1 GND 2 SCK/SF Ground 3 IN1 Input 1 SPI-Clock/Status-flag 4 VS Supply voltage 5 VS Supply voltage 6 OU1 7 OU1 Output 1 8 SO serial out 9 SI serial in Output 1 10 GND Ground 11 GND Ground 12 DMS Diagnostic-Mode selection (+ Supply Voltage for SPI-Interface) 13 EN 14 OU2 Output 2 15 OU2 Output 2 16 VS Supply voltage 17 SS Slave select 18 DI Disable 19 IN2 Input 2 20 GND Ground Enable PIN CONNECTION (Top view) GND 1 20 GND SCK 2 19 IN2 IN1 3 18 DI VS 4 17 SS VS 5 16 VS OU1 6 15 OU2 OU1 7 14 OU2 SO 8 13 EN SI 9 12 DMS 10 11 GND GND D01AT471 2/25 L9230 ABSOLUTE MAXIMUM RATINGS The integrated circuit must not be destroyed by use at the limit values. Each limit value can be used, as long as no other limit is violated. Voltage reference point: All values are, if not otherwise stated, relative to ground. Direction of current flow: Current flow into a pin is positive. Rise-, fall- and delaytimes: If not otherwise stated, all rise times are between 10% and 90%, fall times between 90% and 10% and delay times at 50% of the relevant steps. Symbol VS Parameter Supply voltage VLI Logic inputs IN1, IN2, DI, EN, SS, SI, SCK,DMS ILI Logic inputs IN1, IN2, DI, EN, SS, SI, SCK,DMS VLO Logic outputs SF, SO Max. Unit static destruction proof Test Condition -1 40 V dynamic destruction proof t <0.5s (single pulse, Tj < 85°C) -2 40 V -0.5 7 V -20 mA 7 V Max. Unit +150 +175 °C °C R ≥ 10kΩ Min. Typ. -0.5 THERMAL DATA Symbol Tj Parameter Test Condition Junction temperature Min. Typ. -40 dynamic t < 1 s Tstg Storage temperature -55 +125 °C Tamb Ambient temperature -40 +125 °C 3 °C/W Rth j-case Tj_sd Thermal resistance junction to case (2) Thermal Shutdown Junction Temperature Threshold 165 175 Min. Typ. °C ELECTRICAL CHARACTERISTCS ( Tj = -40 to +150°C; VS = 5 to 28V) Symbol Parameter Test Condition Max. Unit 28 V 40 V 4.7 5 V Switch OFF voltage 4.5 5 V Switch ON voltage 4.7 5 V Hysteresis 200 Power Supply VS Supply Voltage Static Condition 5 Dynamic Condition (t < 500ms) Undervoltage Shutdown IS Supply current (at least down to 2.5V) (1) f = 0 kHz, IO = 0 A f = 20kHz, IO = 0 A mV 13 30 mA mA Note: 1. For supply voltages down to 2.5V the output stages are in tristate condition and the status flag is set to low. Below 2.5V the device operates in undefined condition 2. Guaranteed by design and package characterization 3/25 L9230 ELECTRICAL CHARACTERISTCS ( Tj = -40 to +150°C; VS = 5 to 28V) (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit 1 1.5 2 V -200 -125 Logic inputs VI Logic Input Voltage IN1, IN2, DI, EN II Logic Input Current IN1, IN2, DI VI ≤ 1V IEN Input Current EN VIEN ≥ 2V tdt Detection Time EN, DI µA 75 100 µA 3 4 µs Power Outputs (OUT1, OUT2) RS Switch on Resistance LS ROUT-Vs, VS > 5 V 150 250 mΩ Switch on Resistance HS ROUT-GND, VS > 5 V 150 250 mΩ Current Limitation Peak value controlled inductive load L = 0,8 to 5 mH resistive load R = 0,8 to 1.8 Ω |IOU|max |IOU|max Switch-off Current -40 °C < Tj < 165 °C Tj < 175 °C 5.5 6 2.5 7.7 A A ta Switch-off time (2) 12 17 22 µs tb Blanking time (2) 8 11.5 15 µs 1.4 1.5 1.6 ta/tb Tracking (2) |IOUK| Short circuit detection current (1) ∆|IOUK| Short Circuit Current Trecking (1) see figure 1 5.5 11 1600 A mA t Reactivation time after internal shut down (2) Overcurrent- or overtemperature shut down to reactivation of the output stage 1 ms IL Leakage Current Output stage switched off 1 mA 2 V 100 ns VFD trr Free-wheel diode forward voltage IO = 3A, VS = 0V Free-wheel diode reverse recovery time (2) VSFHigh Output„high“ (SF not set) (*) VS = 5V, RPull_up = 27KΩ |Iou| max Switch OFF Current Tj = -40 to 165°C Tj = < 175°C 4.1 V 6 A 2.5 A µA ISF Output„high“ (SF not set) (2) VSF = 5V ISF Output„low“ (SF set) (3 ) VSF = 1V 300 µA VSF = 0.5V 100 µA VSF = 0.8V 500 µA 4/25 20 L9230 ELECTRICAL CHARACTERISTCS ( Tj = -40 to +150°C; VS = 5 to 28V) (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit 2 30 kHz 5 30 kHz 3 5 µs 3 5 µs 0.4 1 µs 3 4 µs 15 ms 15 µs 100 µA Timing f PWM Frequency fS Switching Frequency during current limitation min. operating time 10µs tdon Output ON-delay IN1 --> OUT1 or IN2 --> OUT2 tdoff Output OFF-delay tr, tf Output rise-, fall Time OUT1H--> OUT1L, OUT2H--> OUT2L, IOUT = 3 A OUT1L--> OUT1H, OUT2L--> OUT2H tddis Disable Delay Time DIn --> OUTn, En --> OUTn tdp Power on Delay Time VS = on --> output stage active Delay time for fault detection |∆I| Effect of reverse current at power supply 0.2 5 4,5V < VDMS < 5,5V - IVs < 3A ∆I for ISI, ISO, ISS, ISCK, IIN1, IIN2, IEN,IDI (*) For lower pull up resistances than 27kΩ the specified value of xxxV (minimum) is guaranteed by design Note: 1. In case of SC OUTx to Vs the switch off current is always higher than the start value of current regulation (∆|IOUK| = |IOUK| - |IOUmax| 2. Guaranteed by design 3. Value is tested down to 6V. For supply voltage below 6V on increased current can be fed back in the device via a protection path 5/25 L9230 Figure 1. Output delay time INn 50% 50% tdoff tdon 90% OUTn 10% D01AT472 Figure 2. Disable delay time DIn 50% tddis OUTn 10% Z D01AT473 Figure 3. Output switching time 90% 90% OUTn 10% tf 6/25 tr D01AT474 L9230 Figure 4. LOAD CURRENT CURRENT LIMITATION OVERCURRENT >8A typ 6.6A A CONTROL SIGNAL STATUS FLAG OVERCURRENT DETECTION DETAIL A 6.6A ta tb ta = SWITCH_OFF TIME IN CURRENT LIMITATION tb = CURRENT LIMITATION BLANKING TIME D01AT475 Figure 5. Temperature-depending current-limitation Maximum rating for junction temperature Overtemperature switch-off Switch-off current in case of current limitation For 165°C < Tj < 175°C the maximum current decreases from Imax for < 1s 175°C > 175°C 6,6A ± 1,1A Tj < 165°C Imax. = 6,6A ± 1,1A to Imax. = 2,5A ± 1,1A. Tolerance-range of temperature-dependent current-reduction 6.6A Range of Overtemperature switch-off 2.5A 165°C 175°C Tj 7/25 L9230 ELECTRICAL CHARACTERISTICS (continued) SPI INTERFACE The timing of L9230 is defined as follows: - The change at output (SO) is forced by the rising edge of the SCK signal. - The input signal (SI) is taken over on the falling edge of the SCK signal. - SS = active without any clocks at SCK is not allowed - The data received during a writing access is taken over into the internal registers on the rising edge of the SS signal, if exactly 16 SPI clocks have been counted during SS = active. Figure 6. 10 9 SS 11 2 3 1 SCK 8 12 4 SO tristate 5 SI 7 Bit (n-3) Bit (n-4)...1 Bit 0; LSB 6 MSB IN Bit (n-2) Bit (n-3) Bit (n-4)...1 LSB IN n = 16 ELECTRICAL CHARACTERISTCS ( continued) Symbol Parameter Test Condition Min. Typ. Max. Unit 1 V Input SCK (SPI clock input 4.5V < DMS < 5.5V) VSCKL Low Level VSCKH High Level 2 ∆VSCK Hysteresis 0.1 CSCK Input Capacity 8/25 V 0.4 V 10 pF L9230 ELECTRICAL CHARACTERISTICS (continued) Symbol -ISCK Parameter Input Current Test Condition Min. Pull up current source connected to VS Typ. Max. Unit 20 50 µA 1 V Input SS (Slave select signal) VSSL Low Level L9230 is selected VSSH High Level 2 ∆VSS Hysteresis 0.1 CSS Input Capacity -ISS Input Current Pull up current source connected to VDD V 20 0.4 V 10 pF 50 µA 1 V Input SI (SPI data input) VSIL Low Level VSIH High Level 2 ∆VSI Hysteresis 0.1 CSI Input Capacity -ISI Input Current Pull up current source connected to VDD V 20 0.4 V 10 pF 50 µA 0.4 V Output SO (Tristate output of the L9230 (SPI output); On active reset (DI) output SO is in tristate.) VSOL Low Level ISO = 2mA VSOH High Level ISO = -2mA CSO Capacity Capacity of the pin in tristate ISO Leakage Current In tristate VVDD - 0.75 -10 V 10 pF 10 µA 0.8 V V 10 mA Input DMS (Supply-Input for the SPI-Inteface and Selection Pin for SPI- or SF-Mode) Vi Ic Input Voltage Input Current SPI-Mode Status-Flag-Mode 3.5 SPI-Mode Timing t cyc Cycle-Time (referred to master) 200 ns t lead Enable Lead Time (referred to master) 100 ns t lag Enable Lag Time (referred to master) 150 ns 9/25 L9230 Symbol Parameter Test Condition Min. Typ. Max. Unit 40 150 ns ns tv Data Valid CL = 40pF Data Valid CL = 200pF (referred to L9230) t su Data Setup Time (referred to master) 50 ns th Data Hold Time (referred to master) 20 ns t dis Disable Time (referred to L9230) t dt Transfer Delay (referred to master) 150 ns t SCKH Serial clock high time (referred to master) 50 µs t SCKL Access time (referred to master) 8.35 ns Clock inactive before chipselect becomes valid 200 ns Clock inactive after chipselect becomes valid 200 ns 20 ns V V t rs rise-, fall time 100 Load on SO 50pF ns DIAGNOSTIC Diagnostic Threshold (Open Load Detection DMS > 4,5V, EN < 0,8V) VOUT1 VOUT2 Load is available 0.8 0.8 VOUT1 VOUT2 Load is missing 1 IOUT2 -IOUT1 tD 10/25 Diagnostic Current DMS > 4.5V, EN < 0.8V DMS > 4.5V, EN < 0.8V Tracking Diagnostic Current IOUT1 / IOUT2 Delay Time VS 0.8 V V µA µA 700 1000 1000 1500 1300 2000 1.4 1.5 1.6 30 100 ms L9230 TRUTH TABLE Pos. SF 3) DI EN IN1 IN2 OUT1 OUT2 1. forward L H H L H L H 2. reverse L H L H L H H 3. Free-wheeling low L H L L L L H 4. Free-wheeling high L H H H H H H 5. Disable H X X X Z Z L 6. Enable X L X X Z Z L 7. IN1 disconnected L H Z X H X H 8. IN2 disconnected L H X Z X H H 9. DI disconnected Z X X X Z Z L 10. EN disconnected X Z X X Z Z L 11. Current limit. active L H X X Z Z H 12. Undervoltage 1.) X X X X Z Z L 13. Overtemperature 2.) X X X X Z Z L 14. Overcurrent 2.) X X X X Z Z L 1.) 2.) SPI 4) DIA_REG See Page 17 In case of undervoltage tristate and status-flag are reset automatically. Whenever overcurrent or overtemperature is detected, the fault is stored (i.e. status-flag remains low). The tristate conditions and the status-flag 3) are reset via DI or EN. L = Low H = High X = High or Low Z = High impedance (all output stage transistors are switched off in static state. For more inform. see next page ) Overcurrent: IOUT1,2 >8,0 A Overtemperature: Tj >175°C Undervoltage: VVs-GND <5.0 V 3.) If Mode „Status-Flag“ is selected (see 1.5) 4.) If Mode „SPI-Diagnosis is selected (see 1.5) (at least down to 2,5V) 11/25 L9230 Description of the state „Z“ The state „Z“ has, depending on the previous operating condition different meaning. 1. dynamical I. e. the inductive load is current carrying and is switched off according to Pos. 5, 6, 9, 10, 11, 12, 13, or 14 of the truth table a.) All output stage transistors are switched off. b.) The current flow is continued via the free wheeling diodes. c.) Free wheeling is detected by a negative voltage-level at OUn. d.) Switch on of the parallel-transistor of the current carrying diode. f.) Free wheeling is finshed, if the voltage-level on OUn is positive again. 2. statical g.) all output-stages switched off. Figure 7. CURRENT CARRYNG FREE WHEELING HIGH IMPEDANCE IVS -IGND ILOAD VOUn VSVS-VDS Zº -VS 12/25 Z D01AT478 L9230 DIAGNOSTIC The Diagnosis-Mode can be selected between SPI-Diagnosis and Status-Flag Diagnosis. The choise of the Diagnosis-Mode is selected by the voltage-level on pin 12 (DMS Diagnosis Mode Selection). DMS = GND Status-Flag DMS = Vcc SPI-Diagnostic For the connection of pins SI, SO, SS and SCK/SF see Fig. 10 respectively Fig. 11. Status-Flag The Status-Flag showes the condition „tristate“. At the following fault-cases the output-stages switches in tristate and set the status-flag from high to low. - Short circuit of OUT1 or OUT2 against VS or GND - Short circuit between OUT1 and OUT2 - Overcurrent - Overtemperature - Undervoltage on VS In cause of short circuit or overcurrent, the fault will be stored. The output stage switches in tristate and the status-flag is set from high level to low-level if the specified value is exceeded. If the voltage level changes from high to low on DI or from low to high on EN, the output stage switches on again and the status-flag is reset to high-level. In cause of overtemperature the fault will be stored. The output stage switches in tristate and the status-flag is set from high level to low-level if the specified value is exceeded. the voltage level changes from high to low on DI or from low to high on EN, the output stage switches on again and the status-flag is reset to high-level. In cause of undervoltage on VBatt the output stage switches in tristate and the status-flag is set from high level to low-level if the specified value is fallen. If the voltage has risen about the specified value again, the output stage switches on again and the status-flag is reset to high-level. The maximum current which can flow under normal operating conditions is limited to typical Imax. = 6,6A . When the maximum current value is reached, the output stages are switched tristate for a fixed time. According to the time-constant the current decreases exponentially until the next switch-on occurs. At the end if the fixed time the output stage switches on again and the status-flag is reset to high-level. 13/25 L9230 SPI-INTERFACE General Discription The serial SPI interface establishes a communication link between L9230 and the systems microcontroller. L9230 always operates in slave mode whereas the controller provides the master function. The maximum baud rate is 2 MBaud (200pF). Applying an active slave select signal at SS L9230 is selected by the SPI master. SI is the data input (Slave In), SO the data output (Slave Out). Via SCK (Serial Clock Input) the SPI clock is provided by the master. In case of inactive slave select signal (High) the data output SO goes into tristate. Figure 8. SPI Power Supply DMS SS SI SPI Control: State Machine Clock Counter Control Bits Parity Generator Shift Register DIA_REG Depending on the application the first two bits of an instruction may be used to estabish an extended device-addressing. This gives the opportunity to operate up to 4 Slave-devices sharing one common SS signal from the Master-Unit Power Supply of the SPI-Interface SPI-Logic and I/O-Pins are alternativ supplied from DMS or Vcc internal, depending on which voltage is higher. That is why diagnosis of the EN-/DI-Pins is always possible, even in case of missing H-Bridge-power supply e.g. during „Vorlauf/Nauchlauf“. 14/25 L9230 Characteristics of the SPI Interface 1) When DMS is > 3,5V, the SPI is active, independent of the state of EN or DI and the voltage on VS. During active reset conditions (DMS < 3,5V) the SPI is driven into its default state. When reset becomes inactive, the state machine enters into a waitstate for the next instruction. 2) If the slave select signal at SS is inactive (high), the state machine is forced to enter the waitstate, i.e. the state machine waits for the following instruction. 3) During active (low) state of the select signal SS the falling edge of the serial clock signal SCK will be used to latch the input data at SI. Output data at SO are driven with the rising edge of SCK. Further processing of the data according to the instruction ( i.e. modification of internal registers) will be triggered by the rising edge of the SS signal. (-> See Note) 3 ) Chipaddress: In order to establish the option of extended addressing the uppermost two bits of the instruction-byte ( i.e the first two SI-bits of a Frame ) are reserved to send a chipaddress. To avoid a busconflict the output SO must stay high impedant during the addressing phase of a frame (i.e. until the addressbits are recognised as valid chipaddress). This tristate behavior should be realised in any case, regardless wether the extended addressoption is used or not. If the chipaddress does not match, the according access will be ignored and SO remains high impedant for the complete frame regardless which frametype is applied. 5) Check byte: Simultaneously to the receipt of an SPI instruction L9230 transmitts a check byte via the output SO to the controller. This byte indicates regular or irregular operation of the SPI. It contains an initial bitpattern and a flag indicating an invalid instruction of the previous access. 6) On the read access the databits at the SPI input SI are rejected. 7) Invalid instruction/access: An instruction is invalid, if one of the following conditions is fulfilled: - an unused instruction code is detected (see tables with SPI instructions). - in case the previous transmission is not completed in terms of internal data processing. ( Violation of the minimum Access-Time. ) If an invalid instruction is detected, any modifications on registers of L9230 are not allowed. In case an unused instruction code occured the databyte “ffhex” will be transmitted after having sent the check byte. In addition any access is invalid if the number of SPI clock pulses (falling edge) counted during active SS differs from exactly 16 clock pulses (-> See Note). 15/25 L9230 SPI Communication Figure 9. Reading access / 8 bit SS SI SPI INSTRUCTION MSB XXXX XXXX SO VERIFICATION BYTE MSB DATA/8 BIT MSB D01AT480 SPI Instruction The uppermost 2 bit of the instruction byte contains the chipadress. The individual chipadress is a mask-option and must be defined in accordance to the SPI-Members sharing on SS line. SPI Instruction-Format MSB 7 6 5 4 3 2 1 0 0 0 INSTR4 INSTR3 INSTR2 INSTR1 INSR0 INSW Bit Name 7,6 CPAD1,0 5-1 INSTR (4-0) 0 INSW Description Chip Adress (has to be ‘0’, ‘0’) SPI instruction (encoding) Don‘t care SPI Instruction-Bytes Encoding SPI Instruction bit 7,6 CPAD1,0 bit 5,4,3,2,1 INSTR(4...0) Description Bit 0 RD_IDENT 00 00000 0 read identifier RD_VERSION 00 00001 1 read version RD_DIA 00 00100 1 read DIA_REG all others 16/25 no function L9230 Reset of the Diagnostic Register DIA_REG On the following conditions DIA_REG is reset: - DI high - EN low - With the rising edge of the SS-signal after the SPI-Instruction RD_DIA. - When the voltage on DMS exceeds the threshold for detecting SPI-Mode. (after undervoltage condition) - Undervoltage on VS (< 5,0V) sets Bit 0 .... Bit 3 of DIA_REG to 0000. - If UB rises over about the undervoltage level, the Bits of DIA_REG are restored (when VS internal or DMS > 3,5V) Verification byte: MSB 7 6 5 4 3 2 1 0 Z Z 1 0 1 0 1 TRANS_F Bit Name 0 TRANS_F Description Bit = 1: error detected during previous transfer Bit = 0: previous transfer was recognised as valid 1 Fixed to High 2 Fixed to Low 3 Fixed to High 4 Fixed to Low 5 Fixed to High 6 send as high impedance 7 send as high impedance 17/25 L9230 Diagnostics/Encoding of Failures Description of the SPI Registers Register: (SPI Instructions: RD_DIA) DIA_REG 7 6 5 4 3 2 1 0 DI OT CurrRed CurrLim DIA21 DIA20 Dia11 DIA10 State of Reset: FFH Access by Controller: Read only Bit Name Description 0 DIA 10 1 DIA 11 Diagnosis-Bit2 of OUT1 2 DIA 20 Diagnosis-Bit1 of OUT2 Diagnosis-Bit1 of OUT1 3 DIA 21 Diagnosis-Bit2 of OUT2 4 CurrLim is set to „0“ in case of current limitation 5 CurrRed 6 OT 7 DI is set to „0“ in case of temperature dependet current limitation is set to „0“ in case of overtemperature shows the wired-or state of the Pins EN and DI Encoding of the Diagnostic Bits of the Output-Stages OUT1 and OUT2 DIA21 DIA20 DIA11 DIA10 - - 0 0 Short circuit over load (SCOL) - - 0 1 Short circuit to battery on OUT1 (SCB1) - - 1 0 Short circuit to ground on OUT1 (SCG1) - - 1 1 No error detected on OUT1 0 0 - - Open load (OL) 0 1 - - Short circuit to battery on OUT2 (SCB2) 1 0 - - Short circuit to ground on OUT2 (SCG2) 1 1 - - No error detected on OUT2 0 0 0 0 Undervoltage on Pin UB Description of DIA_REG Bit7 18/25 EN DI DIA_REG Bit7 0 0 0 0 1 0 1 0 1 1 1 0 L9230 Device Identifier The IC‘s identifier is used for production test purposes and features plug & play functionality depending on the systems software release. It is made up on a device-number and a revision number each one read-only accessible via standardised instructions. The Device number is defines once to allow indentification of different IC-Types by software. The Revision number may be utilised to distinguish different states of hardware. The contents is divided into an upper 4 bit field reserved to define revisions correspondending to specific software releases. The lower 4 bit field is utilised to indentify the actual maskset. Both (SWR and MSR) will start with 0000b and are increased by 1 every time an according modification of the hardware is introduced. Reading the IC Identifier (SPI Instruction: RD_IDENT): IC Identifier1 (Device ID) 7 6 5 4 3 2 1 0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Bit Name 7...0 ID(7...0) Description ID-No.: 10100001 L9230 Reading the IC revision number (SPI Instruction: RD_VERSION): IC’s revision number 7 6 5 4 3 2 1 0 SWR3 SWR2 SWR1 SWR0 MSR3 MSR2 MSR1 MSR0 Bit Name Description 7...4 SWR(3...0) Revision corresponding to Software release: 0Hex 3...0 MSR(3...0) Revision corresponding to Maskset: 0Hex 19/25 L9230 Figure 10. Application example with SPI-Interface DMS UB IN1 VBATT VOLTAGE REGULATOR VCC IN2 DI POWER-ON RESET RESET µC OUT1 SCK M SS SO OUT2 SI I.E. WATCH DOG µP EN GND D01AT481 Figure 11. Application example with Status-Flag DMS 47K UB SF VBATT VOLTAGE REGULATOR VCC IN1 IN2 POWER-ON RESET RESET µC OUT1 DI M SS SO OUT2 SI I.E. WATCH DOG µP EN GND 20/25 D01AT482 L9230 Figure 12. Application examples for Overvoltage- and Reverse-Voltage Protection Version 1 REVERSE POLARITY PROTECTION VIA MAIN RELAIS VS H-BRIDGE VS < 40V IGNITION SWITCH MAIN RELAIS BATTERY Version 2 REVERSE POLARITY PROTECTION VIA ACTIVE DIODE H-BRIDGE VS < 40V VS BATTERY D01AT483 ESD-SOLIDITY The connection pins of the IC have to be protected against Electrostatic Discharge ESD) by suitable integrated protection structures. The integrated circuit has to meet the demand of the „Human-Body-Model“ with VC = ± 4kV C = 100pF and R2 = 1,5kΩ (330Ω for OUT1 and OUT2). Thereby any defect or destruction of the integrated circuit must not occur. The protection structures realized to reach the ESD-strength have to be coordinated. The ESD-strength has to be verified by the test circuit given as below. Figure 13. S2 R1 (1) (2) R2 S1 US = V DCVOLTMETER C OUT S3 D01AT484 For the Pins 4, 5, 6, 7, 14 and 15 UC = + 4kV R1 = 100kΩ R2 = 330Ω C = 100pF Number of pulses each pin: 18 Frequency: 1Hz Arrangement and performance: The requirements of MIL883D Methode 3015 have to be fulfilled. 21/25 L9230 ISO-PULSES In the main-power-supply-system disturbance transients according to ISO 7637-1 First Edition 1990-06-01 may occur. By means of external components (see Fig. 12) the following maximum ratings of the IC will not be exceeded. statical -1V ...... +40V dynamical for t < 500 ms -2V ...... +40V APPENDIX A OUT1 OUT2 Load available 1 1 Open Load 1 0 SC -> GND on OUT1 with Load 0 0 SC detected on normal operation SC -> GND on OUT2 with Load 0 0 SC detected on normal operation SC -> UB on OUT1 with Load 1 1 SC detected on normal operation SC -> UB on OUT2 with Load 1 1 SC detected on normal operation SC -> GND on OUT1 Open Load 0 0 OL not detected SC -> GND on OUT2 Open Load 1 0 OL detected SC -> UB on OUT1 Open Load 1 0 OL detected SC -> UB on OUT2 Open Load 1 1 OL not detected Double Fault Double Fault Figure 14. VBatt int 5V IN1 IN2 1.5 mA OUT1 OUT2 1 mA 22/25 L9230 APPENDIX B Figure 15. Voltage Supply of SPI-Logic and EN/DI-Logic VBatt EN DI OutputStage EN/DILogic internal Vcc DMS = GND EN/DI-Logic is supplied from internal VCC DMS = VCC EN/DI-Logic is supplied from DMS (OR int. VCC) DMS SO SI SCK SS Status EN/DI SPILogic Undervoltage on VBatt Failure and Status Output Stage 23/25 L9230 DIM. mm MIN. TYP. A a1 inch MAX. MIN. TYP. 3.6 0.1 0.142 0.3 a2 0.004 0.012 3.3 0.130 a3 0 0.1 0.000 0.004 b 0.4 0.53 0.016 0.021 c 0.23 0.32 0.009 0.013 D (1) 15.8 16 0.622 0.630 0.386 D1 9.4 9.8 0.370 E 13.9 14.5 0.547 e 1.27 e3 E1 (1) 0.570 0.450 11.1 E2 0.429 0.437 2.9 0.114 E3 5.8 6.2 0.228 0.244 G 0 0.1 0.000 0.004 H 15.5 15.9 0.610 0.626 h L 1.1 0.8 JEDEC MO-166 0.043 1.1 N Weight: 1.9gr 0.050 11.43 10.9 OUTLINE AND MECHANICAL DATA MAX. 0.031 0.043 8˚ (typ.) S 8˚ (max.) T 10 0.394 PowerSO20 (1) “D and E1” do not include mold flash or protusions. - Mold flash or protusions shall not exceed 0.15mm (0.006”) - Critical dimensions: “E”, “G” and “a3”. N R N a2 b A e DETAIL A c a1 DETAIL B E e3 H DETAIL A lead D slug a3 DETAIL B 20 11 0.35 Gage Plane -C- S SEATING PLANE L G E2 E1 BOTTOM VIEW C (COPLANARITY) T E3 1 24/25 h x 45 10 PSO20MEC D1 0056635 L9230 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 25/25