PROFET® Preliminary BTS 725 L1 Smart Two Channel Highside Power Switch Features • Overload protection • Current limitation • Short-circuit protection • Thermal shutdown • Overvoltage protection (including load dump) • Reverse battery protection1) • Undervoltage and overvoltage shutdown with auto-restart and hysteresis • Open drain diagnostic output • Open load detection in ON-state • CMOS compatible input • Loss of ground and loss of Vbb protection • Electrostatic discharge (ESD) protection Product Summary Overvoltage Protection Operating voltage active channels: On-state resistance RON Nominal load current IL(NOM) Current limitation IL(SCr) Vbb(AZ) Vbb(on) one 60 4.0 17 43 V 5.0 ... 24 V two parallel 30 mΩ 6.0 A 17 A Application • µC compatible power switch with diagnostic feedback for 12 V DC grounded loads • Most suitable for resistive and lamp loads • Replaces electromechanical relays and discrete circuits General Description N channel vertical power FET with charge pump, ground referenced CMOS compatible input and diagnostic feedback, monolithically integrated in Smart SIPMOS technology. Fully protected by embedded protection functions. Pin Definitions and Functions Pin 1,10, 11,12, 15,16, 19,20 3 7 17,18 13,14 4 8 2 6 5,9 1) Symbol Function Positive power supply voltage. Design the Vbb wiring for the simultaneous max. short circuit currents from channel 1 to 2 and also for low thermal resistance IN1 Input 1,2, activates channel 1,2 in case of IN2 logic high signal OUT1 Output 1,2, protected high-side power output OUT2 of channel 1,2. Design the wiring for the max. short circuit current ST1 Diagnostic feedback 1,2 of channel 1,2, ST2 open drain, low on failure GND1 Ground 1 of chip 1 (channel 1) GND2 Ground 2 of chip 2 (channel 2) N.C. Not Connected Pin configuration (top view) Vbb GND1 IN1 ST1 N.C. GND2 IN2 ST2 N.C. Vbb 1 2 3 4 5 6 7 8 9 10 • 20 19 18 17 16 15 14 13 12 11 Vbb Vbb OUT1 OUT1 Vbb Vbb OUT2 OUT2 Vbb Vbb With external current limit (e.g. resistor RGND=150 Ω) in GND connection, resistor in series with ST connection, reverse load current limited by connected load. Semiconductor Group 1 03.96 Preliminary BTS 725 L1 Block diagram Two Channels; Open Load detection in on state; + Vbb Voltage Overvoltage Current source protection limit Leadframe Gate protection VLogic 3 Voltage Charge pump sensor Level shifter OUT1 17,18 Temperature sensor Rectifier IN1 Open load 4 ST1 Logic ESD Load detection R O1 1 GND1 GND1 Chip 1 Signal GND Chip 1 Load GND + Vbb Leadframe OUT2 13,14 Logic and protection circuit of chip 2 (equivalent to chip 1) 7 IN2 Load 8 ST2 R O2 6 GND2 Chip 2 PROFET Signal GND Chip 2 GND2 Load GND Leadframe connected to pin 1, 10, 11, 12, 15, 16, 19, 20 Maximum Ratings at Tj = 25°C unless otherwise specified Parameter Symbol Supply voltage (overvoltage protection see page 4) Supply voltage for full short circuit protection Tj,start = -40 ...+150°C Vbb Vbb Semiconductor Group 2 Values Unit 43 24 V V Preliminary BTS 725 L1 Maximum Ratings at Tj = 25°C unless otherwise specified Parameter Symbol Values Unit Load current (Short-circuit current, see page 5) Load dump protection2) VLoadDump = UA + Vs, UA = 13.5 V RI3) = 2 Ω, td = 200 ms; IN = low or high, each channel loaded with RL = 3.4 Ω, Operating temperature range Storage temperature range Power dissipation (DC)5 Ta = 25°C: Ta = 85°C: (all channels active) Electrostatic discharge capability (ESD) (Human Body Model) Input voltage (DC) Current through input pin (DC) Current through status pin (DC) IL VLoad dump4) self-limited 60 A V Tj Tstg Ptot °C VESD -40 ...+150 -55 ...+150 3.7 1.9 1.0 VIN IIN IST -10 ... +16 ±2.0 ±5.0 V mA 12 41 34 K/W Values min typ max Unit W kV see internal circuit diagram page 8 Thermal resistance junction - soldering point5),6) junction - ambient5) each channel: one channel active: all channels active: Rthjs Rthja Electrical Characteristics Parameter and Conditions, each of the two channels Symbol at Tj = 25 °C, Vbb = 12 V unless otherwise specified Load Switching Capabilities and Characteristics On-state resistance (Vbb to OUT) IL = 2 A each channel, Tj = 25°C: RON Tj = 150°C: two parallel channels, Tj = 25°C: 2) 3) 4) 5) 6) -- 50 100 60 120 25 30 mΩ Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins, e.g. with a 150 Ω resistor in the GND connection and a 15 kΩ resistor in series with the status pin. A resistor for input protection is integrated. RI = internal resistance of the load dump test pulse generator VLoad dump is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839 Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm2 (one layer, 70µm thick) copper area for Vbb connection. PCB is vertical without blown air. See page 14 Soldering point: upper side of solder edge of device pin 15. See page 14 Semiconductor Group 3 Preliminary BTS 725 L1 Parameter and Conditions, each of the two channels Symbol Values min typ max IL(NOM) 3.6 5.5 4.0 6.0 -- A -- -- 10 mA ton toff 80 80 200 230 400 450 µs dV/dton 0.1 -- 1 V/µs -dV/dtoff 0.1 -- 1 V/µs Vbb(on) Vbb(under) Vbb(u rst) Vbb(ucp) 5.0 3.5 --- ---5.6 24 5.0 5.0 7.0 V V V V ∆Vbb(under) -- 0.2 -- V Vbb(over) Vbb(o rst) ∆Vbb(over) Vbb(AZ) 24 23 -42 --0.5 47 34 ---- V V V V ---- 20 29 -- 50 56 12 µA --- 1.8 3.6 3.5 7 mA at Tj = 25 °C, Vbb = 12 V unless otherwise specified Nominal load current one channel active: two parallel channels active: 5) Device on PCB , Ta = 85°C, Tj ≤ 150°C Output current while GND disconnected or pulled up; Vbb = 30 V, VIN = 0, see diagram page 9 Turn-on time to 90% VOUT: Turn-off time to 10% VOUT: RL = 12 Ω, Tj =-40...+150°C Slew rate on 10 to 30% VOUT, RL = 12 Ω, Tj =-40...+150°C: Slew rate off 70 to 40% VOUT, RL = 12 Ω, Tj =-40...+150°C: Operating Parameters Operating voltage7) Tj =-40...+150°C: Undervoltage shutdown Tj =-40...+150°C: Undervoltage restart Tj =-40...+150°C: Undervoltage restart of charge pump see diagram page 13 Tj =-40...+150°C: Undervoltage hysteresis ∆Vbb(under) = Vbb(u rst) - Vbb(under) Overvoltage shutdown Tj =-40...+150°C: Overvoltage restart Tj =-40...+150°C: Overvoltage hysteresis Tj =-40...+150°C: ) 8 Overvoltage protection Tj =-40...+150°C: I bb = 40 mA Standby current, all channels off Tj =25°C: VIN = 0 Tj =150°C: Leakage output current (included in Ibb(off)) VIN = 0 Operating current 9), VIN = 5V, Tj =-40...+150°C IGND = IGND1 + IGND2, one channel on: two channels on: 7) 8) 9) IL(GNDhigh) Ibb(off) IL(off) IGND At supply voltage increase up to Vbb = 5.6 V typ without charge pump, VOUT ≈Vbb - 2 V see also VON(CL) in circuit diagram on page 8. Add IST, if IST > 0 Semiconductor Group 4 Unit µA Preliminary BTS 725 L1 Parameter and Conditions, each of the two channels Symbol Values min typ max Unit each channel, Tj =-40°C: IL(SCp) 27 37 47 20 30 40 Tj =25°C: 12 18 25 Tj =+150°C: two parallel channels twice the current of one channel Repetitive short circuit current limit, Tj = Tjt each channel IL(SCr) -17 --17 -two parallel channels A at Tj = 25 °C, Vbb = 12 V unless otherwise specified Protection Functions Initial peak short circuit current limit, (see timing diagrams, page 11) A (see timing diagrams, page 11) Initial short circuit shutdown time Tj,start =-40°C: toff(SC) Tj,start = 25°C: --- 5 4 --- ms 150 -- -10 --- °C K --- -610 32 -- V mV (see page 10 and timing diagrams on page 11) Thermal overload trip temperature Thermal hysteresis Tjt ∆Tjt Reverse Battery Reverse battery voltage 10) Drain-source diode voltage (Vout > Vbb) IL = - 4.0 A, Tj = +150°C -Vbb -VON Diagnostic Characteristics Open load detection current, (on-condition) 10 -800 each channel, Tj = -40°C: I L (OL) 10 -600 Tj = 25°C: 10 -600 Tj = +150°C: twice the current of one channel two parallel channels ) 11 Open load detection voltage 2 3 4 Tj =-40..+150°C: VOUT(OL) Internal output pull down 4 10 30 (OUT to GND), VOUT = 5 V Tj =-40..+150°C: RO 4 10) mA V kΩ Requires a 150 Ω resistor in GND connection. The reverse load current through the intrinsic drain-source diode has to be limited by the connected load. Note that the power dissipation is higher compared to normal operating conditions due to the voltage drop across the intrinsic drain-source diode. The temperature protection is not active during reverse current operation! Input and Status currents have to be limited (see max. ratings page 3 and circuit page 8). 11) External pull up resistor required for open load detection in off state. Semiconductor Group 5 Preliminary BTS 725 L1 Parameter and Conditions, each of the two channels Symbol Values min typ max RI 2.5 3.5 6 kΩ VIN(T+) 1.7 -- 3.5 V VIN(T-) 1.5 -- -- V -1 0.5 -- -50 V µA 20 50 90 µA 100 520 1000 µs -- 250 600 µs 5.4 --- 6.1 --- -0.4 0.6 V at Tj = 25 °C, Vbb = 12 V unless otherwise specified Input and Status Feedback12) Input resistance (see circuit page 8) Tj =-40..+150°C: Input turn-on threshold voltage Tj =-40..+150°C: Input turn-off threshold voltage Tj =-40..+150°C: Input threshold hysteresis VIN = 0.4 V: Off state input current Tj =-40..+150°C: VIN = 5 V: On state input current Tj =-40..+150°C: Delay time for status with open load after switch off Tj =-40..+150°C: (see timing diagrams, page 12), Status invalid after positive input slope Tj =-40..+150°C: (open load) Status output (open drain) Zener limit voltage Tj =-40...+150°C, IST = +1.6 mA: ST low voltage Tj =-40...+25°C, IST = +1.6 mA: Tj = +150°C, IST = +1.6 mA: 12) ∆ VIN(T) IIN(off) IIN(on) td(ST OL4) td(ST) VST(high) VST(low) If ground resistors RGND are used, add the voltage drop across these resistors. Semiconductor Group 6 Unit Preliminary BTS 725 L1 Truth Table Cannel 1 Input 1 Output 1 Status 1 Cannel 2 Input 2 Output 2 Status 2 level level BTS 725L1 L H L H L H L H L H L H L H Z H H H L L L L L L H H H (L13)) L L14) H (L15)) H L H H H H Normal operation Open load Short circuit to Vbb Overtemperature Undervoltage Overvoltage L = "Low" Level H = "High" Level X = don't care Z = high impedance, potential depends on external circuit Status signal valid after the time delay shown in the timing diagrams Parallel switching of channel 1 and 2 is easily possible by connecting the inputs and outputs in parallel. The status outputs ST1 and ST2 have to be configured as a 'Wired OR' function with a single pull-up resistor. Terms Ibb V bb 3 IN1 VST1 4 ST1 I IN2 Vbb IN1 I ST1 V Leadframe Leadframe I IN1 I L1 PROFET Chip 1 OUT1 R I GND1 IN2 I ST2 17,18 V GND1 2 7 VON1 VOUT1 GND1 IN2 V ST2 8 Vbb ST2 I L2 PROFET Chip 2 OUT2 VON2 13,14 GND2 6 R GND2 IGND2 VOUT2 Leadframe (Vbb) is connected to pin 1,10,11,12,15,16,19,20 External RGND optional; two resistors RGND1, RGND2 = 150 Ω or a single resistor RGND = 75 Ω for reverse battery protection up to the max. operating voltage. 13) 14) With external resistor between output and Vbb An external short of output to Vbb in the off state causes an internal current from output to ground. If R GND is used, an offset voltage at the GND and ST pins will occur and the VST low signal may be errorious. 15) Low resistance to V may be detected by no-load-detection bb Semiconductor Group 7 Preliminary BTS 725 L1 Overvoltage protection of logic part Input circuit (ESD protection), IN1 or IN2 GND1 or GND2 R IN I + V bb ESD-ZD I I V I RI IN GND Z2 Logic ESD zener diodes are not to be used as voltage clamp at DC conditions. Operation in this mode may result in a drift of the zener voltage (increase of up to 1 V). R ST ST V PROFET Z1 GND R GND Status output, ST1 or ST2 Signal GND +5V R ST(ON) VZ1 = 6.1 V typ., VZ2 = 47 V typ., RI = 3.5 kΩ typ., RGND = 150 Ω, RST = 15 kΩ nominal. ST Reverse battery protection GND ESDZD - Vbb + 5V ESD-Zener diode: 6.1 V typ., max 5.0 mA; RST(ON) < 380 Ω at 1.6 mA, ESD zener diodes are not to be used as voltage clamp at DC conditions. Operation in this mode may result in a drift of the zener voltage (increase of up to 1 V). R ST IN RI OUT ST Power Inverse Diode Logic overvoltage output clamp, OUT1 or OUT2 GND RGND +Vbb Signal GND VZ Power GND RGND = 150 Ω, RI = 3.5 kΩ typ, Temperature protection is not active during inverse current operation. V ON OUT PROFET Power GND VON clamped to VON(CL) = 47 V typ. Semiconductor Group RL 8 Preliminary BTS 725 L1 GND disconnect with GND pull up Open-load detection, OUT1 or OUT2 ON-state diagnostic condition: VON < RON·IL(OL); IN high IN + V bb Vbb PROFET OUT ST VON ON GND OUT Logic unit V Open load detection V bb V IN ST V GND If VGND > VIN - VIN(T+) device stays off Due to VGND > 0, no VST = low signal available. OFF-state diagnostic condition: VOUT > 3 V typ.; IN low R EXT OFF V Logic unit Open load detection R OUT O Signal GND GND disconnect Vbb IN PROFET OUT ST GND V bb V IN V ST V GND In case of IN = high is VOUT ≈ VIN - VIN(T+). Due to VGND > 0, no VST = low signal available. Semiconductor Group 9 Preliminary BTS 725 L1 Typ. on-state resistance Typ. standby current RON = f (Vbb,Tj ); IL = 2 A, IN = high Ibb(off) = f (Tj ); Vbb = 9...24 V, IN1,2 = low RON [mOhm] Ibb(off) [µA] 40 150 35 125 30 Tj = 150°C 100 75 25 85°C 20 25°C 15 -40° C 10 50 25 5 0 -50 0 0 10 20 30 0 50 100 150 Vbb [V] 200 Tj [°C] Typ. open load detection current Typ. initial short circuit shutdown time IL(OL) = f (Vbb,Tj ); IN = high toff(SC) = f (Tj,start ); Vbb =12 V IL(OL) [mA] toff(SC) [msec] 500 6 450 5 no load detection not specified for Vbb < 6 V 400 350 300 250 200 150 4 3 2 100 1 50 0 0 5 10 15 20 25 Vbb [V] Semiconductor Group 10 0 -50 0 50 100 150 200 Tj,start [°C] Preliminary BTS 725 L1 Timing diagrams Both channels are symmetric and consequently the diagrams are valid for channel 1 and channel 2 Figure 1a: Vbb turn on: Figure 3a: Turn on into short circuit: shut down by overtemperature, restart by cooling IN1 IN1 other channel: normal operation IN2 V bb I L1 V I OUT1 L(SCp) I L(SCr) V OUT2 t off(SC) ST ST open drain t t Heating up of the chip may require several milliseconds, depending on external conditions (toff(SC) vs. Tj,start see page 10) Figure 2a: Switching a lamp: Figure 3b: Turn on into short circuit: shut down by overtemperature, restart by cooling (two parallel switched channels 1 and 2) IN IN1/2 ST I V I +I L1 L2 I L(SCp) OUT I L(SCr) L t t off(SC) ST1/2 The initial peak current should be limited by the lamp and not by the initial short circuit current IL(SCp) = 28 A typ. of the device. t ST1 and ST2 have to be configured as a 'Wired OR' function ST1/2 with a single pull-up resistor. Semiconductor Group 11 Preliminary BTS 725 L1 Figure 5b: Open load: detection in ON-state, open load occurs in on-state Figure 4a: Overtemperature: Reset if Tj <Tjt IN IN t d(ST OL1) ST ST V V t d(ST OL2) OUT OUT T I J normal open normal L t t td(ST OL1) = 20 µs typ., td(ST OL2) = 10 µs typ Figure 5a: Open load: detection in ON-state, turn on/off to open load Figure 5c: Open load: detection in ON- and OFF-state (with REXT), turn on/off to open load IN IN ST t d(ST) t d(ST OL4) ST t d(ST) V OUT V OUT I L I L open open t t Semiconductor Group 12 Preliminary BTS 725 L1 Figure 6a: Undervoltage: Figure 7a: Overvoltage: IN IN V bb V bb V V bb(under) V ON(CL) Vbb(over) V bb(o rst) bb(u rst) V V OUT OUT ST ST t t Figure 6b: Undervoltage restart of charge pump on-state off-state V V V bb(u rst) V bb(over) off-state VON(CL) V on bb(o rst) bb(u cp) V bb(under) V bb IN = high, normal load conditions. Charge pump starts at Vbb(ucp) = 5.6 V typ. Semiconductor Group 13 Preliminary BTS 725 L1 Package and Ordering Code Standard P-DSO-20-9 BTS725L1 Ordering Code Q67060-S7006-A2 All dimensions in millimetres 1) Does not include plastic or metal protrusions of 0.15 max per side 2) Does not include dambar protrusion of 0.05 max per side Definition of soldering point with temperature Ts: upper side of solder edge of device pin 15. Pin 15 Printed circuit board (FR4, 1.5mm thick, one layer 70µm, 6cm2 active heatsink area) as a reference for max. power dissipation Ptot, nominal load current IL(NOM) and thermal resistance Rthja Semiconductor Group 14