PROFET® BTS 736 L2
Smart High-Side Power Switch
Two Channels: 2 x 40mΩ
Status Feedback
Product Summary
Operating Voltage
Vbb(on)
Active channels
On-state Resistance
RON
Nominal load current
IL(NOM)
Current limitation
IL(SCr)
Package
4.75...41V
one
two parallel
40mΩ
20mΩ
4.8A
7.3A
30A
30A
P-DSO-20-9
General Description
•
•
N channel vertical power MOSFET with charge pump, ground referenced CMOS compatible input and
diagnostic feedback, monolithically integrated in Smart SIPMOS technology.
Providing embedded protective functions
Applications
•
•
•
•
µC compatible high-side power switch with diagnostic feedback for 5V, 12V and 24V grounded loads
All types of resistive, inductive and capacitve loads
Most suitable for loads with high inrush currents, so as lamps
Replaces electromechanical relays, fuses and discrete circuits
Basic Functions
•
•
•
•
•
•
Very low standby current
CMOS compatible input
Fast demagnetization of inductive loads
Stable behaviour at undervoltage
Wide operating voltage range
Logic ground independent from load ground
Protection Functions
•
•
•
•
•
•
•
•
Block Diagram
Short circuit protection
Overload protection
Current limitation
Thermal shutdown
Overvoltage protection (including load dump) with external
resistor
Reverse battery protection with external resistor
Loss of ground and loss of Vbb protection
Electrostatic discharge protection (ESD)
ST1
IN2
Logic
Channel
1
Logic
Channel
2
PROFET
GND
Diagnostic feedback with open drain output
Open load detection in ON-state
Feedback of thermal shutdown in ON-state
Semiconductor Group
IN1
ST2
Diagnostic Function
•
•
•
Vbb
1 of 14
OUT 1
Load 1
OUT 2
Load 2
2003-Oct-01
BTS 736 L2
Functional diagram
overvoltage
protection
internal
voltage supply
gate
control
+
charge
pump
logic
current limit
VBB
clamp for
inductive load
OUT1
temperature
sensor
IN1
ESD
LOAD
Open load
detection
ST1
GND1
Channel 1
IN2
Control and protection circuit
of
channel 2
ST2
OUT2
GND2
PROFET
Pin configuration
Pin Definitions and Functions
Pin
1,10,
11,12,
15,16,
19,20
3
7
17,18
13,14
4
8
2
6
5,9
Symbol Function
Vbb
Positive power supply voltage. Design the
wiring for the simultaneous max. short circuit
currents from channel 1 to 2 and also for low
thermal resistance
IN1
Input 1,2, activates channel 1,2 in case of
IN2
logic high signal
OUT1
Output 1,2, protected high-side power output
OUT2
of channel 1,2. Design the wiring for the max.
short circuit current
ST1
Diagnostic feedback 1,2 of channel 1,2,
ST2
open drain, low on failure
GND1
Ground 1 of chip 1 (channel 1)
GND2
Ground 2 of chip 2 (channel 2)
N.C.
Not Connected
Semiconductor Group
2
(top view)
Vbb 1
•
20 Vbb
GND1 2
IN1 3
19 Vbb
18 OUT1
ST1 4
17 OUT1
N.C. 5
GND2 6
16 Vbb
15 Vbb
IN2 7
ST2 8
14 OUT2
13 OUT2
N.C. 9
12 Vbb
Vbb 10
11 Vbb
2003-Oct-01
BTS 736 L2
Maximum Ratings at Tj = 25°C unless otherwise specified
Parameter
Symbol
Supply voltage (overvoltage protection see page 4)
Supply voltage for full short circuit protection
Tj,start = -40 ...+150°C
Load current (Short-circuit current, see page 5)
Load dump protection1) VLoadDump = VA + Vs, VA = 13.5 V
RI2) = 2 Ω, td = 200 ms; IN = low or high,
each channel loaded with RL = 9.0 Ω,
Operating temperature range
Storage temperature range
Power dissipation (DC)4)
Ta = 25°C:
(all channels active)
Ta = 85°C:
Maximal switchable inductance, single pulse
Vbb = 12V, Tj,start = 150°C4),
IL = 4.0 A, EAS = 296 mJ, 0 Ω
one channel:
IL = 6.0 A, EAS = 631 mJ, 0 Ω
two parallel channels:
Vbb
Vbb
Values
Unit
43
24
V
V
IL
VLoad dump3)
self-limited
60
A
V
Tj
Tstg
Ptot
-40 ...+150
-55 ...+150
3.8
2.0
°C
19.0
17.5
mH
1.0
4.0
8.0
kV
-10 ... +16
±2.0
±5.0
V
mA
Values
typ
Max
Unit
ZL
W
see diagrams on page 9
Electrostatic discharge capability (ESD)
IN:
(Human Body Model)
ST:
out to all other pins shorted:
VESD
acc. MIL-STD883D, method 3015.7 and ESD assn. std. S5.1-1993
R=1.5kΩ; C=100pF
Input voltage (DC)
Current through input pin (DC)
Current through status pin (DC)
VIN
IIN
IST
see internal circuit diagram page 8
Thermal Characteristics
Parameter and Conditions
Symbol
min
Thermal resistance
junction - soldering point4),5)
each channel: Rthjs
junction - ambient4)
one channel active: Rthja
all channels active:
1)
2)
3)
4)
5)
----
-40
33
12
---
K/W
Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins (a 150Ω
resistor for the GND connection is recommended.
RI = internal resistance of the load dump test pulse generator
VLoad dump is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm2 (one layer, 70µm thick) copper area for Vbb
connection. PCB is vertical without blown air. See page 14
Soldering point: upper side of solder edge of device pin 15. See page 14
Semiconductor Group
3
2003-Oct-01
BTS 736 L2
Electrical Characteristics
Parameter and Conditions, each of the two channels
Symbol
at Tj = -40...+150°C, Vbb = 12 V unless otherwise specified
Load Switching Capabilities and Characteristics
On-state resistance (Vbb to OUT); IL = 2 A, Vbb ≥ 7V
each channel,
Tj = 25°C: RON
Tj = 150°C:
Values
min
typ
Max
--
Unit
mΩ
36
67
40
75
18
20
4.4
6.7
4.8
7.3
--
A
--
--
2
mA
100
120
200
250
µs
Turn-off time
IN
RL = 12 Ω
Slew rate on 8)
Tj = -40°C: dV/dton
10 to 30% VOUT, RL = 12 Ω
Tj = 25°C...150°C:
Slew rate off 8)
Tj = -40°C: -dV/dtoff
70 to 40% VOUT, RL = 12 Ω
Tj = 25°C...150°C:
50
50
0.15
0.15
0.15
0.15
-----
1
0.8
1
0.8
V/µs
Operating Parameters
Operating voltage
Vbb(on)
4.75
Vbb(AZ)
41
43
----
---47
10
-1
41
43
-52
16
50
10
---
0.8
1.6
1.4
2.8
two parallel channels, Tj = 25°C:
see diagram, page 10
Nominal load current
one channel active: IL(NOM)
two parallel channels active:
Device on PCB6), Ta = 85°C, Tj ≤ 150°C
Output current while GND disconnected or pulled up7); IL(GNDhigh)
Vbb = 30 V, VIN = 0, see diagram page 8
Turn-on time8)
IN
to 90% VOUT: ton
to 10% VOUT: toff
Tj=-40
Tj=25...150°C:
Overvoltage protection9)
Tj =-40°C:
I bb = 40 mA
Tj =25...150°C:
)
10
Standby current
Tj =-40°C...25°C:
VIN = 0; see diagram page 10
Tj =150°C:
Leakage output current (included in Ibb(off))
VIN = 0
Operating current 11), VIN = 5V,
IGND = IGND1 + IGND2,
one channel on:
two channels on:
Ibb(off)
IL(off)
IGND
V/µs
V
V
µA
µA
mA
6)
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm2 (one layer, 70µm thick) copper area for Vbb
connection. PCB is vertical without blown air. See page 14
7) not subject to production test, specified by design
8) See timing diagram on page 11.
9) Supply voltages higher than V
bb(AZ) require an external current limit for the GND and status pins (a 150Ω
resistor for the GND connection is recommended). See also VON(CL) in table of protection functions and
circuit diagram on page 8.
10) Measured with load; for the whole device; all channels off
11) Add I , if I
ST
ST > 0
Semiconductor Group
4
2003-Oct-01
BTS 736 L2
Parameter and Conditions, each of the two channels
Symbol
at Tj = -40...+150°C, Vbb = 12 V unless otherwise specified
Values
min
typ
Max
Unit
Protection Functions12)
Current limit, (see timing diagrams, page 12)
Tj =-40°C: IL(lim)
Tj =25°C:
Tj =+150°C:
Repetitive short circuit current limit,
Tj = Tjt
each channel IL(SCr)
two parallel channels
40
33
23
49
41
29
60
48
35
A
---
30
30
---
A
--
1.7
--
ms
41
43
150
--
-47
-10
-52
---
°C
K
---
-600
32
--
V
mV
(see timing diagrams, page 12)
Initial short circuit shutdown time
Tj,start =25°C: toff(SC)
(see timing diagrams on page 12)
Output clamp (inductive load switch off)13)
at VON(CL) = Vbb - VOUT, IL= 40 mA
Tj =-40°C: VON(CL)
Tj =25°C...150°C:
Thermal overload trip temperature
Tjt
Thermal hysteresis
∆Tjt
Reverse Battery
Reverse battery voltage 14)
Drain-source diode voltage (Vout > Vbb)
IL = - 4.0 A, Tj = +150°C
-Vbb
-VON
V
12)
Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not
designed for continuous repetitive operation.
13) If channels are connected in parallel, output clamp is usually accomplished by the channel with the lowest
VON(CL)
14) Requires a 150 Ω resistor in GND connection. The reverse load current through the intrinsic drain-source
diode has to be limited by the connected load. Power dissipation is higher compared to normal operating
conditions due to the voltage drop across the drain-source diode. The temperature protection is not active
during reverse current operation! Input and Status currents have to be limited (see max. ratings page 3 and
circuit page 8).
Semiconductor Group
5
2003-Oct-01
BTS 736 L2
Parameter and Conditions, each of the two channels
Symbol
at Tj = -40...+150°C, Vbb = 12 V unless otherwise specified
Values
min
typ
Max
Unit
Diagnostic Characteristics
Open load detection current, (on-condition)
each channel I L (OL)
100
--
900
mA
Input and Status Feedback15)
Input resistance
RI
2.5
3.5
6
kΩ
VIN(T+)
VIN(T-)
∆ VIN(T)
IIN(off)
IIN(on)
td(ST OL4)
1.7
1.5
-1
20
100
--0.5
-50
520
3.2
--50
90
900
V
V
V
µA
µA
µs
--
--
500
µs
5.4
--
6.1
--
-0.4
V
1
(see circuit page 8)
Input turn-on threshold voltage
Input turn-off threshold voltage
Input threshold hysteresis
Off state input current
VIN = 0.4 V:
On state input current
VIN = 5 V:
Delay time for status with open load after switch
off; (see diagram on page 13)
Status invalid after positive input slope
(open load)
Status output (open drain)
Zener limit voltage
IST = +1.6 mA:
ST low voltage
IST = +1.6 mA:
15)
td(ST)
VST(high)
VST(low)
If ground resistors RGND are used, add the voltage drop across these resistors.
Semiconductor Group
6
2003-Oct-01
BTS 736 L2
Truth Table
Channel 1
Input 1
Output 1
Status 1
Channel 2
Input 2
Output 2
Status 2
level
level
BTS 736L2
L
H
L
H
L
H
L
H
Z
H
L
L
H
H
H
L
H
L
Normal
operation
Open load
Overtemperature
L = "Low" Level
H = "High" Level
X = don't care
Z = high impedance, potential depends on external circuit
Status signal valid after the time delay shown in the timing diagrams
Parallel switching of channel 1 and 2 is easily possible by connecting the inputs and outputs in parallel. The
status outputs ST1 and ST2 have to be configured as a 'Wired OR' function with a single pull-up resistor.
Terms
V
Ibb
bb
Leadframe
I IN1
3
I ST1
V
IN1 V ST1
4
Vbb
IN1
ST1
I L1
PROFET
Chip 1
OUT1
R
IGND1
7
VON1
V
V OUT1
GND1
IN2
V ST2
8
Vbb
IN2
I ST2
17,18
GND1
2
Leadframe
I IN2
ST2
I L2
PROFET
Chip 2
OUT2
VON2
13,14
GND2
6
R
IGND2
V OUT2
GND2
Leadframe (Vbb) is connected to pin 1,10,11,12,15,16,19,20
External RGND optional; two resistors RGND1, RGND2 = 150 Ω or a single resistor RGND = 75 Ω for reverse
battery protection up to the max. operating voltage.
Semiconductor Group
7
2003-Oct-01
BTS 736 L2
Input circuit (ESD protection), IN1 or IN2
Overvolt. and reverse batt. protection
+ 5V
R
IN
I
+ Vbb
R ST
V
IN
ESD-ZD I
I
RI
I
Z2
Logic
GND
R ST ST
OUT
V
PROFET
Z1
The use of ESD zener diodes as voltage clamp at DC
conditions is not recommended.
GND
R GND
Signal GND
Status output, ST1 or ST2
ST
ESDZD
GND
Load GND
VZ1 = 6.1 V typ., VZ2 = 47 V typ., RGND = 150 Ω,
RST= 15 kΩ, RI= 3.5 kΩ typ.
In case of reverse battery the load current has to be
limited by the load. Temperature protection is not
active
+5V
R ST(ON)
R Load
Open-load detection OUT1 or OUT2
ON-state diagnostic
Open load, if VON < RON·IL(OL); IN high
ESD-Zener diode: 6.1 V typ., max 5.0 mA; RST(ON) < 375 Ω
at 1.6 mA. The use of ESD zener diodes as voltage clamp at
DC conditions is not recommended.
+ V bb
Inductive and overvoltage output clamp,
OUT1 or OUT2
+Vbb
OUT
Logic
unit
VZ
V
VON
ON
Open load
detection
ON
OUT
GND disconnect
Power GND
VON clamped to VON(CL) = 47 V typ.
IN
Vbb
PROFET
OUT
ST
GND
V
bb
V
IN
V
ST
V
GND
Any kind of load. In case of IN = high is VOUT ≈ VIN - VIN(T+).
Due to VGND > 0, no VST = low signal available.
Semiconductor Group
8
2003-Oct-01
BTS 736 L2
Inductive load switch-off energy
dissipation
GND disconnect with GND pull up
E bb
Vbb
IN
E AS
PROFET
OUT
ELoad
Vbb
IN
ST
GND
PROFET
=
V
V
bb
V
IN ST
V
GND
{
EL
ER
L
Energy stored in load inductance:
2
EL = 1/2·L·I L
While demagnetizing load inductance, the energy
dissipated in PROFET is
EAS= Ebb + EL - ER= VON(CL)·iL(t) dt,
Vbb
PROFET
ZL
R
Vbb disconnect with energized inductive
load
IN
L
ST
GND
Any kind of load. If VGND > VIN - VIN(T+) device stays off
Due to VGND > 0, no VST = low signal available.
high
OUT
with an approximate solution for RL > 0 Ω:
OUT
EAS=
ST
IL· L
(V + |VOUT(CL)|)
2·RL bb
ln (1+ |V
IL·RL
OUT(CL)|
)
GND
V
Maximum allowable load inductance for
a single switch off (one channel)4)
bb
L = f (IL ); Tj,start = 150°C, Vbb = 12 V, RL = 0 Ω
For inductive load currents up to the limits defined by ZL
(max. ratings and diagram on page 9) each switch is
protected against loss of Vbb.
ZL [mH]
1000
Consider at your PCB layout that in the case of Vbb disconnection with energized inductive load all the load current
flows through the GND connection.
100
10
1
2
3
4
5
6
7
8
9
10
11
12
IL [A]
Semiconductor Group
9
2003-Oct-01
BTS 736 L2
Typ. on-state resistance
RON = f (Vbb,Tj ); IL = 2 A, IN = high
RON [mOhm]
80
70
Tj = 150°C
60
50
40
25°C
30
-40°C
20
10
3
5
7
9
30
40
Vbb [V]
Typ. standby current
Ibb(off) = f (Tj ); Vbb = 9...34 V, IN1,2 = low
Ibb(off) [µA]
45
40
35
30
25
20
15
10
5
0
-50
0
50
100
150
200
Tj [°C]
Semiconductor Group
10
2003-Oct-01
BTS 736 L2
Timing diagrams
Both channels are symmetric and consequently the diagrams are valid for channel 1 and
channel 2
Figure 1a: Vbb turn on:
IN1
Figure 2b: Switching a lamp:
IN2
IN
V bb
ST
V
OUT1
V
V
OUT2
OUT
ST1 open drain
I
L
ST2 open drain
t
t
The initial peak current should be limited by the lamp and not by the
current limit of the device.
Figure 2a: Switching a resistive load,
turn-on/off time and slew rate definition:
Figure 2c: Switching an inductive load
IN
IN
VOUT
ST
90%
t on
dV/dtoff
V
dV/dton
10%
t
OUT
off
IL
I
L
I L(OL)
t
t
*) if the time constant of load is too large, open-load-status may
occur
Semiconductor Group
11
2003-Oct-01
BTS 736 L2
Figure 3a: Turn on into short circuit:
shut down by overtemperature, restart by cooling
IN1
Figure 4a: Overtemperature:
Reset if Tj <Tjt
other channel: normal operation
IN
I
ST
L1
I
L(lim)
I
t
ST
V
L(SCr)
OUT
off(SC)
T
J
t
t
Heating up of the chip may require several milliseconds, depending
on external conditions
Figure 3b: Turn on into short circuit:
shut down by overtemperature, restart by cooling
(two parallel switched channels 1 and 2)
Figure 5a: Open load: detection in ON-state, open
load occurs in on-state
IN1/2
IN
I
L1
+I
L2
ST
2xIL(lim)
I
t
t
d(ST OL)
d(ST OL)
V
OUT
L(SCr)
off(SC)
I
ST1/2
normal
L
open
normal
t
t
td(ST OL) = 10 µs typ.
ST1 and ST2 have to be configured as a 'Wired OR' function
ST1/2 with a single pull-up resistor.
Semiconductor Group
t
12
2003-Oct-01
BTS 736 L2
Figure 5b: Open load: turn on/off to open load
IN
ST
I
t
d(STOL4)
L
t
Semiconductor Group
13
2003-Oct-01
BTS 736 L2
Package and Ordering Code
Published by
Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81669 München
© Infineon Technologies AG 2001
All Rights Reserved.
Standard: P-DSO-20-9
Sales Code
BTS 736 L2
Ordering Code
Q67060-S7011-A2
All dimensions in millimetres
Attention please!
The information herein is given to describe certain components and
shall not be considered as a guarantee of characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited
to warranties of non-infringement, regarding circuits, descriptions
and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions
and prices please contact your nearest Infineon Technologies Office
in Germany or our Infineon Technologies Representatives worldwide
(see address list).
Warnings
Due to technical requirements components may contain dangerous
substances. For information on the types in question please contact
your nearest Infineon Technologies Office.
Definition of soldering point with temperature Ts:
upper side of solder edge of device pin 15.
Infineon Technologies Components may only be used in life-support
devices or systems with the express written approval of Infineon
Technologies, if a failure of such components can reasonably be
expected to cause the failure of that life-support device or system, or
to affect the safety or effectiveness of that device or system. Life
support devices or systems are intended to be implanted in the
human body, or to support and/or maintain and sustain and/or
protect human life. If they fail, it is reasonable to assume that the
health of the user or other persons may be endangered.
Pin 15
Printed circuit board (FR4, 1.5mm thick, one layer
70µm, 6cm2 active heatsink area) as a reference for
max. power dissipation Ptot, nominal load current
IL(NOM) and thermal resistance Rthja
Semiconductor Group
14
2003-Oct-01