Low Voltage, 1.15 V to 5.5 V, 4-Channel, Bidirectional Logic Level Translator ADG3304-EP Bidirectional level translation Operates from 1.15 V to 5.5 V Low quiescent current < 5 μA No direction pin Supports defense and aerospace applications (AQEC standard) Military temperature range: −55°C to +125°C Controlled manufacturing baseline One assembly and test site One fabrication site Enhanced product change notification Qualification data available on request FUNCTIONAL BLOCK DIAGRAM VCCA VCCY A1 Y1 A2 Y2 A3 Y3 A4 Y4 EN GND 08845-001 FEATURES Figure 1. APPLICATIONS SPI®, MICROWIRE™ level translation Low voltage ASIC level translation Smart card readers Cell phones and cell phone cradles Portable communications devices Telecommunications equipment Network switches and routers Storage systems (SAN/NAS) GENERAL DESCRIPTIONS The ADG3304-EP is a bidirectional logic level translator that contains four bidirectional channels. It can be used in multivoltage digital system applications, such as data transfer, between a low voltage digital signal processing controller and a higher voltage device using SPI and MICROWIRE interfaces. The internal architecture allows the device to perform bidirectional logic level translation without an additional signal to set the direction in which the translation takes place. The voltage applied to VCCA sets the logic levels on the A side of the device, while VCCY sets the levels on the Y side. For proper operation, VCCA must always be less than VCCY. The VCCA-compatible logic signals applied to the A side of the device appear as VCCY-compatible levels on the Y side. Similarly, VCCY-compatible logic levels applied to the Y side of the device appear as VCCAcompatible logic levels on the A side. The enable pin (EN) provides three-state operation on both the A side and the Y side pins. When the EN pin is pulled low, the terminals on both sides of the device are in the high impedance state. The EN pin is referred to the VCCA supply voltage and driven high for normal operation. The ADG3304-EP is available in compact 14-lead TSSOP package. Full details about this enhanced product are available in the ADG3304 data sheet, which should be consulted in conjunction with this data sheet. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2010 Analog Devices, Inc. All rights reserved. ADG3304-EP TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................6 Applications....................................................................................... 1 ESD Caution...................................................................................6 Functional Block Diagram .............................................................. 1 Pin Configurations and Function Descriptions ............................7 General Descriptions ....................................................................... 1 Outline Dimensions ..........................................................................8 Revision History ............................................................................... 2 Ordering Guide .............................................................................8 Specifications..................................................................................... 3 REVISION HISTORY 10/10—Revision 0: Initial Version Rev. 0 | Page 2 of 8 ADG3304-EP SPECIFICATIONS VCCY = 1.65 V to 5.5 V, VCCA = 1.15 V to VCCY, GND = 0 V, TA = −55°C to +125°C unless otherwise noted. Table 1. Parameter LOGIC INPUTS/OUTPUTS A Side Input High Voltage 2 Input Low Voltage2 Output High Voltage Output Low Voltage Capacitance2 Leakage Current Y Side Input High Voltage2 Input Low Voltage2 Symbol Test Conditions/Comments Min VIHA VCCA = 1.2 V + 0.1 V/−0.05 V VCCA = 1.8 V ± 0.15 V VCCA = 2.5 V ± 0.2 V VCCA = 3.3 V ± 0.3 V VCCA = 5 V ± 0.5 V VCCA = 1.2 V + 0.1 V/−0.05 V VCCA = 1.8 V ± 0.15 V VCCA = 2.5 V ± 0.2 V VCCA = 3.3 V ± 0.3 V VCCA = 5 V ± 0.5 V VY = VCCY, IOH = 20 μA VY = 0 V, IOL = 20 μA f = 1 MHz, EN = 0 VA = 0 V/VCCA, EN = 0 VCCA × 0.88 VCCA × 0.72 1.7 2.2 VCCA × 0.7 VILA VOHA VOLA CA ILA, Hi-Z VIHY VILY Output High Voltage Output Low Voltage Capacitance2 Leakage Current Enable (EN) Input High Voltage2 VOHY VOLY CY ILY, Hi-Z Input Low Voltage2 VILEN Leakage Current Capacitance2 Enable Time2 ILEN CEN tEN VIHEN VCCY = 1.8 V ± 0.15 V VCCY = 2.5 V ± 0.2 V VCCY = 3.3 V ± 0.3 V VCCY = 5 V ± 0.5 V VCCY = 1.8 V ± 0.15 V VCCY = 2.5 V ± 0.2 V VCCY = 3.3 V ± 0.3 V VCCY = 5 V ± 0.5 V VA = VCCA, IOH = 20 μA VA = 0 V, IOL = 20 μA f = 1 MHz, EN = 0 VY = 0 V/VCCY, EN = 0 VCCA = 1.2 V + 0.1 V/−0.05 V VCCA = 1.8 V ± 0.15 V VCCA = 2.5 V ± 0.2 V VCCA = 3.3 V ± 0.3 V VCCA = 5 V ± 0.5 V VCCA = 1.2 V + 0.1 V/−0.05 V VCCA = 1.8 V ± 0.15 V VCCA = 2.5 V ± 0.2 V VCCA = 3.3 V ± 0.3 V VCCA = 5 V ± 0.5 V VEN = 0 V/VCCA, VA = 0 V RS = RT = 50 Ω VA = 0 V/VCCA (A→Y) VY = 0 V/VCCY (Y→A) Rev. 0 | Page 3 of 8 Typ 1 Max VCCA × 0.35 VCCA × 0.35 0.7 0.8 VCCA × 0.3 VCCA − 0.4 0.4 9 ±1 VCCY × 0.67 1.7 2 VCCY × 0.7 VCCY × 0.35 0.7 0.8 VCCY × 0.25 VCCY − 0.4 0.4 6 ±1 VCCA × 0.88 VCCA × 0.72 1.7 2.2 VCCA × 0.7 VCCA × 0.35 VCCA × 0.35 0.7 0.8 VCCA × 0.3 ±1 3 1 1.8 Unit V V V V V V V V V V V V pF μA V V V V V V V V V V pF μA V V V V V V V V V V μA pF μs ADG3304-EP Parameter SWITCHING CHARACTERISTICS2 3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V A→Y Level Translation Propagation Delay Symbol Test Conditions/Comments Min Typ 1 Max Unit ns RS = RT = 50 Ω, CL = 50 pF tP, A→Y 6 15 Rise Time tR, A→Y 2 5 ns Fall Time tF, A→Y 2 5 ns Maximum Data Rate DMAX, A→Y 50 Mbps Channel-to-Channel Skew tSKEW, A→Y 2 ns Part-to-Part Skew tPPSKEW, A→Y 3 ns Y→A Level Translation Propagation Delay RS = RT = 50 Ω, CL = 15 pF tP, Y→A 4 10 ns Rise Time tR, Y→A 1 5 ns Fall Time tF, Y→A 3 10 ns Maximum Data Rate DMAX, Y→A 50 Mbps Channel-to-Channel Skew tSKEW, Y→A 2 ns Part-to-Part Skew tPPSKEW, Y→A 2 ns 1.8 V ± 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V A→Y Translation Propagation Delay RS = RT = 50 Ω, CL = 50 pF tP, A→Y 8 15 Rise Time tR, A→Y 2 8 ns Fall Time tF, A→Y 2 8 ns Maximum Data Rate DMAX, A→Y 50 Mbps Channel-to-Channel Skew tSKEW, A→Y 2 ns Part-to-Part Skew tPPSKEW, A→Y 4 ns Y→A Translation Propagation Delay ns RS = RT = 50 Ω, CL = 15 pF 5 tP, Y→A 12 ns Rise Time tR, Y→A 2 5 ns Fall Time tF, Y→A 2 5 ns Maximum Data Rate DMAX, Y→A 50 Mbps Channel-to-Channel Skew tSKEW, Y→A 2 ns tPPSKEW, Y→A 3 ns Part-to-Part Skew 1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V A→Y Translation Propagation Delay RS = RT = 50 Ω, CL = 50 pF tP, A→Y 9 27 Rise Time tR, A→Y 3 8 ns Fall Time tF, A→Y 2 8 ns Maximum Data Rate DMAX, A→Y 40 Channel-to-Channel Skew tSKEW, A→Y 2 ns Part-to-Part Skew tPPSKEW, A→Y 10 ns Y→A Translation Propagation Delay ns Mbps RS = RT = 50 Ω, CL = 15 pF tP, Y→A 5 13 ns Rise Time tR, Y→A 2 6 ns Fall Time tF, Y→A 2 6 ns Maximum Data Rate DMAX, Y→A 40 Mbps Channel-to-Channel Skew tSKEW, Y→A 2 ns Part-to-Part Skew tPPSKEW, Y→A 4 ns Rev. 0 | Page 4 of 8 ADG3304-EP Parameter 1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 1.8 V ± 0.3 V A→Y Translation Propagation Delay Symbol Typ 1 Max Unit ns RS = RT = 50 Ω, CL = 50 pF tP, A→Y 12 35 tR, A→Y 7 18 ns Fall Time tF, A→Y 3 8 ns Maximum Data Rate DMAX, A→Y 25 Channel-to-Channel Skew tSKEW, A→Y 2 ns Part-to-Part Skew tPPSKEW, A→Y 15 ns Mbps RS = RT = 50 Ω, CL = 15 pF tP, Y→A 14 40 ns Rise Time tR, Y→A 5 24 ns Fall Time tF, Y→A 2.5 10 Maximum Data Rate DMAX, Y→A 25 Mbps Channel-to-Channel Skew tSKEW, Y→A 3 ns Part-to-Part Skew tPPSKEW, Y→A 23.5 ns 2.5 V ± 0.2 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V A→Y Translation Propagation Delay ns RS = RT = 50 Ω, CL = 50 pF tP, A→Y 7 15 Rise Time tR, A→Y 2.5 6 ns Fall Time tF, A→Y 2 8 ns Maximum Data Rate DMAX, A→Y 60 Mbps Channel-to-Channel Skew tSKEW, A→Y 1.5 ns 4 ns Part-to-Part Skew Y→A Translation Propagation Delay tPPSKEW, A→Y ns RS = RT = 50 Ω, CL = 15 pF tP, Y→A 5 12 Rise Time tR, Y→A 1 6 ns Fall Time tF, Y→A 3 8 ns Maximum Data Rate DMAX, Y→A 60 Mbps Channel-to-Channel Skew tSKEW, Y→A 2 ns Part-to-Part Skew tPPSKEW, Y→A 3 ns POWER REQUIREMENTS Power Supply Voltages Quiescent Power Supply Current VCCA VCCY ICCA ICCY Three-State Mode Power Supply Current 2 Min Rise Time Y→A Translation Propagation Delay 1 Test Conditions/Comments IHi-Z, A IHi-Z, Y VCCA ≤ VCCY VA = 0 V/VCCA, VY = 0 V/VCCY, VCCA = VCCY = 5.5 V, EN = 1 VA = 0 V/VCCA, VY = 0 V/VCCY, VCCA = VCCY = 5.5 V, EN = 1 VCCA = VCCY = 5.5 V, EN = 0 VCCA = VCCY = 5.5 V, EN = 0 TA for typical specifications is +25°C. Guaranteed by design, not production tested. Rev. 0 | Page 5 of 8 1.15 1.65 ns 0.17 5.5 5.5 5 V V μA 0.27 5 μA 0.1 0.1 5 5 μA μA ADG3304-EP ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 2. Parameter VCCA to GND VCCY to GND Digital Inputs (A) Digital Inputs (Y) EN to GND Operating Temperature Range Storage Temperature Range Junction Temperature θJA Thermal Impedance (4-Layer Board) 14-Lead TSSOP Lead Temperature, Soldering Vapor phase(60 sec) Infrared (15 sec) Rating −0.3 V to +7 V VCCA to +7 V −0.3 V to (VCCA + 0.3 V) −0.3 V to (VCCY + 0.3 V) −0.3 V to +7 V −55°C to +125°C −65°C to +150°C 150°C 112.6°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION 215°C 220°C Rev. 0 | Page 6 of 8 ADG3304-EP VCCA 1 14 VCCY A1 2 13 Y1 A2 3 ADG3304-EP 12 Y2 A3 4 TOP VIEW (Not to Scale) 11 Y3 A4 5 10 Y4 NC 6 9 NC GND 7 8 EN NC = NO CONNECT 08845-002 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 2. 14-Lead TSSOP Pin Configuration Table 3. 14-Lead TSSOP Pin Function Descriptions Pin No. 1 2 3 4 5 6, 9 7 8 10 11 12 13 14 Mnemonic VCCA A1 A2 A3 A4 NC GND EN Y4 Y3 Y2 Y1 VCCY Description Power Supply Voltage Input for the A1 to A4 I/O Pins (1.15 V ≤ VCCA ≤ VCCY). Input/Output A1. Referenced to VCCA. Input/Output A2. Referenced to VCCA. Input/Output A3. Referenced to VCCA. Input/Output A4. Referenced to VCCA. No Connect. Ground. Active High Enable Input. Input/Output Y4. Referenced to VCCY. Input/Output Y3. Referenced to VCCY. Input/Output Y2. Referenced to VCCY. Input/Output Y1. Referenced to VCCY. Power Supply Voltage Input for the Y1 to Y4 I/O Pins (1.65 V ≤ VCC ≤ 5.5 V). Table 4. Truth Table EN 0 1 1 2 Y I/O Pins Hi-Z1 Normal operation2 A I/O Pins Hi-Z1 Normal operation2 High impedance state. In normal operation, the ADG3304-EP performs level translation. Rev. 0 | Page 7 of 8 ADG3304-EP OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 SEATING PLANE 8° 0° COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 0.75 0.60 0.45 061908-A 1.05 1.00 0.80 Figure 3. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters ORDERING GUIDE Model ADG3304SRU-EP-RL7 Temperature Range −55°C to +125°C Package Description 14-Lead Thin Shrink Small Outline Package [TSSOP] © 2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08845-0-10/10(0) Rev. 0 | Page 8 of 8 Package Option RU-14