For Audio Equipment MN6460A A/D Converter for Digital Audio Equipment Overview The MN6460A is a 16-bit CMOS analog-to-digital converter designed especially for PCM digital audio equipment. It features a built-in digital filter. It uses noise shaping to convert an analog signal to a 16-bit digital signal. Incorporating digital filter permits simplification of the analog filter that normally precedes the A/D converter, thus greatly reducing the power consumption of the overall A/D conversion system. Features Analog and digital-mixed CMOS LSI A/D conversion using noise shaping 64-fold oversampling Built-in digital filter Pin Assignment DVDD LR–POL I–E LR–CLK B–CLK CLR OFCLR N.C. N.C. N.C. N.C. N.C. N.C. N.C. EXCLK CVSS CVDD N.C. N.C. AVSS AVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 Sample and hold circuit is unnecessary Serial output using two's complement code Built-in offset compensation circuit Built-in overflow limiter Single 5-volt power supply (when V REF =1.5 V and AG=2.5 V) Applications DAT players and other digital audio equipment (TOP VIEW) SSOP042-P-0450 DVSS TEST N.C. DOUT N.C. NSUB N.C. N.C. N.C. N.C. TCLK N.C. N.C. N.C. AMPBIAS N.C. AVSS AVDD AIN AG VREF MN6460A For Auido Equipment Block Diagram DSQ:1bit Delta Sigma Quantizer 1st DSQ (+) 24 3rd DSQ 2nd DSQ + AIN × 1/2 – × 1/2 1st DSQ (–) Summing logic A/D converter 15 Clock Generator FIR 1 Comb-filter FIR 2 Low-pass-filter 6 Digital filter 5 B-CLK 4 LR-CLK 3 I-E 2 LR-POL 7 39 P/S Converter OFFSET Canceller OFCLR EXCLK CLR DOUT For Audio Equipment MN6460A Pin Descriptions Pin No. Symbol 1 DVDD 2 LR-POL Function Description Power supply pin for digital circuits (+5 V) Channel selection pin for stereo operation using two chips. "H" level: right channel. "L" level: left channel. 3 I-E 4 LR-CLK Format selection pin. "L" level: signal processing LSI format. "H" level: I2S format. LRCLK input pin (for stereo operation) If LR-POL is at "H" level, "H" level: right channel data output. "L" level, high-impedance state. If LR-POL is at "L" level, "H" level: high-impedance state. "L" level, left channel data output. 5 B-CLK 6 CLR Bit transfer command input (At falling edge signal, a bit transfered) Clear pin. Active high. Driving this pin at "H" level clears internal data. Always this internal data is cleared by feeding a positive pulse to this pin after applying the power. 7 OFCLR 8 N.C. Driving this pin at "L" level enables the offset clear circuit. No connection (Leave this pin open.) 9 N.C. No connection (Leave this pin open.) 10 N.C. No connection (Leave this pin open.) 11 N.C. No connection (Leave this pin open.) 12 N.C. No connection (Leave this pin open.) 13 N.C. No connection (Leave this pin open.) 14 N.C. 15 EXCLK No connection (Leave this pin open.) 512 fs input pin 16 CV SS Ground pin for digital circuits 17 CV DD Power supply pin for digital circuits (+5 V) 18 N.C. No connection (Leave this pin open.) 19 N.C. No connection (Leave this pin open.) 20 AVSS Ground pin for analog circuits 21 AVDD Power supply pin for analog circuits (+5 V) 22 VREF Analog circuit reference voltage input pin (+1.5 V) 23 AG Analog ground input pin (+2.5 V) 24 AIN 25 AVDD Power supply pin for analog circuits (+5 V) Analog input pin 26 AVSS Ground pin for analog circuits 27 N.C. No connection (Leave this pin open.) 28 AMPBIAS Bias voltage adjustment pin for operational amplifier (Keep this at the same voltage as the AG pin.) 29 N.C. No connection (Leave this pin open.) 30 N.C. No connection (Leave this pin open.) 31 N.C. No connection (Leave this pin open.) MN6460A For Auido Equipment Pin Descriptions (continued) Pin No. Symbol 32 TCLK Function Description 33 N.C. No connection (Leave this pin open.) 34 N.C. No connection (Leave this pin open.) 35 N.C. No connection (Leave this pin open.) 36 N.C. No connection (Leave this pin open.) 37 NSUB 38 N.C. 39 DOUT 40 N.C. 41 TEST LSI test pin. (Connect this pin to DVDD .) 42 DVSS Ground pin for digital circuits LSI test clock output pin. (Leave this pin open.) Connect this pin to AVDD . No connection (Leave this pin open.) Serial output pin. Two's complement. MSB first. No connection (Leave this pin open.) Electrical Characteristics Conversion Characteristics DV DD=5.0V, AVDD=5.0V, V AG=2.5V, V REF=1.5V, fEXCLK=24.576MHz, Ta=25˚C Symbol Test Condition min typ Signal-to-noise ratio Parameter S/N EIAJ (1kHz) 85 90 dB Dynamic range D.R. EIAJ (1KHZ) 85 90 dB THD+N EIAJ (1kHz) Total harmonic 0.005 max 0.010 Unit % distortion Specifications for DC Offset An A/D converter usually does not produce digital zero output from analog zero input because the operational amplifier inside has an offset. The MN6460A, however, has circuitry for correcting this. The shipping inspection enables this offset correction circuit and confirms that the DC offset is within the lower four bits. Parameter DC offset Symbol Test Condition min typ max Unit OFCLR="H" ±20 mV OFCLR="L" ±0.6 mV For Audio Equipment MN6460A C5 0.1µF C15 15 14 13 12 11 10 9 HC161.counter 5 6 7 8 10µF 1 2 3 4 5 14 4.7µF 13 12 11 10 + C7 9 8 HC74.D-FF C22 6 7 8 1 2 3 4 5 6 7 256Fs C8 512Fs + 4.7µF 16 + 4.7µF R7 10kΩ + 15 14 13 12 11 10 9 14 HC161.counter C16 1 2 3 4 5 13 12 11 10 9 8 XTAL.512Fs C23 4.7µF 6 7 8 1 2 3 4 5 16 15 14 13 12 11 4.7µF 20 19 18 17 + SW1 GND 4.7µF 16 + C1 4.7µF 4.7µF HC123 1 2 3 4 C15 + 100µF 15 14 13 12 11 10 9 + – + C16 5V 16 + R1 10kΩ D1 CLR 256Fs LRCK DATA BCK Application Circuit Example C44 HC244 1 2 6 7 3 4 5 6 7 8 9 10 R18 330Ω 14 13 12 11 10 7 1 2 3 4 C3 4.7µF 5 1.2kΩ 1.2kΩ Ain(R) 4 5 6 7 C30 3.3µF + R15 10kΩ + C13 10kΩ1kΩ VR4 R14 10kΩ 22µF 22µF VR5 10kΩ + C42 R28 4.7kΩ 22kΩ R13 4.7µF 1kΩ 33µF + – + – R10 R22 100µF R21 R9 C33 – C38 + HAF0614.LPF – 1 2 3 100µF 100µF 4 100µF 5 6 7 C31 + C28 1 2 3 0.1µF R14 R12 + C27 C32 C29 A.GND –12V 33µF 3 2 1 8 C13 C37 C34 22µF 10kΩ 22µF 10kΩ R5 4 6 7 0.1µF 100µF 1000pF C41 1.2kΩ 100pF VR1 C19 1.2kΩ R5 Ain(L) 1kΩ R3 10kΩ R12 10kΩ1kΩ 100µF 22µF + C13 C13 3.3µF+ C11 10kΩ + R4 C5 C41 + + – R8 4.7kΩ 22kΩ R7 10kΩ 4.7µF C18 C43 4.7µF R17 C41 VR2 VR5 C36 C17 0.1µF 10kΩ R23 10kΩ 100pF 4.7µF + C19 HAF0614.LPF 1000pF C14 10µF C26 + 100µF + + C41 C41 4.7µF + MN6460A VR3 10kΩ 0.1µF C23 R11 4.7µF + C41 + EXCLK-R + DVSS 42 1 DVDD TEST 41 2 LR-POL N.C. 40 3 I-E DOUT 39 4 LR-CLK N.C. 38 5 B-CLK NSUB 37 6 CLR 7 OFCLR N.C. 36 N.C. 35 8 N.C. N.C. 9 N.C. N.C. 33 10 N.C. TCLK 32 11 N.C.(TP0) N.C. 31 12 N.C.(TP1) N.C. 30 13 N.C.(TP2) N.C. 29 14 N.C.(TP3) 15 EXCLK AMPBIAS 28 N.C. 27 16 CVSS AVSS 26 17 CVDD AVDD 25 18 N.C. AIN 24 19 N.C. AG 23 20 AVSS VREF 22 21 AVDD 4.7µF 10kΩ 1 DVDD DVSS 42 2 LR-POL TEST 41 3 I-E N.C. 40 4 LR-CLK DOUT 39 5 B-CLK N.C. 38 6 CLR NSUB 37 7 OFCLR N.C. 36 N.C. 35 8 N.C. N.C. 34 9 N.C. N.C. 33 10 N.C. 11 N.C.(TP0) TCLK 32 N.C. 31 12 N.C.(TP1) N.C. 30 13 N.C.(TP2) N.C. 29 14 N.C.(TP3) 15 EXCLK AMPBIAS 28 N.C. 27 16 CVSS AVSS 26 17 CVDD AVDD 25 18 N.C. AIN 24 19 N.C. AG 23 20 AVSS VREF 22 21 AVDD MN6460A EXCLK-L + + C5 + 100µF R16 + + 10µF C12 C16 C2 C15 C16 C5 + C15 4.7µF 4.7µF + 100µF – + A.GND C41 C33 – 4.7µF 4.7kΩ 10µF – A.VDD 7 SW + C3 12V 6 4.7µF + 100µF 4.7µF D.GND + D.VDD 5 LR-CLK B-CLK CLR OFCLR 10µF – 8 34 + – C24 + 5 6 + 1 2 3 4 9 HC32 4.7µF HC32 EXCLK-R 8 EXCLK-L 14 13 12 11 10 9 MN6460A For Auido Equipment Package Dimensions (Unit: mm) SSOP042-P-0450 21.25±0.20 42 22 1.0 0.35±0.10 +0.10 2.4max. 0.1±0.1 (0.6) 0.15 -0.05 0 to 10° 0.3min. 21 2.0±0.2 1 11.5±0.3 9.5±0.2 1.0±0.2 SEATING PLANE