PD -95104
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Advanced Process Technology
Ultra Low On-Resistance
Dynamic dv/dt Rating
175°C Operating Temperature
Fast Switching
Fully Avalanche Rated
Lead-Free
IRF1404SPbF
IRF1404LPbF
HEXFET® Power MOSFET
D
RDS(on) = 0.004Ω
G
Description
ID = 162A
S
Seventh Generation HEXFET® Power MOSFETs from
International Rectifier utilize advanced processing
techniques to achieve extremely low on-resistance per
silicon area. This benefit, combined with the fast
switching speed and ruggedized device design that
HEXFET power MOSFETs are well known for, provides
the designer with an extremely efficient and reliable
device for use in a wide variety of applications.
The D2Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible onresistance in any existing surface mount package. The
D2Pak is suitable for high current applications because of
its low internal connection resistance and can dissipate up
to 2.0W in a typical surface mount application.
The through-hole version (IRF1404L) is available for lowprofile applications.
VDSS = 40V
D2Pak
IRF1404SPbF
TO-262
IRF1404LPbF
Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TA = 25°C
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Parameter
Max.
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
162
115
650
3.8
200
1.3
± 20
519
95
20
5.0
-55 to +175
-55 to +175
300 (1.6mm from case )
Units
W
W
W/°C
V
mJ
A
mJ
V/ns
Typ.
Max.
Units
–––
–––
0.75
40
°C/W
A
°C
Thermal Resistance
Parameter
RθJC
RθJA
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Junction-to-Case
Junction-to-Ambient (PCB mounted, steady-state)*
1
03/11/04
IRF1404S/LPbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
RDS(on)
VGS(th)
gfs
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Forward Transconductance
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
40
–––
–––
2.0
106
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
IDSS
Drain-to-Source Leakage Current
LS
Internal Source Inductance
–––
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
–––
–––
–––
–––
–––
–––
V(BR)DSS
∆V(BR)DSS/∆TJ
I GSS
Typ. Max. Units
Conditions
––– –––
V
VGS = 0V, ID = 250µA
0.036 ––– V/°C Reference to 25°C, ID = 1mA
0.00350.004
Ω
VGS = 10V, ID = 95A
––– 4.0
V
VDS = 10V, ID = 250µA
––– –––
S
VDS = 25V, ID = 60A
––– 20
VDS = 40V, VGS = 0V
µA
––– 250
VDS = 32V, VGS = 0V, TJ = 150°C
––– 200
VGS = 20V
nA
––– -200
VGS = -20V
160 200
ID = 95A
35 –––
nC
VDS = 32V
42
60
VGS = 10V
17 –––
VDD = 20V
140 –––
ID = 95A
ns
72 –––
RG = 2.5Ω
26 –––
RD = 0.21Ω
Between lead,
nH
7.5 –––
and center of die contact
7360 –––
VGS = 0V
1680 –––
VDS = 25V
240 –––
pF
ƒ = 1.0MHz, See Fig. 5
6630 –––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
1490 –––
VGS = 0V, VDS = 32V, ƒ = 1.0MHz
1540 –––
VGS = 0V, VDS = 0V to 32V
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11)
Starting TJ = 25°C, L = 0.12mH
RG = 25Ω, IAS = 95A. (See Figure 12)
ISD ≤ 95A, di/dt ≤ 150A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
––– ––– 162
showing the
A
G
integral reverse
––– ––– 650
S
p-n junction diode.
––– ––– 1.3
V
TJ = 25°C, IS = 95A, VGS = 0V
––– 71 110
ns
TJ = 25°C, IF = 95A
––– 180 270
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 75A
Use IRF1404 data and test conditions.
Pulse width ≤ 300µs; duty cycle ≤ 2%.
* When mounted on 1" square PCB ( FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
2
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IRF1404S/LPbF
1000
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
4.5V
100
100
4.5V
20µs PULSE WIDTH
TJ = 25 °C
10
0.1
1
10
10
0.1
100
1000
RDS(on) , Drain-to-Source On Resistance
(Normalized)
2.5
I D , Drain-to-Source Current (A)
TJ = 25 ° C
TJ = 175 ° C
100
V DS = 25V
20µs PULSE WIDTH
5.0
6.0
7.0
8.0
Fig 3. Typical Transfer Characteristics
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10
100
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
VGS , Gate-to-Source Voltage (V)
1
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
10
4.0
20µs PULSE WIDTH
TJ = 175 ° C
9.0
ID = 159A
2.0
1.5
1.0
0.5
0.0
-60 -40 -20 0
VGS = 10V
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRF1404S/LPbF
VGS = 0V,
f = 1MHz
Ciss = Cgs + Cgd , Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
C, Capacitance (pF)
10000
Ciss
8000
6000
4000
Coss
2000
20
VGS , Gate-to-Source Voltage (V)
12000
1
10
12
8
4
0
100
VDS , Drain-to-Source Voltage (V)
0
40
80
120
160
200
240
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
10000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
TJ = 175 ° C
1000
ID , Drain Current (A)
ISD , Reverse Drain Current (A)
FOR TEST CIRCUIT
SEE FIGURE 13
QG , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
100
10us
100us
100
TJ = 25 ° C
10
1
0.4
V GS = 0 V
0.8
1.2
1.6
2.0
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
VDS = 32V
VDS = 20V
16
Crss
0
ID = 95A
2.4
1ms
10ms
10
1
TC = 25 °C
TJ = 175 °C
Single Pulse
1
10
100
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRF1404S/LPbF
200
LIMITED BY PACKAGE
VGS
160
ID , Drain Current (A)
RD
VDS
D.U.T.
RG
120
+
-V DD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
80
Fig 10a. Switching Time Test Circuit
40
VDS
90%
0
25
50
75
100
125
150
175
TC , Case Temperature ( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response(Z thJC )
1
D = 0.50
0.20
0.1
0.10
PDM
0.05
t1
0.02
0.01
0.01
0.00001
t2
SINGLE PULSE
(THERMAL RESPONSE)
0.0001
Notes:
1. Duty factor D = t 1 / t 2
2. Peak TJ = P DM x Z thJC + TC
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRF1404S/LPbF
D.U.T
RG
+
V
- DD
IAS
20V
0.01Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp
TOP
1000
DRIVER
L
VDS
EAS , Single Pulse Avalanche Energy (mJ)
1200
15V
A
I AS
BOTTOM
ID
39A
67A
95A
800
600
400
200
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature( ° C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
QG
QGS
QGD
50
VG
Charge
Fig 13a. Basic Gate Charge Waveform
Current Regulator
Same Type as D.U.T.
50KΩ
12V
.2µF
.3µF
D.U.T.
+
V
- DS
48
46
44
42
40
0
VGS
20
40
60
80
100
IAV , Avalanche Current ( A)
3mA
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
6
V DSav , Avalanche Voltage ( V )
10 V
Fig 12d. Typical Drain-to-Source Voltage
Vs. Avalanche Current
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IRF1404S/LPbF
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
RG
•
•
•
•
Driver Gate Drive
P.W.
+
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Period
D=
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-channel HEXFET® Power MOSFETs
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7
IRF1404S/LPbF
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information (Lead-Free)
T H IS IS AN IR F 5 3 0 S W IT H
L OT CODE 80 2 4
AS S E M B L E D ON W W 0 2, 20 00
IN T H E AS S E M B L Y L IN E "L "
IN T E R N AT IO N AL
R E C T IF IE R
L OGO
N ote: "P " in as s em bly lin e
po s itio n in dicates "L ead-F r ee"
P AR T N U M B E R
F 5 30 S
AS S E M B L Y
L O T CO D E
D AT E C O D E
Y E AR 0 = 2 0 0 0
W E E K 02
L IN E L
OR
IN T E R N AT IO N AL
R E C T IF IE R
L O GO
AS S E M B L Y
L OT COD E
8
P AR T N U M B E R
F 530S
D AT E CO D E
P = D E S IG N AT E S L E AD -F R E E
P R O D U C T (O P T IO N AL )
Y E AR 0 = 2 0 0 0
W E E K 02
A = AS S E M B L Y S IT E CO D E
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IRF1404S/LPbF
TO-262 Package Outline
IGBT
1- GATE
2- COLLECTOR
3- EMITTER
TO-262 Part Marking Information
EXAMPLE: T HIS IS AN IRL3103L
LOT CODE 1789
AS SEMBLED ON WW 19, 1997
IN T HE ASS EMBLY LINE "C"
Note: "P" in as s embly line
pos ition indicates "Lead-Free"
INT ERNAT IONAL
RECT IFIER
LOGO
ASS EMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 7 = 1997
WEEK 19
LINE C
OR
INT ERNAT IONAL
RECT IFIER
LOGO
AS S EMBLY
LOT CODE
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PART NUMBER
DAT E CODE
P = DES IGNAT ES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 7 = 1997
WEEK 19
A = AS S EMBLY S ITE CODE
9
IRF1404S/LPbF
D2Pak Tape & Reel Infomation
Dimensions are shown in millimeters (inches)
TRR
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
11.60 (.457)
11.40 (.449)
0.368 (.0145)
0.342 (.0135)
15.42 (.609)
15.22 (.601)
24.30 (.957)
23.90 (.941)
TRL
10.90 (.429)
10.70 (.421)
1.75 (.069)
1.25 (.049)
4.72 (.136)
4.52 (.178)
16.10 (.634)
15.90 (.626)
FEED DIRECTION
13.50 (.532)
12.80 (.504)
27.40 (1.079)
23.90 (.941)
4
330.00
(14.173)
MAX.
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
60.00 (2.362)
MIN.
26.40 (1.039)
24.40 (.961)
3
30.40 (1.197)
MAX.
4
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.03/04
10
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/