PD - 9.1497A
IRLI540N
PRELIMINARY
HEXFET® Power MOSFET
Logic-Level Gate Drive
Advanced Process Technology
l Isolated Package
l High Voltage Isolation = 2.5KVRMS
l Sink to Lead Creepage Dist. = 4.8mm
l Fully Avalanche Rated
Description
l
D
l
VDSS = 100V
RDS(on) = 0.044Ω
G
ID = 23A
S
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power
MOSFETs are well known for, provides the designer
with an extremely efficient and reliable device for use
in a wide variety of applications.
The TO-220 Fullpak eliminates the need for additional
insulating hardware in commercial-industrial
applications. The moulding compound used provides
a high isolation capability and a low thermal resistance
between the tab and external heatsink. This isolation
is equivalent to using a 100 micron mica barrier with
standard TO-220 product. The Fullpak is mounted to
a heatsink using a single clip or by a single screw
fixing.
TO-220 FULLPAK
Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Parameter
Max.
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Mounting torque, 6-32 or M3 screw
23
16
120
54
0.36
± 16
310
18
5.4
5.0
-55 to + 175
Units
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
300 (1.6mm from case )
10 lbf•in (1.1N•m)
Thermal Resistance
Parameter
RθJC
RθJA
Junction-to-Case
Junction-to-Ambient
Typ.
Max.
Units
–––
–––
2.8
65
°C/W
3/16/98
IRLI540N
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
∆V(BR)DSS/∆TJ
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
V(BR)DSS
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
LD
Internal Drain Inductance
LS
Internal Source Inductance
Ciss
Coss
Crss
C
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Drain to Sink Capacitance
IGSS
Min.
100
–––
–––
–––
–––
1.0
14
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
0.11
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
11
81
39
62
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA
0.044
VGS = 10V, ID = 12A
0.053
Ω
VGS = 5.0V, ID = 12A
0.063
VGS = 4.0V, ID = 10A
2.0
V
VDS = VGS , ID = 250µA
–––
S
VDS = 25V, ID = 18A
25
VDS = 100V, VGS = 0V
µA
250
VDS = 80V, VGS = 0V, TJ = 150°C
100
VGS = 16V
nA
-100
VGS = -16V
74
ID = 18A
9.4
nC
VDS = 80V
38
VGS = 5.0V, See Fig. 6 and 13
–––
VDD = 50V
–––
ID = 18A
ns
–––
RG = 5.0Ω, VGS = 5.0V
–––
RD = 2.7Ω, See Fig. 10
Between lead,
––– 4.5 –––
6mm (0.25in.)
nH
G
from package
––– 7.5 –––
and center of die contact
––– 1800 –––
VGS = 0V
––– 350 –––
VDS = 25V
pF
––– 170 –––
ƒ = 1.0MHz, See Fig. 5
–––
12 –––
ƒ = 1.0MHz
Source-Drain Ratings and Characteristics
IS
ISM
VSD
trr
Q rr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Starting TJ = 25°C, L = 1.9mH
RG = 25Ω, IAS = 18A. (See Figure 12)
ISD ≤ 18A, di/dt ≤ 180A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
23
––– –––
showing the
A
G
integral reverse
––– ––– 120
p-n junction diode.
S
––– ––– 1.3
V
TJ = 25°C, IS = 18A, VGS = 0V
––– 190 290
ns
TJ = 25°C, IF = 18A
––– 1.1 1.7
µC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Pulse width ≤ 300µs; duty cycle ≤ 2%.
t=60s, ƒ=60Hz
Uses IRL540N data and test conditions
D
S
IRLI540N
1000
1000
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
VGS
15V
12V
10V
8.0V
6.0V
4.0V
3.0V
BOTTOM 2.5V
TOP
ID , Drain-to-Source Current (A)
ID , Drain-to-Source Current (A)
TOP
100
10
2.5V
20µs PULSE WIDTH
T J = 25°C
1
0.1
1
10
A
100
10
2.5V
20µs PULSE WIDTH
T J = 175°C
1
100
0.1
1
V D S , Drain-to-Source Voltage (V)
Fig 2. Typical Output Characteristics
3.0
R D S ( o n ) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
1000
TJ = 25°C
TJ = 175°C
10
V D S = 50V
20µs PULSE WIDTH
1
2
4
6
8
V G S , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
A
100
V D S , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
100
10
10
A
I D = 30A
2.5
2.0
1.5
1.0
0.5
V G S = 10V
0.0
-60
-40
-20
0
20
40
60
80
A
100 120 140 160 180
T J , Junction Temperature (°C)
Fig 4. Normalized On-Resistance
Vs. Temperature
IRLI540N
15
3000
V G S , Gate-to-Source Voltage (V)
V G S = 0V,
f = 1MHz
C iss = C gs+ C gd
, C SHORTED
ds
C rss = C gd
C oss = C ds+ C gd
C, Capacitance (pF)
2000
C oss
C rss
0
10
9
6
3
FOR TEST CIRCUIT
SEE FIGURE 13
0
A
1
V D S = 80V
V D S = 50V
V D S = 20V
12
C iss
1000
I D = 18A
0
100
40
60
80
A
100
Q G , Total Gate Charge (nC)
V D S , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
1000
1000
OPERATION IN THIS AREA LIMITED
BY RD S ( o n )
I D , Drain Current (A)
I S D , Reverse Drain Current (A)
20
100
TJ = 175°C
T J = 25°C
10
100
10µs
100µs
10
1ms
VG S = 0V
1
0.4
0.6
0.8
1.0
1.2
1.4
1.6
V S D , Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
A
1.8
T C = 25°C
T J = 175°C
Single Pulse
1
1
10ms
10
100
V D S , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
A
1000
IRLI540N
25
RD
VDS
VGS
I D , Drain Current (A)
20
D.U.T.
RG
+
-VDD
15
5.0V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
10
Fig 10a. Switching Time Test Circuit
5
VDS
90%
0
25
50
75
100
125
150
175
TC , Case Temperature ( ° C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
D = 0.50
1
0.20
0.10
0.05
0.1
0.01
0.00001
P DM
0.02
0.01
t1
t2
SINGLE PULSE
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
10
L
VD S
D .U .T
RG
IA S
10V
tp
D R IV E R
+
- VD D
A
0.0 1 Ω
Fig 12a. Unclamped Inductive Test Circuit
800
TOP
BOTTOM
ID
7.3A
13A
18A
600
400
200
E AS ,
1 5V
Single Pulse Avalanche Energy (mJ)
IRLI540N
A
0
25
V (B R )D SS
tp
50
75
100
125
150
Starting T J , Junction Temperature (°C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
IAS
Current Regulator
Same Type as D.U.T.
Fig 12b. Unclamped Inductive Waveforms
50KΩ
12V
.2µF
QG
.3µF
5.0 V
QGS
D.U.T.
QGD
+
V
- DS
VGS
VG
3mA
IG
Charge
Fig 13a. Basic Gate Charge Waveform
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
175
IRLI540N
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
•
•
•
•
RG
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
D=
Period
P.W.
+
-
VDD
P.W.
Period
VGS=10V
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
ISD
*
IRLI540N
Package Outline
TO-220 Fullpak Outline
Dimensions are shown in millimeters (inches)
1 0 .6 0 (.4 1 7 )
1 0 .4 0 (.4 0 9 )
ø
3 .4 0 (.1 3 3 )
3 .1 0 (.1 2 3 )
4 .8 0 ( .1 89 )
4 .6 0 ( .1 81 )
-A 3 .7 0 (.14 5 )
3 .2 0 (.12 6 )
1 6 .0 0 (.6 3 0 )
1 5 .8 0 (.6 2 2 )
2 .80 (.1 10 )
2 .60 (.1 02 )
L E A D A S S IG N M E N T S
1 - G A TE
2 - D R A IN
3 - S O U RC E
7 .1 0 (.2 8 0 )
6 .7 0 (.2 6 3 )
1 .1 5 (.0 4 5)
M IN.
NO T E S :
1 D IME N S IO N ING & T O L E R A N C ING
P E R A N S I Y 1 4 .5 M , 1 9 8 2
1
2
3
2 C O N TR O L L ING D IM E N S IO N: IN C H .
3.3 0 (.13 0 )
3.1 0 (.12 2 )
-B -
1 3 .7 0 (.5 4 0 )
1 3 .5 0 (.5 3 0 )
C
A
1 .4 0 (.0 5 5)
3X
1 .0 5 (.0 4 2)
0 .9 0 (.0 3 5 )
3X 0 .7 0 (.0 2 8 )
0 .2 5 (.0 1 0)
3X
M
A M
B
2 .54 (.1 0 0)
2X
0 .4 8 (.0 1 9 )
0 .4 4 (.0 1 7 )
2 .85 (.1 1 2 )
2 .65 (.1 0 4 )
D
B
M IN IM U M C R E E P A G E
D IS T A NC E B E T W E E N
A -B -C -D = 4.8 0 (.1 89 )
Part Marking Information
TO-220 Fullpak
E X A M P LE : TH IS IS A N IR FI840 G
W ITH AS S E M B LY
LO T CO DE E 401
A
IN TE R N AT IO NA L
RE C TIF IE R
LOGO
P AR T NU M B ER
IR F I8 40G
E 4 01 9 24 5
A S S EM BL Y
LO T CO DE
DA T E CO D E
(Y YW W )
YY = YE A R
W W = W EEK
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T 3Z2, Tel: (905) 453 2200
IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590
IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IR FAR EAST: 171 (K&H Bldg.) 30-4 Nishi-ikebukuro 3-chome, Toshima-ku, Tokyo Japan Tel: 81 33 983 0086
IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 16907 Tel: 65 221 8371
Data and specifications subject to change without notice.
3/98