PD - 9.1333B IRLR/U3103 PRELIMINARY HEXFET® Power MOSFET l l l l l l l Logic-Level Gate Drive Ultra Low On-Resistance Surface Mount (IRLR3103) Straight Lead (IRLU3103) Advanced Process Technology Fast Switching Fully Avalanche Rated D VDSS = 30V RDS(on) = 0.019Ω G ID = 46A S Description Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve the lowest possible on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient device for use in a wide variety of applications. D -P A K T O -2 52 A A The D-PAK is designed for surface mounting using vapor phase, infrared, or wave soldering techniques. The straight lead version (IRFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 watts are possible in typical surface mount applications. I-P A K TO -2 5 1 A A Absolute Maximum Ratings ID @ TC = 25°C ID @ TC = 100°C IDM PD @TC = 25°C VGS EAS IAR EAR dv/dt TJ T STG Parameter Max. Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds 46 29 220 69 0.56 ±16 240 34 6.9 2.0 -55 to + 150 Units A W W/°C V mJ A mJ V/ns °C 300 (1.6mm from case) Thermal Resistance Parameter Min. Typ. RθJC Junction-to-Case –––– –––– RθJA Junction-to-Ambient (PCB mount)** –––– –––– RθJA Junction-to-Ambient –––– –––– ** When mounted on 1" square PCB (FR-4 or G-10 Material ) . For recommended footprint and soldering techniques refer to application note #AN-994 Max. Units 1.8 50 110 °C/W 8/7/96 IRLR/U3103 Electrical Characteristics @ TJ = 25°C (unless otherwise specified) ∆V(BR)DSS/∆TJ Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance VGS(th) gfs Gate Threshold Voltage Forward Transconductance IDSS Drain-to-Source Leakage Current V(BR)DSS Qg Qgs Qgd td(on) tr td(off) tf Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time LD Internal Drain Inductance LS Internal Source Inductance Ciss Coss Crss Input Capacitance Output Capacitance Reverse Transfer Capacitance I GSS Min. 30 ––– ––– ––– 1.0 23 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– Typ. ––– 0.037 ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– ––– 9.0 210 20 54 Max. Units Conditions ––– V VGS = 0V, I D = 250µA ––– V/°C Reference to 25°C, I D = 1mA 0.019 VGS = 10V, ID = 28A Ω 0.024 VGS = 4.5V, I D = 23A ––– V VDS = VGS , ID = 250µA ––– S VDS = 25V, I D = 34A 25 VDS = 30V, VGS = 0V µA 250 VDS = 24V, VGS = 0V, TJ = 125°C 100 V GS = 16V nA -100 VGS = -16V 50 ID = 34A 14 nC VDS = 24V 28 V GS = 4.5V, See Fig. 6 and 13 ––– VDD = 15V ––– I D = 34A ns ––– RG = 3.4Ω, VGS = 4.5V ––– RD = 0.43Ω, See Fig. 10 Between lead, ––– 4.5 ––– 6mm (0.25in.) nH from package ––– 7.5 ––– and center of die contact ––– 1600 ––– VGS = 0V ––– 640 ––– pF VDS = 25V ––– 320 ––– ƒ = 1.0MHz, See Fig. 5 D G S Source-Drain Ratings and Characteristics IS ISM VSD trr Qrr ton Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse RecoveryCharge Forward Turn-On Time Min. Typ. Max. Units Conditions MOSFET symbol ––– ––– 46 showing the A G integral reverse ––– ––– 220 p-n junction diode. ––– ––– 1.3 V TJ = 25°C, IS = 28A, VGS = 0V ––– 81 120 ns TJ = 25°C, IF = 34A ––– 210 310 nC di/dt = 100A/µs Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) D S Specification changes Rev. # Parameters Old spec. New spec. Comments Revision Date 1 VGS(th) (Max.) 2.5V No spec. Removed VGS(th) Max. Specification 5/1/96 ±20 ±16 Decrease VGS Max. Specification 5/1/96 1 VGS (Max.) Notes: Repetitive rating; pulse width limited by Pulse width ≤ 300µs; duty cycle ≤ 2%. max. junction temperature. ( See fig. 11 ) Caculated continuous current based on maximum allowable junction temperature; VDD = 15V, starting TJ = 25°C, L = 300µH Package limitation current = 20A. RG = 25Ω, IAS = 34A. (See Figure 12) This is applied for I-PAK, LS of D-PAK is measured between lead and center of I SD ≤ 34A, di/dt ≤ 140A/µs, VDD ≤ V(BR)DSS , die contact Uses IRL3103 data and test conditions. TJ ≤ 150°C IRLR/U3103 1000 1000 VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTT OM 2.5V VGS 15V 12V 10V 8.0V 6.0V 4.0V 3.0V BOTTOM 2.5V TOP ID , D ra in -to -S o u rce C u rre n t (A ) ID , D ra in -to -S o u rce C u rre n t (A ) TOP 100 10 100 10 2.5 V 2.5 V 20 µ s PU LSE W ID TH T J = 2 5°C 1 0.1 1 10 2 0µ s PU L SE W ID TH T J = 1 50 °C 1 A 100 0.1 1 V D S , Drain-to-Source V oltage (V ) Fig 2. Typical Output Characteristics, T J = 150o C 2.0 R D S (o n ) , D ra in -to -S o u rc e O n R e si sta n ce (N o rm a li ze d ) I D , D r ain- to-S ourc e C urre nt (A ) 1000 T J = 2 5 °C TJ = 1 5 0 ° C 10 V DS = 1 5 V 2 0 µ s P U L S E W ID T H 1 2.0 3.0 4.0 5.0 6.0 7.0 8.0 A 100 V D S , Drain-to-S ource Voltage (V ) Fig 1. Typical Output Characteristics, T J = 25oC 100 10 9.0 V G S , G ate-to -S ource V olta ge (V ) Fig 3. Typical Transfer Characteristics A I D = 46 A 1.5 1.0 0.5 V G S = 10 V 0.0 -60 -40 -20 0 20 40 60 80 A 100 120 140 160 T J , Junction T emperature (°C) Fig 4. Normalized On-Resistance Vs. Temperature IRLR/U3103 2800 C iss C , C a p a c ita n c e (p F ) 2400 V GS C is s C rs s C os s = = = = 15 0V , f = 1MH z C gs + C g d , Cds SH OR TED Cgd C ds + C gd V G S , G a te -to -S o u rce V o lta g e (V ) 3200 C os s 2000 1600 1200 C rs s 800 I D = 34A V DS = 2 4V V DS = 1 5V 12 9 6 3 400 0 0 A 1 10 FO R TEST CIR CU IT SEE FIG UR E 13 0 100 V D S , Drain-to-Source V oltage (V) 20 30 40 50 60 A 70 Q G , T otal Gate C harge (nC ) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 1000 1000 OPE R ATIO N IN TH IS A RE A LIMITE D BY R D S(o n) I D , D ra in C u rre n t (A ) I S D , R e v e rse D ra in C u rre n t (A ) 10 100 TJ = 15 0°C T J = 25 °C 10µ s 100 1 00µs 10 1m s 10m s VG S = 0 V 10 0.4 0.8 1.2 1.6 2.0 2.4 A 2.8 V S D , S ource-to-Drain Voltage (V ) Fig 7. Typical Source-Drain Diode Forward Voltage T C = 25 °C T J = 15 0°C S ing le Pulse 1 1 A 10 V D S , Drain-to-Source Voltage (V) Fig 8. Maximum Safe Operating Area 100 IRLR/U3103 50 RD VDS L IM IT E D B Y P A C K A G E VGS I D , D ra in C u rre n t (A m p s) 40 D.U.T. RG + - VDD 30 4.5V Pulse Width ≤ 1 µs Duty Factor ≤ 0.1 % 20 Fig 10a. Switching Time Test Circuit 10 VDS 90% A 0 25 50 75 100 125 150 TC , Case Temperature (°C ) 10% VGS Fig 9. Maximum Drain Current Vs. Case Temperature td(on) tr t d(off) tf Fig 10b. Switching Time Waveforms Therm al R esp onse (Z thJC ) 10 1 D = 0.50 0 .2 0 0 .1 0 PD M 0 .0 5 0.1 t 0 .0 2 0 .0 1 t2 S IN G L E P U L S E (T HE RM A L R E S P O NS E ) 0.01 0.00001 1 N o te s : 1 . D u ty fa c to r D = t 1 / t 2 2. P e a k T J = P DM x Z t h J C + T C 0.0001 0.001 0.01 0.1 t 1 , Rectan gular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case A 1 IRLR/U3103 D.U.T. RG + V - DD IAS 4.5 V tp 0.01Ω Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS E A S , S in g le P u ls e A va la n c h e E n e rg y (m J) 500 L VDS TO P B OTTO M 400 300 200 100 VD D = 1 5V 0 25 tp A 50 75 100 125 Starting T J , Junction Temperature (°C) VDD Fig 12c. Maximum Avalanche Energy Vs. Drain Current VDS IAS Fig 12b. Unclamped Inductive Waveforms Current Regulator Same Type as D.U.T. 50KΩ QG 12V .2µF .3µF 4.5 V QGS D.U.T. QGD + V - DS VGS VG 3mA IG Charge Fig 13a. Basic Gate Charge Waveform ID 15 A 2 1A 34 A ID Current Sampling Resistors Fig 13b. Gate Charge Test Circuit 150 IRLR/U3103 Peak Diode Recovery dv/dt Test Circuit + Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer + - - • • • • + + dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test Driver Gate Drive Period P.W. D= - VDD P.W. Period VGS=10V D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent Ripple ≤ 5% * VGS = 5V for Logic Level Devices Fig 13. For N-Channel HEXFETS ISD * IRLR/U3103 Package Outline TO-252AA Outline Dimensions are shown in millimeters (inches) 2.38 (.094) 2.19 (.086) 6.73 (.265) 6.35 (.250) 1.14 (.045) 0.89 (.035) -A1.27 (.050) 0.88 (.035) 5.46 (.215) 5.21 (.205) 0.58 (.023) 0.46 (.018) 4 6.45 (.245) 5.68 (.224) 6.22 (.245) 5.97 (.235) 1.02 (.040) 1.64 (.025) 10.42 (.410) 9.40 (.370) 1 2 LEA D AS SIG NME NT S 1 - G AT E 3 0.51 (.020) MIN. -B 1.52 (.060) 1.15 (.045) 3X 1.14 (.045) 2X 0.76 (.030) 0.89 (.035) 0.64 (.025) 0.25 ( .010) 2.28 (.090) 4.57 (.180) 2 - DRA IN 3 - S OUR CE 4 - DRA IN 0.58 (.023) 0.46 (.018) M A M B NOT ES: 1 DIME NSIO NING & T OLE RANCING P ER A NSI Y 14.5M, 1982. 2 CO NTRO LLING DIMENS ION : INCH. 3 CO NFO RMS T O JEDE C O UTLINE TO -252AA . 4 DIME NSIO NS S HO W N ARE BEF O RE SO LD ER DIP , SO LDER DIP MA X. +0.16 (.006). Part Marking Information TO-252AA (D-PARK) E XA M PL E : T HIS IS AN IR F R1 20 W IT H AS S EM B LY L OT C OD E 9 U 1P INT ER N AT IO N A L R E CT IF IE R L O GO A IR F R 1 20 9U AS S EM B LY L OT CO D E FIR ST P O RT IO N OF P A RT N U MB E R 1P S E CO N D P O RT ION O F PA R T NU M BE R IRLR/U3103 Package Outline TO-251AA Outline Dimensions are shown in millimeters (inches) 6.73 (.265) 6.35 (.250) 2.38 (.094) 2.19 (.086) -A- 0.58 (.023) 0.46 (.018) 1.27 ( .050) 0.88 ( .035) 5.46 (.215) 5.21 (.205) LEAD AS SIG NMENT S 4 1 - G AT E 2 - DRA IN 6.45 (.245) 5.68 (.224) 3 - S OURCE 4 - DRA IN 6.22 ( .245) 5.97 ( .235) 1.52 ( .060) 1.15 ( .045) 1 2 3 -B - NOT ES : 1 DIME NSIO NING & T OLE RANCING P ER A NSI Y14.5M, 1982. 2.28 (.090) 1.91 (.075) 2 CO NTRO LLIN G DIMENS ION : INCH. 3 CO NFO RMS TO J EDE C O UT LINE TO -252AA . 9.65 (.380) 8.89 (.350) 4 DIME NSIO NS SHOW N A RE BEF O RE SO LDER DIP , SO LDER DIP MA X. +0.16 (.006). 3X 1.14 (.045) 0.76 (.030) 2.28 (.090) 3X 1.14 (.045) 0.89 (.035) 0.89 (.035) 0.64 (.025) 0.25 (.010) 2X M A M B 0.58 (.023) 0.46 (.018) Part Marking Information TO-251AA (I-PARK) E XA M P LE : TH IS IS A N IR FU 1 20 W ITH A S SE M B LY L O T C OD E 9 U1 P INT E RN AT ION A L R EC T IFIER LO GO IRF U 12 0 9U AS S E MB L Y L OT C OD E F IRS T P O RT IO N O F P A RT N U M BE R 1P S EC O ND PO R TIO N OF P AR T N U MB E R IRLR/U3103 Tape & Reel Information TO-252AA Dimensions are shown in millimeters (inches) TR TRR 1 6 .3 ( .6 4 1 ) 1 5 .7 ( .6 1 9 ) 1 2.1 ( .47 6 ) 1 1.9 ( .46 9 ) F E E D D IR E C T IO N TR L 16 .3 ( .6 4 1 ) 15 .7 ( .6 1 9 ) 8 .1 ( .3 18 ) 7 .9 ( .3 12 ) FE E D D IR E C TIO N N O TE S : 1 . C O N T R O LL IN G D IM E N S IO N : M ILL IM E TE R . 2 . A L L D IM E N S IO N S A R E S H O W N IN M IL LIM E T E R S ( IN C H E S ). 3 . O U T L IN E C O N F O R M S T O E IA -4 8 1 & E IA -5 41 . 1 3 IN C H 16 m m NO T ES : 1 . O U T LIN E C O N F O R M S T O E IA -4 81 . WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331 EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020 IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111 IR FAR EAST: K&H Bldg., 2F, 3-30-4 Nishi-Ikeburo 3-Chome, Toshima-Ki, Tokyo Japan 171 Tel: 81 3 3983 0086 IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371 http://www.irf.com/ Data and specifications subject to change without notice. 8/96