BSO094N03S OptiMOS®2 Power-Transistor Product Summary Features • Fast switching MOSFET for SMPS • Optimized technology for notebook DC/DC V DS 30 V R DS(on),max 9.1 mΩ ID 13 A 1 • Qualified according to JEDEC for target applications • N-channel • Logic level P-DSO-8 • Excellent gate charge x R DS(on) product (FOM) • Very low on-resistance R DS(on) • Avalanche rated • dv /dt rated Type Package Ordering Code Marking BSO094N03S P-DSO-8 Q67042-S4209 94N3S Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Continuous drain current Value Symbol Conditions ID Unit 10 secs steady state T A=25 °C2) 13 10 T A=70 °C2) 10 8.3 A Pulsed drain current I D,pulse T A=25 °C3) 52 Avalanche energy, single pulse E AS I D=13 A, R GS=25 Ω 86 mJ Reverse diode dv /dt dv /dt I D=13 A, V DS=20 V, di /dt =200 A/µs, T j,max=150 °C 6 kV/µs Gate source voltage V GS Power dissipation P tot Operating and storage temperature T j, T stg ±20 T A=25 °C2) 1.56 -55 ... 150 W °C 55/150/56 IEC climatic category; DIN IEC 68-1 Rev. 1.11 2.5 V page 1 2004-02-09 BSO094N03S Parameter Values Symbol Conditions Unit min. typ. max. - - 35 minimal footprint, t p≤10 s - - 110 minimal footprint, steady state - - 150 6 cm2 cooling area2), t p≤10 s - - 50 6 cm2 cooling area2), steady state - - 80 Thermal characteristics Thermal resistance, junction - soldering point R thJS Thermal resistance, junction - ambient R thJA K/W Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0 V, I D=1 mA 30 - - Gate threshold voltage V GS(th) V DS=V GS, I D=30 µA 1.2 1.6 2 Zero gate voltage drain current I DSS V DS=30 V, V GS=0 V, T j=25 °C - 0.1 1 V DS=30 V, V GS=0 V, T j=125 °C - 10 100 V µA Gate-source leakage current I GSS V GS=20 V, V DS=0 V - 10 100 nA Drain-source on-state resistance R DS(on) V GS=4.5 V, I D=11 A - 10.3 12.9 mΩ V GS=10 V, I D=13 A - 7.6 9.1 - 1.1 - Ω 19 37 - S Gate resistance RG Transconductance g fs 1) |V DS|>2|I D|R DS(on)max, I D=13 A J-STD20 and JESD22 2) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. 3) See figure 3 Rev. 1.11 page 2 2004-02-09 BSO094N03S Parameter Values Symbol Conditions Unit min. typ. max. - 1730 2300 - 620 820 Dynamic characteristics Input capacitance C iss Output capacitance C oss Reverse transfer capacitance C rss - 81 120 Turn-on delay time t d(on) - 5.4 8 Rise time tr - 4.4 6.6 Turn-off delay time t d(off) - 22 33 Fall time tf - 3.2 4.8 Gate to source charge Q gs - 4.8 6.4 Gate charge at threshold Q g(th) - 2.8 3.7 Gate to drain charge Q gd - 3.3 4.9 Switching charge Q sw - 5.3 7.6 Gate charge total Qg - 13 18 Gate plateau voltage V plateau - 2.8 - Gate charge total, sync. FET Q g(sync) V DS=0.1 V, V GS=0 to 5 V - 12 16 Output charge Q oss V DD=15 V, V GS=0 V - 15 20 - - 2.5 - - 52 V GS=0 V, V DS=15 V, f =1 MHz V DD=15 V, V GS=10 V, I D=6.5 A, R G=2.7 Ω pF ns Gate Charge Characteristics4) V DD=15 V, I D=6.5 A, V GS=0 to 5 V nC V nC Reverse Diode Diode continous forward current IS Diode pulse current I S,pulse Diode forward voltage V SD V GS=0 V, I F=2.5 A, T j=25 °C - 0.74 1 V Reverse recovery charge Q rr V R=13 V, I F=I S, di F/dt =400 A/µs - - 10 nC 4) T A=25 °C A See figure 16 for gate charge parameter definition Rev. 1.11 page 3 2004-02-09 BSO094N03S 1 Power dissipation 2 Drain current P tot=f(T A); t p≤10 s I D=f(T A); V GS≥10 V; t p≤10 s 3 16 2.5 12 I D [A] P tot [W] 2 1.5 8 1 4 0.5 0 0 0 40 80 120 160 0 40 80 T A [°C] 160 T A [°C] 3 Safe operation area 4 Max. transient thermal impedance 1) I D=f(V DS); T A=25 °C ; D =0 Z thJS=f(t p) parameter: t p parameter: D =t p/T 102 120 102 100 100 10 µs 0.5 100 µs 101 10 I D [A] limited by on-state resistance 100 0.2 10 0.1 1 ms Z thJS [K/W] 101 1 10 ms 0.05 100 0.02 1 0.01 10 s 10-1 0.1 10-1 0.1 10-2 0.01 single pulse DC 10-2 0.01 0.1 1 -1 10 Rev. 1.11 10 0 10 100 1 V DS [V] 10 2 10 page 4 0.00001 0.0001 0.001 0.01 0.1 1 10 10-5 10-4 10-3 10-2 10-1 100 101 t p [s] 2004-02-09 BSO094N03S 5 Typ. output characteristics 6 Typ. drain-source on resistance I D=f(V DS); T j=25 °C R DS(on)=f(I D); T j=25 °C parameter: V GS parameter: V GS 30 25 10 V 4.5 V 25 3.4 V 20 3.3 V 3.6 V 20 15 R DS(on) [mΩ] I D [A] 3.2 V 3.1 V 3V 15 3.8 V 4V 4.2 V 4.5 V 5V 10 10 10 V 5 2.8 V 5 2.6 V 0 0 0 1 2 3 0 10 V DS [V] 20 30 20 30 I D [A] 7 Typ. transfer characteristics 8 Typ. forward transconductance I D=f(V GS); |V DS|>2|I D|R DS(on)max g fs=f(I D); T j=25 °C parameter: T j 50 60 50 40 40 I D [A] g fs [S] 30 30 20 20 10 125 °C 10 25 °C 0 0 0 1 2 3 4 10 I D [A] V GS [V] Rev. 1.11 0 page 5 2004-02-09 BSO094N03S 9 Drain-source on-state resistance 10 Typ. gate threshold voltage R DS(on)=f(T j); I D=13 A; V GS=10 V V GS(th)=f(T j); V GS=V DS parameter: I D 16 2.5 2 12 300 µA 8 V GS(th) [V] R DS(on) [mΩ] 98 % typ 1.5 30 µA 1 4 0.5 0 0 -60 -20 20 60 100 140 180 -60 -20 20 60 100 140 180 T j [°C] T j [°C] 11 Typ. capacitances 12 Forward characteristics of reverse diode C =f(V DS); V GS=0 V; f =1 MHz I F=f(V SD) parameter: T j 104 102 10000 100 150 °C 25 °C 150 °C, 98 % Ciss 103 1000 102 100 101 10 101 10 100 1 10-1 0.1 I F [A] C [pF] Coss 0 Crss 10 20 30 V DS [V] Rev. 1.11 25 °C, 98% 0 0.2 0.4 0.6 0.8 1 1.2 V SD [V] page 6 2004-02-09 BSO094N03S 13 Avalanche characteristics 14 Typ. gate charge I AS=f(t AV); R GS=25 Ω V GS=f(Q gate); I D=6.5 A pulsed parameter: T j(start) parameter: V DD 100 12 15 V 10 6V 24 V 8 V GS [V] I AV [A] 25 °C 10 100 °C 125 °C 6 4 2 1 0 1 10 100 1000 0 5 10 15 20 25 30 Q gate [nC] t AV [µs] 15 Drain-source breakdown voltage 16 Gate charge waveforms V BR(DSS)=f(T j); I D=1 mA 36 V GS 34 Qg 32 V BR(DSS) [V] 30 28 V g s(th) 26 24 Q g (th) 22 Q sw Q gs 20 -60 -20 20 60 100 140 Q gate Q gd 180 T j [°C] Rev. 1.11 page 7 2004-02-09 BSO094N03S Package Outline P-DSO-8: Outline Footprint Packaging Tape Tube Dimensions in mm Rev. 1.11 page 8 2004-02-09 BSO094N03S Published by Infineon Technologies AG Bereich Kommunikation St.-Martin-Straße 53 D-81541 München © Infineon Technologies AG 1999 All Rights Reserved. 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Infineon Technologies' components may only be used in life-support devices or systems with the expressed written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 1.11 page 9 2004-02-09