PD -97140
IRFP4668PbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
G
D
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
S
VDSS
200V
RDS(on) typ.
8.0m:
max. 9.7m:
130A
ID
D
G
D
S
TO-247AC
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
Parameter
Max.
Continuous Drain Current, VGS @ 10V
Units
130
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V
92
IDM
Pulsed Drain Current c
520
PD @TC = 25°C
Maximum Power Dissipation
520
W
Linear Derating Factor
3.5
VGS
Gate-to-Source Voltage
± 30
W/°C
V
dv/dt
TJ
Peak Diode Recovery e
57
Operating Junction and
-55 to + 175
TSTG
Storage Temperature Range
A
V/ns
°C
300
Soldering Temperature, for 10 seconds
(1.6mm from case)
10lbxin (1.1Nxm)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
EAS (Thermally limited)
Single Pulse Avalanche Energy d
IAR
Avalanche Current c
EAR
Repetitive Avalanche Energy f
mJ
760
See Fig. 14, 15, 22a, 22b,
A
mJ
Thermal Resistance
Symbol
Parameter
Typ.
Max.
RθJC
Junction-to-Case j
–––
0.29
RθCS
Case-to-Sink, Flat Greased Surface
0.24
–––
RθJA
Junction-to-Ambient ij
–––
40
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Units
°C/W
1
9/8/08
IRFP4668PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
V(BR)DSS
ΔV(BR)DSS/ΔTJ
RDS(on)
VGS(th)
IDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
RG
Min. Typ. Max. Units
200
–––
–––
3.0
–––
–––
–––
–––
–––
–––
0.21
8.0
–––
–––
–––
–––
–––
1.0
–––
–––
9.7
5.0
20
250
100
-100
–––
Conditions
V VGS = 0V, ID = 250μA
V/°C Reference to 25°C, ID = 5mAc
mΩ VGS = 10V, ID = 81A f
V VDS = VGS, ID = 250μA
μA VDS = 200V, VGS = 0V
VDS = 200V, VGS = 0V, TJ = 125°C
nA VGS = 20V
VGS = -20V
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
Qsync
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)
Parameter
Min. Typ. Max. Units
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
150 ––– –––
––– 161 241
–––
54
–––
–––
52
–––
––– 109 –––
Turn-On Delay Time
–––
41
–––
Rise Time
––– 105 –––
Turn-Off Delay Time
–––
64
–––
Fall Time
–––
74
–––
Input Capacitance
––– 10720 –––
Output Capacitance
––– 810 –––
Reverse Transfer Capacitance
––– 160 –––
Effective Output Capacitance (Energy Related)h ––– 630 –––
––– 790 –––
Effective Output Capacitance (Time Related)g
S
nC
ns
pF
Conditions
VDS = 50V, ID = 81A
ID = 81A
VDS = 100V
VGS = 10V f
ID = 81A, VDS =0V, VGS = 10V
VDD = 130V
ID = 81A
RG = 2.7Ω
VGS = 10V f
VGS = 0V
VDS = 50V
ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 160V h
VGS = 0V, VDS = 0V to 160V g
Diode Characteristics
Symbol
Parameter
IS
Continuous Source Current
ISM
(Body Diode)
Pulsed Source Current
VSD
trr
(Body Diode)c
Diode Forward Voltage
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
Notes:
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.23mH
RG = 25Ω, IAS = 81A, VGS =10V. Part not recommended for
use above this value.
ISD ≤ 81A, di/dt ≤ 520A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400μs; duty cycle ≤ 2%.
2
Min. Typ. Max. Units
–––
–––
–––
–––
130
520
A
Conditions
MOSFET symbol
showing the
integral reverse
D
G
p-n junction diode.
TJ = 25°C, IS = 81A, VGS = 0V f
TJ = 25°C
VR = 100V,
IF = 81A
TJ = 125°C
di/dt = 100A/μs f
TJ = 25°C
––– –––
1.3
V
––– 130 –––
ns
––– 155 –––
––– 633 –––
nC
TJ = 125°C
––– 944 –––
–––
8.7
–––
A TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
S
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
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IRFP4668PbF
1000
1000
100
BOTTOM
10
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
≤60μs PULSE WIDTH
1
Tj = 25°C
0.1
100
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
4.5V
10
4.5V
4.5V
≤60μs PULSE WIDTH
Tj = 175°C
0.01
1
0.1
1
10
100
1000
0.1
100
1000
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
3.5
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current(Α)
10
VDS, Drain-to-Source Voltage (V)
1000
100
TJ = 175°C
10
TJ = 25°C
1
VDS = 50V
≤ 60μs PULSE WIDTH
0.1
3.0
4.0
5.0
6.0
7.0
8.0
2.5
2.0
1.5
1.0
0.5
0.0
9.0
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
16000
VGS, Gate-to-Source Voltage (V)
Coss = Cds + Cgd
Ciss
8000
4000
Coss
Crss
0
1
ID= 81A
VDS = 160V
VDS = 100V
12
VDS = 40V
8
4
0
10
100
VDS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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Fig 4. Normalized On-Resistance vs. Temperature
16
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
12000
ID = 81A
VGS = 10V
3.0
VGS, Gate-to-Source Voltage (V)
C, Capacitance (pF)
1
VDS, Drain-to-Source Voltage (V)
0
40
80
120
160
200
QG Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFP4668PbF
10000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
TJ = 175°C
100
TJ = 25°C
10
1
1000
VGS = 0V
0.5
1.0
100μsec
100
10msec
10
1msec
1
0.1
1.5
ID , Drain Current (A)
120
100
80
60
40
20
0
100
125
150
175
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
140
75
1
1000
Id = 5mA
240
230
220
210
200
190
-60 -40 -20 0 20 40 60 80 100120140160180
TJ , Temperature ( °C )
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Drain-to-Source Breakdown Voltage
2500
EAS, Single Pulse Avalanche Energy (mJ)
14
12
10
Energy (μJ)
100
250
TC , CaseTemperature (°C)
8
6
4
2
ID
18A
24A
BOTTOM 81A
TOP
2000
1500
1000
500
0
0
0
40
80
120
160
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
10
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
50
DC
VDS , Drain-toSource Voltage (V)
VSD , Source-to-Drain Voltage (V)
25
Tc = 25°C
Tj = 175°C
Single Pulse
0.1
0.1
0.0
OPERATION IN THIS AREA
LIMITED BY R DS (on)
200
25
50
75
100
125
150
175
Starting TJ, Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
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IRFP4668PbF
Thermal Response ( Z thJC )
1
D = 0.50
0.1
0.20
0.10
0.05
0.02
0.01
τJ
0.01
R1
R1
τJ
τ1
R2
R2
R3
R3
Ri (°C/W)
τC
τ1
τ2
τ2
Ci= τi/Ri
Ci= τi/Ri
τ3
τ3
τ
τι (sec)
0.063359 0.000278
0.110878 0.005836
0.114838 0.053606
0.001
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
Avalanche Current (A)
Duty Cycle = Single Pulse
100
0.01
0.05
10
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
800
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 81A
600
400
200
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFP4668PbF
70
ID = 1.0A
60
ID = 1.0mA
5.0
ID = 250μA
50
4.0
IRRM - (A)
VGS(th) Gate threshold Voltage (V)
6.0
3.0
40
30
2.0
1.0
0.0
20
IF = 52A
VR = 100V
10
TJ = 125°C
TJ = 25°C
0
-75
-50 -25
0
25
50
75
100 125 150 175
100 200 300 400 500 600 700 800 900 1000
TJ , Temperature ( °C )
dif / dt - (A / μs)
Fig. 17 - Typical Recovery Current vs. dif/dt
Fig 16. Threshold Voltage Vs. Temperature
5000
70
60
4000
QRR - (nC)
IRRM - (A)
50
40
30
20
IF = 81A
VR = 100V
10
TJ = 125°C
TJ = 25°C
0
3000
2000
IF = 52A
VR = 100V
1000
TJ = 125°C
TJ = 25°C
0
100 200 300 400 500 600 700 800 900 1000
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
dif / dt - (A / μs)
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
5000
QRR - (nC)
4000
3000
2000
1000
IF = 81A
VR = 100V
TJ = 125°C
TJ = 25°C
0
100 200 300 400 500 600 700 800 900 1000
dif / dt - (A / μs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFP4668PbF
Driver Gate Drive
D.U.T
-
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
DRIVER
L
VDS
tp
D.U.T
RG
+
V
- DD
IAS
VGS
20V
A
0.01Ω
tp
I AS
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
Fig 22b. Unclamped Inductive Waveforms
VDS
90%
VGS
D.U.T.
RG
+
- VDD
V10V
GS
10%
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
td(on)
Fig 23a. Switching Time Test Circuit
tr
t d(off)
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
12V
tf
.2μF
.3μF
D.U.T.
+
V
- DS
Vgs(th)
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
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Qgs1 Qgs2
Qgd
Qgodr
Fig 24b. Gate Charge Waveform
7
IRFP4668PbF
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
TO-247AC Part Marking Information
EXAMPLE: THIS IS AN IRFPE30
WIT H AS S EMBLY
LOT CODE 5657
AS S EMBLED ON WW 35, 2001
IN T HE AS S EMBLY LINE "H"
Note: "P" in ass embly line pos ition
indicates "Lead-Free"
INTERNATIONAL
RECT IFIER
LOGO
PART NUMBER
IRFPE30
56
135H
57
AS S EMBLY
LOT CODE
DAT E CODE
YEAR 1 = 2001
WEEK 35
LINE H
TO-247AC packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
8
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 09/08
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