Data Sheet No.PD94720 IR3651SPbF HIGH VOLTAGE SYNCHRONOUS PWM BUCK CONTROLLER Features Description • • • • • • • The IR3651 is a high voltage PWM controller • • High Voltage Operating up to 75V Programmable Switching Frequency up to 400kHz 1A Output Drive Capability Precision Reference Voltage (1.25V) Programmable Soft-Start Programmable Over Current Protection Hiccup Current Limit Using MOSFET RDS(on) sensing External Frequency Synchronization 14-pin SOIC Package designed for high performance synchronous Buck DC/DC applications. The IR3651 drives a pair of external N-MOSFETs using a programmable switching frequency up to 400kHz allows flexibility to tune the operation of the IC to meet system level requirements, and synchronization allows the simplification of system level filter design. The output voltage can be precisely regulated using the internal 1.25V reference voltage for low Applications • • • • • voltage applications. Protection such as under 48V non-isolated DC to DC Converter Embedded Telecom Systems Networking and Computing Voltage Regulator Distributed Point of Load Power Architectures General high voltage DC/DC Converters voltage lockout and hiccup current limit are provided to give required system level security in the event of fault conditions. Vin: 12V-75V Vaux=12V C3 C1 C4 C2 DRVcc Vb Vcc R5 Vout L1 SYNC Rt Q1 HDrv Vs IR3651S OCset SS/SD ROCset Q2 LDrv C6 C5 C8 PGnd Gnd Comp R2 R4 C10 Typical application Circuit ORDERING INFORMATION PKG DESIG S S PACKAGE DESCRIPTION IR3651SPBF IR3651STRPBF R3 C9 Fb C7 10/11/2006 R1 PIN PARTS PARTS COUNT PER TUBE PER REEL 14 55 ------14 -------2500 T&R ORIANTAION Fig A IR3651SPbF ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND) • Vcc, DRVcc Supply Voltage ..................................… -0.3V to 20V • Vs Supply Voltage …………………………………….. -0.3V to 150V • Vb Supply Voltage …………………………………….. -0.3V to Vs+20V • OCset …………….…………………………………….. 10mA • Storage Temperature Range ..................................... -65°C To 150°C • Operating Junction Temperature Range ................... -40°C To 150°C • ESD Classification …………………………………..… JEDEC, JESD22-A114 (1K) • Moisture Sensitivity Level ……………………………. JEDEC Level 3 @ 260oC CAUTION: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications are not implied. Package Information 14-Pin SOIC NB (S) Fb 1 Comp 2 14 Rt 13 Gnd SS/SD 3 12 OCset SYNC 4 11 Vcc PGnd 5 10 Vs Ldrv 6 DRVcc 7 9 HDrv 8 Vb ΘJA = 88.2o C/W ΘJC = 37o C/W 10/11/2006 2 IR3651SPbF Block Diagram Vcc 11 3V Bias Generator 1.25V 0.25V Gnd 13 POR 4.17V SYNC 4 Rt Rt 14 Vcc Oscillator 8 Vb LOW VOLTAGE LEVEL SHIFT S Ct Q POR R Reset Dom HIGH VOLTAGE LEVEL SHIFT CIRCUIT UV DETECT UV Q S R 9 HDrv 3V 20uA 10 Vs 64uA Max SS/SD 3 3uA 7 DRVcc OCP UV DETECT Error Comp 1.25V Fb 1 25K 6 LDrv Vcc Error Amp LOW VOLTAGE LEVEL SHIFT 25K Comp 2 DELAY 5 PGND OCP R 0.3V Q 12 OCset PBias S SS 10uA POR Fig. 1: Simplified block diagram of the IR3651 10/11/2006 3 IR3651SPbF Pin Description Pin Name 1 Fb 2 Comp 3 SS/SD 4 SYNC 5 PGnd 6 LDrv 7 DRVcc 8 Vb 9 HDrv 10 Vs 11 Vcc 12 OCSet 13 Gnd 14 Rt 10/11/2006 Description Inverting input to the error amplifier. This pin is connected directly to the output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier. Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to ground to provide loop compensation. Soft start / shutdown. This pin provides user programmable soft-start function. Connect an external capacitor from this pin to ground to set the start up time of the output voltage. The converter can be shutdown by pulling this pin below 0.3V. The internal oscillator can be synchronized to an external clock via this pin. Power Ground. This pin serves as a separate ground for the MOSFET driver and should be connected to the system’s power ground plane. Output driver for low side MOSFET. This pin provides biasing for the internal low side driver. A minimum of 0.1uF, high frequency capacitor must be connected from this pin to power ground. This pin powers the high side driver and must be connected to a voltage higher than bus voltage. A minimum of 0.1uF, high frequency capacitor must be connected from this pin to switch node. Output driver for high side MOSFET Switch node. Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin is return path for the upper gate driver. This pin provides power for the internal blocks of the IC. A minimum of 0.1uF, high frequency capacitor must be connected from this pin to ground. Current limit set point. A resistor from this pin to drain of low side MOSFET will set the current limit threshold. Signal ground for internal reference and control circuitry. Connecting a resistor from this pin to ground sets the oscillator frequency. 4 IR3651SPbF Recommended Operating Conditions Symbol Definition Min Vbus Vcc DRVcc Vb to Vs Fs Tj Converting Voltage Supply Voltage Supply Voltage Supply Voltage Operating Frequency Junction Temperature Max 12 4.5 10 10 100 -40 Units 75 13.2 16 16 400 125 V V V V kHz o C Electrical Specifications Unless otherwise specified, these specifications apply over Vcc=5V; DRVcc=Vb=12V, 0oC<Tj< 125oC Parameter SYM Test Condition Min TYP MAX Unit s Reference Voltage Feedback Voltage VFB Accuracy Fb Voltage Line Regulation 1.25 o o 0 C<Tj<125 C o o -40 C<Tj<125 C, Note1 -1.5 -3 V +1.5 +1.5 % % 2.0 mV LREG 5V<Vcc<12V VCC Supply Current (Stat) ICC(Static) SS=0V, No Switching 6 7 mA VCC Supply Current (Dyn) ICC(Dynamic) Fs=200kHz, CLOAD=1.5nF 6 7 mA 0.3 0.5 mA 4 5 mA SS=0V, No Switching 0.3 0.5 mA Fs=200kHz, CLOAD=1.5nF 4.5 5.5 mA 4.17 4.35 4.1 0.3 9.7 8.9 0.9 9.7 8.9 0.9 V V V V V V V V V 230 460 kHz Supply Current DRVcc Supply Current (Stat) IC(Static) DRVcc Supply Current (Dyn) IC(Dynamic) Vb Supply Current (Stat) Ib(Static) Vb Supply Current (Dyn) Ib(Dynamic) SS=0V, No Switching Fs=200kHz, CLOAD=1.5nF Under Voltage Lockout VCC-Start-Threshold VCC-Stop-Threshold VCC-Hysteresis DRVcc-Start-Threshold DRVcc-Stop-Threshold DRVCc-Hysteresis Vb-Start-Threshold Vb-Stop-Threshold Vb-Hysteresis VCC_UVLO(R) VCC_UVLO(F) DRcc_UVLO(R) DRVcc_UVLO(F) Vb_UVLO(R) Vb_UVLO(F) Supply ramping up Supply ramping down Supply ramping up and down Supply ramping up Supply ramping down Supply ramping up and down Supply ramping up Supply ramping down Supply ramping up and down 4.0 3.75 0.15 8.3 7.5 0.6 8.3 7.5 0.6 Rt=120K Rt=51K 170 340 0.25 9 8.2 9 8.2 Oscillator Frequency FS Ramp Amplitude Vramp Note2 Min Duty Cycle Dmin Fb=2V Min Pulse Width Dmin(ctrl) Max Duty Cycle Dmax Sync Frequency Range Sync Pulse Duratin Sync(Fs) Fs=200kHz, Note2 Fs=200kHz, Fb=1.2V Fs=400kHz, Fb=1.2V 20% above free running freq 200 400 1.25 V 0 % 200 ns 80 70 % 480 kHz Sync(puls) 200 ns Sync high Level Threshold Sync(H) 2 V Sync Low Level Threshold Sync(L) 10/11/2006 0.8 V 5 IR3651SPbF Parameter SYM Test Condition Min TYP MAX Units -0.1 -0.4 µA Error Amplifier Input Bias Current IFB SS=3V, Fb=1V Source/Sink Current I(source/Sink) 50 85 120 µA Transconductance gm 1500 2400 3000 µmho 15 20 25 µA 0.25 V 12.5 5 µA µA % Soft Start/SD Soft Start Current ISS Shutdown Threshold SD Output SS=0V Over Current Protection OCSET Current Hiccup Current Hiccup Duty Cycle IOCSET IHiccup Hiccup(duty) 7.5 Note2 IHiccup / ISS , Note2 10 3 Output Drivers LO, Drive Rise Time Tr(Lo) CL=1.5nF See Fig 2, Note2 CL=1.5nF, See Fig 2, Note2 10 20 ns HI Drive Rise Time Tr(Hi) 10 20 ns LO Drive Fall Time Tf(Lo) CL=1.5nF See Fig 2,Note2 10 20 ns HI Drive Fall Time Tf(Hi) 10 20 ns Dead Band Time Tdead CL=1.5nF, See Fig 2,Note2 See Fig 2 45 100 ns Upper Driver Source Current Upper Driver Sink Curret Lower Driver Source Current Lower Driver Sink Current Iupper(source) HDrv short circuit current. PW<10us HDrv short circuit current. PW<10us LDrv short circuit current. PW<10us LDrv short circuit current. PW<10us Iupper(sink) Ilower(source) Ilower(sink) 30 pulsed 1.0 A pulsed 1.0 A pulsed 1.0 A pulsed 1.0 A Note1: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production. Note2: Guaranteed by Design but not tested in production. Tr Tf 9V High Side Driver (HDrv) 2V Tr Tf 9V Low Side Driver (LDrv) 2V Deadband H_to_L Deadband L_to_H Fig. 2: Definition of Rise/Fall time and Deadband Time 10/11/2006 6 IR3651SPbF TYPICAL OPERATING CHRACTERISTICS (-40oC TO +125oC) Vfb Transconductance 1.253 2.16 1.251 1.249 2.08 [mM HO ] [V] 1.247 1.245 1.243 1.241 1.239 1.237 2 1.92 1.84 1.76 1.68 1.235 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 1.6 130 -40 T emp [ C ] -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 60 70 80 90 100 110 120 130 90 100 110 120 130 Te m p [ C ] Icc(dynamic) Icc(static) 6.6 6.6 6.3 6.3 6 [mA] [mA] 6 5.7 5.4 5.7 5.4 5.1 5.1 4.8 4.8 4.5 -40 4.5 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 -40 130 -30 -20 -10 0 10 20 30 40 50 T e mp [ C] T emp [ C ] Ib(dynamic) Ic(dynamic) 4.95 4.06 4.9 3.98 3.9 4.8 [m A ] [mA] 4.85 4.75 3.82 3.74 4.7 3.66 4.65 3.58 4.6 -40 -30 -20 -10 3.5 0 10 20 30 40 50 60 70 -40 80 90 100 110 120 130 -30 -20 -10 0 10 20 30 40 50 60 70 80 T emp [ C ] Tem p [C] DRVcc_UVLO Vb_UVLO 9.2 9.2 9.15 9.15 9.1 9.1 [V] [V] 9.05 9 8.95 9.05 9 8.95 8.9 8.85 8.9 8.8 8.85 -40 -30 -20 -10 0 10 20 30 40 50 T emp [ C ] 10/11/2006 60 70 80 90 100 110 120 130 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Te m p [ C ] 7 IR3651SPbF TYPICAL OPERATING CHRACTERISTICS (-40oC TO +125oC) Vcc_UVLO Frequency RT=120K 4.3 201.5 4.28 4.26 201 [k H z ] 4.24 [V] 4.22 4.2 4.18 200.5 200 4.16 199.5 4.14 4.12 199 4.1 -40 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 100 110 120 130 130 T emp [ C] Te m p [ C ] Max DC @ 200KHz Dead time 100 91 90 90.5 80 90 [% ] [ns] 70 60 50 89.5 89 40 88.5 30 88 20 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 -40 130 -30 -20 -10 0 10 20 Iss 40 50 60 70 80 90 Iocset -15.000 -8.000 -16.000 -8.500 -17.000 -9.000 -18.000 -9.500 -19.000 -10.000 [uA] [uA] 30 Temp [ C] T emp [ C ] -20.000 -10.500 -21.000 -11.000 -22.000 -11.500 -23.000 -12.000 -24.000 -12.500 -25.000 -13.000 -50 -30 -10 10 30 50 Temp [C] 10/11/2006 70 90 110 130 -50 -30 -10 10 30 50 70 90 110 130 Temp [C] 8 IR3651SPbF Circuit Description THEORY OF OPERATION Introduction The timing of the IC is controlled by an internal oscillator circuit that can be externally programmed up to 400kHz. The IR3651 operates with a wide input voltage from 36V to 75V allowing an extended operating input voltage range. The current limit is programmable and uses onresistance of the low-side MOSFET, eliminating the need for an external current sense resistor. Under-Voltage Lockout The under-voltage lockout circuit monitors the Vcc supply and assures that the IC doesn’t starts until the Vcc reaches the set threshold. Lockout occurs if Vcc falls below 4.1V. Normal operation resumes once Vcc rises above the set value. Shutdown The output can be shutdown by pulling the softstart pin below 0.3V. This can be easily done by using an external small signal transistor. During shutdown both MOSFET drivers will be turned off. Normal operation will resume by cycling soft start pin. Error Amplifier The IR3651 is a voltage mode controller. The error amplifier is of transconductance type. The amplifier is capable of operating with Type III compensation control scheme using low ESR output capacitance. Switching Frequency vs. Rt 450 400 Switching Frequency (kHz) The IR3651 is a voltage mode PWM synchronous controller. The output voltage is set by feedback pin (Fb) and the internal reference voltage (1.25V). These are two inputs to error amplifier. The error signal between these two inputs is compared to a fixed frequency linear sawtooth ramp and generates fixed frequency pulses of variable duty-cycle (D) which drivers Nchannel external MOSFETs. 350 300 250 200 150 100 50 0 0 50 100 150 200 250 300 Rt (Kohm) Fig. 3: Switching Frequency vs. Rt Frequency Synchronization The IR3651 is capable of accepting an external digital synchronization signal. Synchronization will be enabled by the rising edge at an external clock. Switching frequency is set by external resistor (Rt). During synchronization, Rt is selected such that the free running frequency is 20% below the synchronization frequency. When unused, the sync pin will remain floating and is noise immune. Pre-Bias Startup IR3651 is able to start up into pre-charged output, which prevents oscillation and disturbances of the output voltage. The output starts in asynchronous fashion and keeps the synchronous MOSFET off until the first gate signal for control MOSFET is generated. Below figure shows a typical PreBias condition at start up. Depends on system configuration, specific amount of output capacitors may be required to prevent discharging the output voltage Volt Vo Pre-Bias Voltage (Output Voltage before startup) Operating Frequency Selection The switching frequency is determined by connecting an external resistor (Rt) to ground. Figure 3 provides a graph of oscillator frequency versus Rt. 10/11/2006 Time 9 IR3651SPbF Soft-Start The IR3651 has programmable soft-start to control the output voltage rise and limit the inrush current during start-up. To ensure correct start-up, the soft-start sequence initiates when Vcc rises above its threshold and generate the Power On Ready (POR) signal. The soft-start function operates by sourcing current to charge an external capacitor to about 3V. Initially, the soft-start function clamps the output of error amplifier by injecting a current (64uA) into the Fb pin and generates a voltage about 1.6V (64ux25K) across the negative input of error amplifier (see figure 4). The magnitude of the injected current is inversely proportional to the voltage at the soft-start pin. As the soft-start voltage ramps up, the injected current decreases linearly and so does the voltage at negative input of error amplifier. When the soft-start capacitor is around 1V, the voltage at the positive input of the error amplifier is approximately 1.25V. The output of error amplifier will start increasing and generating the first PWM signal. As the softstart capacitor voltage continues to go up, the current flowing into the Fb pin will keep decreasing. The feedback voltage increases linearly as the soft start voltage ramps up. When soft-start voltage is around 2V the output voltage is reached the steady state and the injected current is zero. 3V 20uA SS/SD 64uA POR Comp 25K 1.25V Error Amp 25K Fb Fig. 4: Soft-Start circuit for IR3651 Output of UVLO POR 3V ≅2V ≅1V Soft-Start Voltage Current flowing into Fb pin 0V 64uA 0uA Voltage at negative input ≅1.6V of Error Amp Figure 5 shows the theoretical operational waveforms during soft-start. 1.25V The output voltage start-up time is the time period when soft-start capacitor voltage increases from 1V to 2V. 1.25V The start-up time will be dependent on the size of the external soft-start capacitor and can be estimate by: 20µA ∗ Tstart = 2V −1V Css Voltage at Fb pin 0V Fig. 5: Theoretical operation waveforms during soft-start For a given start-up time, the soft-start capacitor (nF) can be estimated as: CSS ≅ 20µA * Tstart (ms) 10/11/2006 --(1) 10 IR3651SPbF Over-Current Protection The over current protection is performed by sensing current through the RDS(on) of low side MOSFET. This method enhances the converter’s efficiency and reduce cost by eliminating a current sense resistor. As shown in figure 6, an external resistor (RSET) is connected between OCSet pin and the drain of low side MOSFET (Q2) which sets the current limit set point. The internal current source develops a voltage across RSET. When the low side MOSFET is turned on, the inductor current flows through the Q2 and results a voltage which is given by: VOCSet = (IOCSet ∗ ROCSet ) − (RDS(on) ∗ IL ) 28uA OCP 20uA SS1 / SD 20 3uA Fig. 7: 3uA current source for discharging soft-start capacitor during hiccup The OCP circuit starts sampling current approximately 200ns before the low gate drive turns off. The OCSet pin is internally clamped during deadtime to prevent false trigging, figure 8 shows the OCSet pin during one switching cycle. --(2 ) IOCSET Q1 IR3651 L1 OCSet RSET VOUT Q2 Hiccup Control Fig. 6: Connection of over current sensing resistor The critical inductor current can be calculated by setting: VOCSet = (IOCSet ∗ ROCSet ) − (RDS(on) ∗ IL ) = 0 ISET = IL(critical) = ROCSet ∗ IOCSet RDS(on) ISET = IL(critical) = 1.5 * Io + --(3 ) ∆iL 2 An over current is detected if the OCSet pin goes below ground. This trips the OCP comparator and cycles the soft start function in hiccup mode. The hiccup is performed by charging and discharging the soft-start capacitor in certain slope rate. As shown in figure 7 a 3uA current source is used to discharge the soft-start capacitor. Fig. 8: OCset pin during normal condition Ch1: Inductor point, Ch2:Ldrv, Ch3:OCSet The value of RSET should be checked in an actual circuit to ensure that the over current protection circuit activates as expected. The IR3651 current limit is designed primarily as disaster preventing, "no blow up" circuit, and doesn't operate as a precision current regulator. The OCP comparator resets after every soft start cycles, the converter stays in this mode until the overload or short circuit is removed. The converter will automatically recover. 10/11/2006 11 IR3651SPbF Application Information Soft-Start Programming Output Voltage Programming The soft-start timing can be programmed by selecting the soft-start capacitance value. The start-up time of the converter can be calculated by using: Output voltage is programmed by reference voltage and external voltage divider. The Fb pin is the inverting input of the error amplifier, which is internally referenced to 1.25V. The divider is ratioed to provide 1.25V at the Fb pin when the output is at its desired value. The output voltage is defined by using the following equation: When an external resistor divider is connected to the output as shown in figure 9. ⎛ R ⎞ Vo = Vref ∗ ⎜⎜1 + 8 ⎟⎟ R9 ⎠ ⎝ CSS ≅ 20µA * Tstart --(1) Where Tstart is the desired start-up time (ms) For a start-up time of 5ms, the soft-start capacitor will be 0.1uF. Choose a ceramic capacitor at 0.1uF. --( 4 ) Equation (4) can be rewritten as: ⎛ Vref R9 = R8 ∗ ⎜⎜ ⎝ V O−Vref ⎞ ⎟⎟ ⎠ --( 5 ) For the calculated values of R8 and R9 see feedback compensation section. VOUT IR3651 R8 Fb R9 Fig. 9: Typical application of the IR3651 for programming the output voltage 10/11/2006 12 IR3651SPbF Input Capacitor Selection The input filter capacitor should be selected based on how much ripple the supply can tolerate on the DC input line. The ripple current generated during the on time of upper MOSFET should be provided by input capacitor. The RMS value of this ripple is expressed by: IRMS = Io ∗ D ∗ (1 − D ) --(7 ) D= Vo Vin Where: D is the Duty Cycle Output Capacitor Selection The voltage ripple and transient requirements determine the output capacitors types and values. The criteria is normally based on the value of the Effective Series Resistance (ESR). However the actual capacitance value and the Equivalent Series Inductance (ESL) are other contributing components, these components can be described as: ∆Vo = ∆Vo(ESR) + ∆Vo(ESL) + ∆Vo(C ) IRMS is the RMS value of the input capacitor current. Io is the output current. For applications with input supplies above 30V, choice of input capacitor type is limited to ceramics or aluminum electrolytics. Ceramic capacitors offer high peak current capabilities, they also feature low ESR and ESL at higher frequency which enhance better efficiency, however high voltage ceramic capacitors are available with only in low value capacitance. A combination of ceramic capacitors and electrolytic capacitors are recommended. ∆Vo(ESR) = ∆IL * ESR - -(9) ⎛Vin ⎞ ⎟ * ESL ⎝L⎠ ∆Vo(ESL) = ⎜ ∆Vo(C ) = ∆IL 8 * Co * Fs ∆Vo = Output voltage ripple ∆IL = Inductor ripple current Inductor Selection The inductor is selected based on output power, operating frequency and efficiency requirements. Low inductor value causes large ripple current, resulting in the smaller size, faster response to a load transient but poor efficiency and high output noise. Generally, the selection of inductor value can be reduced to desired maximum ripple current in the inductor ( ∆i ) . The optimum point is usually found between 20% and 50% ripple of the output current. For the buck converter, the inductor value for desired operating ripple current can be determined using the following relation: Vin − Vo = L ∗ L = (Vin − Vo ) ∗ Where: ∆i 1 ; ∆t = D ∗ Fs ∆t Vo Vin ∗ ∆i * Fs --(8 ) Vin = Maximum input voltage Since the output capacitor has major role in overall performance of converter and determines the result of transient response, selection of capacitor is critical. The IR3651 can perform well with all types of capacitors. As a rule the capacitor must have low enough ESR to meet output ripple and load transient requirements, yet have high enough ESR to satisfy stability requirements. The goal for this design is to meet the voltage ripple requirement in smallest possible capacitor size. Therefore ceramic capacitor is selected due to low ESR and small size. In the case of tantalum or low ESR electrolytic capacitors, the ESR dominates the output voltage ripple, equation (9) can be used to calculate the required ESR for the specific voltage ripple. Vo = Output Voltage ∆i = Inductor ripple current F s= Switching frequency ∆t = Turn on time D = Duty cycle 10/11/2006 13 IR3651SPbF Power MOSFET Selection The IR3651 uses two N-Channel MOSFETs. The selections criteria to meet power transfer requirements is based on maximum drain-source voltage (VDSS), gate-source drive voltage (Vgs), maximum output current, On-resistance RDS(on) and thermal management. The MOSFET must have a maximum operating voltage (VDSS) exceeding the maximum input voltage (Vin). The gate drive requirement is almost the same for both MOSFETs. Logic-level transistor can be used and caution should be taken with devices at very low Vgs to prevent undesired turn-on of the complementary MOSFET, which results in shootthrough current. The total power dissipation for MOSFETs includes conduction and switching losses. For the Buck converter the average inductor current is equal to the DC load current. The conduction loss is defined as: Pcond = (upper switch)= I ∗ Rds(on) ∗ D ∗ ϑ Pcond = (lower switch)= I ∗ Rds(on) ∗ (1 − D) ∗ϑ 2 load 2 load switching losses in synchronous Buck converter. The synchronous MOSFET turns on under zero voltage conditions, therefore, the turn on losses for synchronous MOSFET can be neglected. With a linear approximation, the total switching loss can be expressed as: Psw = Vds(off ) tr + tf * * Iload 2 T - -(10) Where: V ds(off) = Drain to source voltage at the off time tr = Rise time tf = Fall time T = Switching period Iload = Load current The switching time waveforms is shown in figure10. VDS 90% ϑ = Rds(on) temperature dependency The RDS(on) temperature dependency should be considered for the worst case operation. This is typically given in the MOSFET data sheet. Ensure that the conduction losses and switching losses do not exceed the package ratings or violate the overall thermal budget. 10% VGS td(ON) tr td(OFF) tf Fig. 10: switching time waveforms The switching loss is more difficult to calculate, even though the switching transition is well understood. The reason is the effect of the parasitic components and switching times during the switching procedures such as turn-on / turnoff delays and rise and fall times. The control MOSFET contributes to the majority of the 10/11/2006 14 IR3651SPbF Feedback Compensation The IR3651 is a voltage mode controller; the control loop is a single voltage feedback path including error amplifier and error comparator. To achieve fast transient response and accurate output regulation, a compensation circuit is necessary. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency and adequate phase margin (greater than 45o). The output LC filter introduces a double pole, – 40dB/decade gain slope above its corner resonant frequency, and a total phase lag of 180o (see figure 11). The resonant frequency of the LC filter expressed as follows: FLC = 1 2 ∗ π Lo ∗ Co The ESR zero of the output capacitor is expressed as follows: 1 FESR = - -(12) 2 ∗ π * ESR * Co VO R8 Fb E/A R9 Gain VREF CPOLE R3 Gain(dB) H(s) dB Frequency FZ Fig. 12: TypeII compensation network and its asymptotic gain plot The transfer function (Ve/Vo) is given by: ⎛ R9 ⎞ 1 + sR3C4 ⎟⎟ * H(s) = ⎜⎜ gm * R sC4 9 + R8 ⎠ ⎝ Phase 0 0dB Ve C4 - -(11) Figure 11 shows gain and phase of the LC filter. Since we already have 180o phase shift just from the output filter, the system risks being unstable. Comp - -(13) -40dB/decade The (s) indicates that the transfer function varies as a function of frequency. This configuration introduces a gain and zero, expressed by: FLC Frequency -180 FLC [H(s)] = ⎛⎜⎜ g Frequency ⎝ Fig. 11: Gain and Phase of LC filter The IR3651’s error amplifier is a differential-input transconductance amplifier. The output is available for DC gain control or AC phase compensation. The error amplifier can be compensated either in typeII or typeIII compensation. When it is used in typeII compensation the transconductance properties of the error amplifier become evident and can be used to cancel one of the output filter poles. This will be accomplished with a series RC circuit from Comp pin to ground as shown in figure 12. This method requires that the output capacitor should have enough ESR to satisfy stability requirements. In general the output capacitor’s ESR generates a zero typically at 5kHz to 50kHz which is essential for an acceptable phase margin. 10/11/2006 Fz = m * R9 ⎞ ⎟ * R3 R9 + R8 ⎟⎠ 1 2π * R3 * C4 - -(14) The gain is determined by the voltage divider and error amplifier’s transconductance gain. First select the desired zero-crossover frequency (Fo): Fo > FESR and Fo ≤ (1/5 ~ 1/10) * Fs Use the following equation to calculate R4: R3 = Vosc * Fo * FESR * (R8 + R9 ) Vin * FLC2 * R9 * gm - -(15) Where: Vin = Maximum Input Voltage Vosc = Oscillator Ramp Voltage Fo = Crossover Frequency FESR = Zero Frequency of the Output Capacitor FLC = Resonant Frequency of the Output Filter R8 and R9 = Feedback Resistor Dividers gm = Error Amplifier Transconductance 15 IR3651SPbF To cancel one of the LC filter poles, place the zero before the LC filter resonant frequency pole: VO ZIN Fz = 75%FLC C3 C7 1 Fz = 0.75 * 2π Lo * Co - -(16) R3 R10 Zf Using equations (15) and (16) to calculate C4. One more capacitor is sometimes added in parallel with C4 and R3. This introduces one more pole which is mainly used to suppress the switching noise. The additional pole is given by: FP = CPOLE = 1 π * R3 * Fs − For FP << Fb R9 1 C4 ≅ Fs 2 For a general solution for unconditionally stability for any type of output capacitors, in a wide range of ESR values we should implement local feedback with a compensation network (typeIII). The typically used compensation network for voltage-mode controller is shown in figure 15. In such configuration, the transfer function is given by: Ve 1 − g m Zf = Vo 1 + g m ZIN The error amplifier gain is independent of the transconductance under the following condition: g m * Zf >> 1 and g m * Zin >> 1 Ve FZ2 FP2 FP3 Frequency Fig.15: Compensation network with local feedback and its asymptotic gain plot As known, transconductance amplifier has high impedance (current source) output, therefore, consideration should be taken when loading the error amplifier output. It may exceed its source/sink output current capability, so that the amplifier will not be able to swing its output voltage over the necessary range. The compensation network has three poles and two zeros and they are expressed as follows: FP1 = 0 FP 2 = 1 2π * R10 * C7 FP 3 = 1 1 ≅ ⎛ C * C3 ⎞ 2π * R3 * C3 ⎟⎟ 2π * R3 ⎜⎜ 4 ⎝ C4 + C3 ⎠ Fz1 = 1 2π * R3 * C4 Fz 2 = 1 1 ≅ 2π * C7 * (R8 + R10 ) 2π * C7 * R8 - -(17) By replacing Zin and Zf according to figure 15, the transformer function can be expressed as: Comp H(s) dB FZ1 1 π * R3 * Fs E/A VREF Gain(dB) 1 C *C 2π * R3 * 4 POLE C4 + CPOLE The pole sets to one half of switching frequency which results in the capacitor CPOLE: C4 R8 Cross over frequency is expressed as: H (s ) = (1 + sR3C4 ) * [1 + sC7 (R8 + R10 )] 1 * sR8 (C4 + C3 ) ⎡ ⎛ C4 * C3 ⎞⎤ ⎟⎟⎥ * (1 + sR10C7 ) ⎢1 + sR3 ⎜⎜ ⎝ C4 + C3 ⎠⎦ ⎣ 10/11/2006 Fo = R3 * C7 * Vin 1 * Vosc 2π * Lo * Co 16 IR3651SPbF Based on the frequency of the zero generated by output capacitor and its ESR versus crossover frequency, the compensation type can be different. The table below shows the compensation types and location of crossover frequency. Compensator type FESR vs. Fo Output capacitor TypII(PI) FLC<FESR<Fo<Fs/2 Electrolytic , Tantalum TypeIII(PID) Method A FLC<Fo<FESR<Fs/2 Tantalum, ceramic TypeIII(PID) Method B FLC<Fo<Fs/2<FESR Ceramic The following design rules will give a crossover frequency approximately one-tenth of the switching frequency. The higher the band width, the potentially faster the load transient response. The DC gain will be large enough to provide high DC-regulation accuracy (typically -5dB to -12dB). The phase margin should be greater than 45o for overall stability. Desired Phase Margin: For FLC<Fo<Fs/2<FESR typeIII method B is selected to place the pole and zeros. Fo < FESR and Fo ≤ (1/5 ~ 1/10) * Fs FZ 2 = Fo * FP 2 = Fo * 1 − SinΘ 1 + SinΘ 1 + SinΘ 1 − SinΘ Select : FZ1 = 0.5 * FZ 2 and FP3 = 0.5 * Fs R3 ≥ 2 ; gm C4 = 1 ; 2π * FZ1 * R 3 C3 = 1 ; 2π * FP 3 * R3 C7 = 2π * Fo * Lo * Co * Vosc ; R3 * Vin 3 Calculate R10, R8 and R9 : R10 = 1 ; 2π * C7 * FP 2 R8 = 1 − R10; 2π * C7 * FZ 2 R9 = Vref * R8 ; Vo − Vref Programming the Current-Limit The Current-Limit threshold can be set by connecting a resistor (RSET) from drain of low side MOSFET to the OCSet pin. The resistor can be calculated by using equation (3). The RDS(on) has a positive temperature coefficient and it should be considered for the worse case operation. This resistor must be placed close to the IC, place a small ceramic capacitor from this pin to ground for noise rejection purposes. ISET = IL(critical) = 10/11/2006 π Calculate C4 , C3 and C7 : Table1- The compensation type and location of FESR versus Fo The details of these compensation types are discussed in application note AN-1043 which can be downloaded from IR Web-Site. Θmax = ROCSet ∗ IOCSet RDS(on) --(3 ) 17 IR3651SPbF Layout Consideration The layout is very important when designing high frequency switching converters. Layout will affect noise pickup and can cause a good design to perform with less than expected results. Start to place the power components, make all the connection in the top layer with wide, copper filled areas. The inductor, output capacitor and the MOSFET should be close to each other as possible. This helps to reduce the EMI radiated by the power traces due to the high switching currents through them. Place input capacitor directly to the drain of the high-side MOSFET, to reduce the ESR replace the single input capacitor with two parallel units 10/11/2006 . The feedback part of the system should be kept away from the inductor and other noise sources. The critical bypass components such as capacitors for Vcc, DRVc and Vb should be close to respective pins. It is important to place the feedback components including feedback resistors and compensation components close to Fb and Comp pins. In multilayer PCB use one layer as power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. The goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. These two grounds must be connected together on the PC board layout at a single point. 18 IR3651SPbF 1 1 1 Figure A IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 This product has been designed and qualified for the Industrial market. Visit us at www.irf.com for sales contact information Data and specifications subject to change without notice. 10/11/2006 10/11/2006 19