INFINEON PMB2349

Wireless Components
Optimized RF/IF Dual PLL Frequency Synthesizer
PMB 2349 Version 1.0
Specification May 2000
Confidential
TARGET SPECIFICATION
CONFIDENTIAL
Revision History: Current Version: May 2000
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Edition 03.99
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PMB 2349
TARGET SPECIFICATION
Product Info
Confidential
Product Info
General Description
Features
Package
The PMB 2349 is a RF/IF Dual-PLL
frequency synthesizer implemented in
Infineon’s high speed BiCMOS technology B6HFC. The device contains
two PLLs with integrated prescalers
especially designed for use in battery
powered radio equipment and mobile
telephones. Primary applications are
P-VQFN-24-3
single- and dual-band digital cellular
systems e.g. GSM, PCN (DCS 1800)
and PCS systems.
Operation range 2.7 to 5.0 V
Dividing ratios:
A counters: PLL1: 0 to 63
PLL2: 0 to 15
N counters: PLL1: 3 to 16,383
PLL2: 3 to 16,383
R counters 3 to 16,383 for PLL1
and PLL2
Ultra low phase noise
Ultra low spurious
Faster lock-in times
New bipolar power modes
New programmable Reference
Amplifier
Fast phase detectors and charge
External or internal reference cur-
Switchable polarity and program-
pump outputs without dead zone
rent setting for PD outputs
mable phase detector currents
Low operating current consumption Fast serial 3-wire bus interface with
low threshold voltage Schmitt-Trig Programmable power down modes
ger inputs for interfacing with low
High input sensitivity and high input
voltage baseband circuits
frequencies: PLL1 (RF): 2.8 GHz
Two data registers in PLL2 for fast
PLL2 (IF): 600 MHz
Programmable dual modulus
prescaler divide ratio:
PLL1: 1:64/65 or 1:32/33
PLL2: 16/17 or 1:8/9
IF band switching
A programmable output port for
lock detect or general porpose
(VCO switch etc.).
Ordering Information
Type
Ordering Code
PMB 2349
Wireless Components
Package
P-VQFN-24
Product Info
Specification, May 2000
1
Table of Contents
2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1
2.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-2
2.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-2
2.3
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-3
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1
3.1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2
3.2
Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3
3.3
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-7
3.4
Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-8
3.4.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-8
3.4.2 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-8
3.4.3 Standby Condition (power down) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-10
3.4.4 Divide ratio programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-10
3.4.5 Prescaler Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-10
3.4.6 Fast wake-up programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-11
3.4.7 Phase Detector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-11
4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1
4.1
Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-2
5 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1
5.1
Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-2
5.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-2
5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-3
5.1.3 Typical Supply Current ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-3
5.1.4 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-4
5.2
Serial Control Data Format Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-6
5.3
Serial Control Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-7
5.4
Input Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-12
5.4.1 Typical RF Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-12
5.4.2 Typical IF Sensitivity: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-12
5.4.3 Typical Ri Sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-13
5.5
Charge Pump Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-14
5.5.1 Carge Pump Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-14
5.5.2 Typical Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-15
5.6
5-15
Threshold Voltages of Schmitt-Trigger Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
Product Description
Contents of this Chapter
2.1
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.3
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
PMB 2349
preliminary
Product Description
Confidential
2.1 Overview
The PMB 2349 is a RF/IF Dual-PLL frequency synthesizer implemented in Infineon’s high speed BiCMOS technology B6HFC. The device contains two PLLs
with integrated prescalers especially designed for use in battery powered radio
equipment and mobile telephones. Primary applications are single- and dualband digital cellular systems e.g. GSM, PCN (DCS 1800) and PCS systems.
2.2 Features
Operation range 2.7 to 5.0 V
Ultra low phase noise
Ultra low spurious
Faster lock-in times
New bipolar power modes
New programmable Reference Amplifier
External or internal reference current setting for PD outputs
Low operating current consumption
Programmable power down modes
High input sensitivity and high input frequencies:
PLL1 (RF): 2.8 GHz, PLL2 (IF): 600 MHz
Programmable dual modulus
prescaler divide ratio:
PLL1: 1:64/65 or 1:32/33
PLL2: 16/17 or 1:8/9
Dividing ratios:
A counters: PLL1: 0 to 63
PLL2: 0 to 15
N counters: PLL1: 3 to 16,383
PLL2: 3 to 16,383
R counters 3 to 16,383 for PLL1 and PLL2
Fast phase detectors and charge pump outputs without dead zone
Switchable polarity and programmable phase detector currents
Fast serial 3-wire bus interface with low threshold voltage Schmitt-Trigger
inputs for interfacing with low voltage baseband circuits
Two data registers in PLL2 for fast IF band switching
A programmable output port for lock detect or general porpose (VCO switch
etc.).
Wireless Components
2-2
Specification, May 2000
PMB 2349
preliminary
Product Description
Confidential
2.3 Package Outlines
VQFN-24-3.eps
Figure 2-1
Wireless Components
P-VQFN-24
2-3
Specification, May 2000
3
Functional Description
Contents of this Chapter
3.1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2
Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
3.3
Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
3.4.6
3.4.7
Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Standby Condition (power down) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Divide ratio programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Prescaler Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Fast wake-up programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Phase Detector Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
PMB 2349
preliminary
Functional Description
Confidential
VPD2
CP2
GND1
IF
IFX
GND2
RI
NC
20
19
18
17
16
15
14
13
3.1 Pin Configuration
12
R e xt
11
M FO
23
10
CLK
24
9
3
4
5
6
7
8
RF1
RFX
GND2
EN
DA
NC
GND1
VCC1
PM B 2349
2
22
CP1
VCC2
1
21
VPD1
BACK
BACK
Pin_config.wmf
Figure 3-1
Wireless Components
Pin Configuration
3-2
Specification, May 2000
PMB 2349
preliminary
Functional Description
Confidential
3.2 Pin Definition and Function
Table 3-1 Pin Definition and Function
Pin No.
Symbol
23
VCC1
Positive supply voltage
for CMOS circuitry
1
VPD1
Positive supply voltage
for charge pump of PLL1
2
CP1
PLL1 charge pump output
Phase detector tristate
charge pump output
Equivalent I/O-Schematic
Function
P D O u tp ut E q u iva le n t
3
*2 p F
CP1
E SD
3
GND1
Ground for CMOS circuitry
4
RF1
RF frequency input 1
RF input with highly sensitive preamplifier for
PLL1.
AC coupling must be set
up.
R F a n d IF In p u t E q u iva le n t
5 /1 6
5
6 /1 5
RFX
R F /IF
6
R F x/IF x
GND2
Wireless Components
RF frequency input
(inverted)
RF input with highly sensitive preampifier for
PLL1.
AC coupling must be set
up
Ground for bipolar circuitry
3-3
Specification, May 2000
PMB 2349
preliminary
Functional Description
Confidential
Table 3-1 Pin Definition and Function (continued)
Pin No.
Symbol
7
EN
Equivalent I/O-Schematic
S e ria l C o n tro l In p ut E q u iva le n t
7 5 kΩ
8
560Ω
CLK
*2 p F
ESD
8
DA
S e ria l C o n tro l In p ut E q u iva le n t
7 5 kΩ
9
DA
560Ω
*2 p F
Function
3-Wire bus input:
Enable
Enable input of the serial
control interface with
Schmitt-Trigger input
stage. When EN=H the
input signals CLK and DA
are disabled. When EN=L
the serial control interface
is enabled. The received
data are transferred to the
registers with the positive
edge of the EN-signal.
3-Wire bus input: Data
Data input of the serial
control interface with
Schmitt-Trigger input
stage.The serial data are
read into the internal shift
register with the positive
edge of CLK.
ESD
10
CLK
S e ria l C o n tro l In p ut E q u iva le n t
7 5 kΩ
10
EN
3-Wire bus input: Clock
Clock input of the serial
control interface with
Schmitt-Trigger input
stage
560Ω
*2 p F
ESD
11
MFO
L D a s L o ck D e te cto r
11
*2 p F
L D /fo
ESD
Wireless Components
3-4
Lock detector output
Unipolar output of the
phase detector in the
form of a pulse-width
modulated signal. In the
locked state the output
signal is at H-level. In
standby mode the output
is resistive.
For test purpose the push
pull output fo is enabled.
Specification, May 2000
PMB 2349
preliminary
Functional Description
Confidential
Table 3-1 Pin Definition and Function (continued)
Pin No.
Symbol
12
Rext
Equivalent I/O-Schematic
Function
CP & Prescaler reference current setting
External resistor for CP &
Prescaler reference current setting.
O S W O utp u t E q u iva le n t
12
2pF
R e xt
ESD
14
RI
R I In put E qu ivale nt
STDBY
5 00K Ω
13
5 60Ω
RI
Reference frequency
input
Input with highly sensitive preamplifier. With
small input signals AC
coupling must be set up,
where DC coupling can
be used for large input
signals.
2 pF
ESD
/S T D B Y
15
GND2
Ground for bipolar circuitry
16
IFX
IF frequency input
(inverted)
IF input with highly sensitive preampifier for PLL2.
AC coupling must be set
up.
R F a n d IF In p u t E q u iva le n t
17
18
IF
5 /1 6
6 /1 5
R F /IF
R F x/IF x
GND1
Wireless Components
IF frequency input
IF input with highly sensitive preampifier for PLL2.
AC coupling must be set
up.
Ground for CMOS circuitry
3-5
Specification, May 2000
PMB 2349
preliminary
Functional Description
Confidential
Table 3-1 Pin Definition and Function (continued)
Pin No.
Symbol
19
CP2
Equivalent I/O-Schematic
Function
Phase detector tristate
charge pump output for
PLL2
P D O u tp ut E q u iva le n t
18
*2 p F
CP2
E SD
20
VPD2
Positive supply voltage
for charge pump 2.
22
VCC2
Positive supply voltage
for bipolar circuitry
9+21
BACK
Backplane - BIPOLAR
ground recommended
13+24
NC
not connected
Wireless Components
3-6
Specification, May 2000
PMB 2349
preliminary
Functional Description
Confidential
3.3 Functional Block Diagram
PLL1 (RF)
Mod1
VCC1
Modulus Control
VCC2
14 Bit
N-Counter
6 Bit
A-Counter
Data Reg.
Shadow Reg.
Data Reg.
Shadow Reg.
Shift Register
Shift Register
VPD1
VPD2
Phase
Detector
PD1
Mod1
64/65
32/33
GND1
RF
14 Bit
R1-Counter
14 Bit
R1-Counter
Data Reg.
Shadow Reg.
Data Reg.
Shift Register
Shift Register
Phase
Detector
PD2
GND1
IF
IFX
Mod2
16/17
8/9
RFX
Modulus Control
GND2
GND2
14 Bit
N-Counter
4 Bit
A-Counter
EN
Serial
Control
Logic
Dec
DA
RI
Multiplexer
Multiplexer
Data Reg. 1
Data Reg. 2
Data Reg. 1
Data Reg. 2
Shift Register
Bias
Iref
Shift Register
LD
fo
CLK
REXT
LD
PLL2 (IF)
Funct_block.wmf
Figure 3-2
Wireless Components
Functional Block Diagram
3-7
Specification, May 2000
PMB 2349
preliminary
Functional Description
Confidential
3.4 Circuit Description
3.4.1
General Description
The PMB 2349 consists of two fully programmable PLLs, one for the RF and
one for the IF frequency range. Each PLL contains a high frequency dual modulus prescaler, an A- and a N-counter with dual modulus control logic, a reference- (R-) counter, and a phase detector with charge pump output. The two
synthesizers are controlled via the common serial 3-wire interface.
The reference frequency is applied at the common RI-input and divided by the
R-counter of each PLL. Its maximum value is 45 MHz. The RF and IF input frequencies will be divided by the corresponding prescalers with a programmable
32/32 or 64/65 (RF) and 8/9 or 16/17 (IF) divide ratio and the following programmable A/N-counters. The maximum RF frequency value is 2.8 GHz and 600
MHz for the IF frequency.
The phase and frequency detectors with the charge pumps have a linear operating range without a dead zone for very small phase deviations.
The multifunctional output port LD/MFO can be programmed as lock detector
and general purpose output.
3.4.2
Programming
Programming of the IC is done via the serial data interface. The content of the
bus telegram (serial data format) is assigned to the functional units according
to the address.
The most significant bit (MSB) of the serial data formats is shifted first.
The short control data format allows a fast PD-current change.
The long control data format allows the programming of asynchronous or synchronous data acquisition of PLL1 (RF), 4 different PD-output current modes for
the PLL1 and 1 PD-output current modes for PLL2, polarity setting of the PDoutput signals, 2 standby modes, charge pump pulse width and the prescaler
divide ratio.
The A/N-counter data format of PLL1 contains the A/N-counter value.. The data
format of PLL2 comprise the counter values as well.
The R-counter data format contains the R-counter values.
The PLL1 (RF) of PMB 2349 offers the possibility of synchronous counter and
charge pump current programming to avoid phase errors at the phase detector
when R- and A-/N-counter are programmed one after another or the charge
pump current is altered.
Wireless Components
3-8
Specification, May 2000
PMB 2349
preliminary
Functional Description
Confidential
Asynchronous Mode:
The serial data is written directly to the data registers of the addressed counter
with the Enable pulse. As each counter is loading the new starting value after it
is decremented to „zero“, the counters changes therefore their counter values
asynchronously to the others.
Synchronous Mode (only for RF):
In this mode counter programming is controlled by the R- and N-counters. The
serial data (exception: higher part of long control data format) is first written with
the Enable pulse to the corresponding shadow registers. From there the values
for R-counter, A-/N-counter and charge pump current values of short/long control data format are loaded into the corresponding data register when the Ncounter reaches „zero+1“. Therefore the change of all counter states is synchronised to the reloading of the N-counter to avoid additional phase error
caused by the programming. The transfer of the charge pump current values
into the corresponding data register is tied to the N-counter loading, but follows
the loading of the N-data register in the distance of one N-counter dividing ratio.
This guarantees that a new PD-current value becomes valid at the same time
when the counters are loaded with the new data.
Synchronous programming sequence:
1. Setting of synchronous counter programming by bit c13 of long control data
format.
2. Programming of the R-counter, and optional short control data format. With
the Enable signal data is loaded into the shadow registers.
3. Programming of the A/N-counter. Data is loaded into shadow registers, the
EN-signal starts the synchronous transfer to the data registers.
Synchronous data programming is of especial advantage, when large frequency steps are to be made in a short time. For this purpose a high reference
frequency can be programmed in order to achieve rapid – “rough” – transient
response. This method increases the fundamental frequency by nearly the
square root of the reference frequency ratio and therefore the settling time is
reduced. When rough lock is achieved, another synchronous data transfer is
needed to switch back to the original channel spacing. A “fine” lock in will finish
the total step response. It may not be necessary to change reference frequency,
but it make sense to perform synchronous data acquisition in any case. Especially for GSM, PCN (DCS 1800) and PCS systems the synchronous mode
should be used to achieve best performance of the PMB 2347.
Wireless Components
3-9
Specification, May 2000
PMB 2349
preliminary
Functional Description
Confidential
3.4.3
Standby Condition (power down)
Each PLL of the PMB 2349 has two programmable standby modes to reduce
the current consumption (standby 1, standby 2).
Standby 1: The corresponding PLL is switched off, the current consumption
is reduced below 1 µA.
Standby 2:
3.4.4
The corresponding counters, the charge pump and the outputs
are switched off. Only the preamplifier of RI-input stays active.
(See standby table)
Divide ratio programming
The frequency of an external VCO controlled by the PMB 2347 is given below:
f RI
M
f VCO = [ ( P ⋅ N ) + A ] ⋅ ------- = ----- ⋅ f RI
R
R
with A ≤ N .
fVCO:
fRI:
N:
A:
P:
R:
M=P*N+A:
frequency of the external VCO
reference frequency
divide ratio of the N-counter
divide ratio of the A-swallow counter
divide ratio of the prescaler
divide ratio of the R-counter
total divide ratio
Note:
for continous frequency steps following condition is necessary
[P ⋅ N + A] ≥ P ⋅ (P – 1)
3.4.5
Prescaler Divide Ratio
For the highest input frequencies of the prescalers the larger divide ratio is necessary:
RF-PLL:
64/65 for frequencies greater 1500 MHz
IF-PLL:
16/17 for frequencies greater 375 MHz
Wireless Components
3 - 10
Specification, May 2000
PMB 2349
preliminary
Functional Description
Confidential
3.4.6
Fast wake-up programming
When the circuit is connected to the supply voltage all registers are undefined.
Due to the fact that each counter is loading its new start value after it is decremented to „zero“, the start-up time of the counters with the programmed values
is too long for some applications. If the counters are programmed in standby
mode 2 and the PLLs are switched afterwards in operating mode, the counters
are starting immediatly with the programmed values. Therefore following data
transfer sequence is recommended:
Table 3-2 Fast Wake Up Data Transfer Sequence
3.4.7
Step
Serial Data Transfer Sequence
1
Long Control Word: Asynchronous Mode, Standby2
2
R-Counter
3
A-/N-Counter
4
Long Control Word: Synchronous Mode, Operating Mode
Phase Detector Outputs
RI
fR
(RI:R)
RF1/2
fV
CP
(RF1:M)
(RF2:M)
P-Channel
Tri-State
N-Channel
positive Polarity
CP
P-Channel
Tri-State
N-Channel
negative Polarity
LD
Frequency fV < fR
fV lagging
Frequency fV > fR
fV leading
Frequency fV = fR
lock state
The timing diagram is valid for PLL1 and PLL2.
Wireless Components
3 - 11
Specification, May 2000
4
Applications
Contents of this Chapter
4.1
Hint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
PMB 2349
preliminary
Applications
Confidential
4.1 Hint
More Information about “Application” see in separate Document
APPLICATION NOTE PMB 2349.
Wireless Components
4-2
Specification, May 2000
5
Reference
Contents of this Chapter
5.1
Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
5.2
Serial Control Data Format Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
5.3
Serial Control Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5.4
Input Sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5.5
Charge Pump Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14
5.6
Threshold Voltages of Schmitt-Trigger Input . . . . . . . . . . . . . . . . . . 5-15
PMB 2349
preliminary
Reference
Confidential
5.1 Electrical Data
5.1.1
Absolute Maximum Ratings
WARNING
The maximum ratings may not be exceeded under any circumstances, not even
momentarily and individually, as permanent damage to the IC will result.
Table 5-1 Absolute Maximum Ratings
#
Parameter
Symbol
Limit Values
min
max
Unit
1
Supply Voltage
VCC1/2
-0.3
5.5
V
2
Input Voltage
VI
-0.3
VCC1/
2+0.3
V
3
Output Voltage
VO
GND
VCC1/2
V
4
Total power dissipation
Ptot
5
Ambient temperature
TA
6
Storage temperature
TStg
7
Thermal Resistance
8
ESD Integrity
(according to MIL 883 Method 3015.7)
except Pins Vpd1[2] and Vpd2[19]
Wireless Components
300
mW
-40
85
°C
-50
125
°C
RthJA
170
K/W
VESD
0.5
KV
5-2
Remarks
in operation
preliminary
Specification, May 2000
PMB 2349
preliminary
Reference
Confidential
5.1.2
Operating Range
Within the operational range the IC operates as described in the circuit
description.
The AC/DC characteristic limits are not guaranteed.
Table 5-2 Operating Range, VCC1/2= 2.7V - 5.0V, TAMB=-27°C
#
Parameter
Symbol
Limit Values
min
Unit
Test Conditions
L
Item
max
1
Supply Voltage
VCC1/2
2.7
5.0
V
2
Input frequency RF
ƒRF
250
2800
MHz
3
Input frequency IF
ƒIF
100
600
MHz
4
Input reference frequency
ƒRi
1
45
MHz
5
CP-output current of
PLL1
/ ICP1 /
4
+20%
mA
6
CP-output current of
PLL2
/ ICP2 /
1
+20%
mA
7
CP-output voltages
VCP1/2
0.5
VPD1/2
- 0.5
V
8
Ambient temperature
TA
-40
85
°C
VCC1/2 = 3.6V
This value is guaranteed by design.
5.1.3
Typical Supply Current ICC
Table 5-3 Typical Supply Current ICC
#
Parameter
Symbol
Limit Values
min
typ
Unit
Item
max
1
Supply Voltage
2.7
2
Supply current:
3
PLL1 & PLL2 active
ICC1/2
-20%
9402
+20%
µA
4
PLL1 active, PLL2 standby
ICC1/2
-20%
7840
+20%
µA
5
PLL1 standby2, PLL2 active
ICC1/2
-20%
3065
+20%
µA
6
PLL1 & PLL2 standby 2
ICC1/2
120
µA
7
PLL1 & PLL2 standby 1
ICC1/2
<1
µA
VCC1/2
Test Conditions
V
Note 1)
1) VCC1/2= 2.7V, REXT = 12k, RF-/ IF- and Ri-inputs are open,
3WB optical interface, ICP1 = 4.0mA, ICP2 = 2.0mA, Iref = 100 µA
Wireless Components
5-3
Specification, May 2000
PMB 2349
preliminary
Reference
Confidential
5.1.4
AC/DC Characteristics
AC/DC characteristics involve the spread of values guaranteed within the specified supply voltage and ambient temperature range. Typical characteristics are
the median of the production.
Table 5-4 AC/DC Characteristics with VCC1/2=2.7 .. 5.0 V, Ambient temperature TAMB= 27°C
Symbol
Limit Values
min
typ
Unit
Test Conditions
D Item
max
Input Signals DA, CLK, EN (Schmitt-Trigger input stage)
VCC
V
VIL
0.3 VCC
V
Input capacity
CI
5
pF
H-input current
IH
10
µA
VI=VCC2=3.6V
2.3
L-input current
IL
-10
µA
VI=GND
2.4
VI
100
mVrms
f= 4 - 45 MHz,
VCC1=3.6V
2.10
V/µs
VCC1=2.7 - 5.0 V
H-input voltage
VIH
L-input voltage
0.7 VCC
Input Signal RI
Input voltage
4
Slew rate
Input capacity
CI
3
pF
H-input current
IH
30
µA
VI=VCC1=3.6V
L-input current
VI
-30
µA
VI=GND
Input voltage
PI
-10
0
dBm
f = 150-500 MHz
3.1
Input voltage
PI
-10
0
dBm
f = 500-1500 MHz
3.2
Input voltage
PI
-20
-10
dBm
f = 1500-2500 MHz
3.3
Input voltage
PI
-15
-10
dBm
f = 2500-2800 MHz
3.4
Input voltage
PI
-15
+4
dBm
f = 50 - 300 MHz
4.1
Input voltage
PI
-25
-5
dBm
f = 200 - 450 MHz
4.2
Input voltage
PI
-25
-15
dBm
f = 450 - 600 MHz
4.3
2.13
Input Signals RF
Input Signals IF
Wireless Components
5-4
Specification, May 2000
PMB 2349
preliminary
Reference
Confidential
Table 5-4 AC/DC Characteristics with VCC1/2=2.7 .. 5.0 V, Ambient temperature TAMB= 27°C (continued)
Symbol
Limit Values
Unit
Test Conditions
D Item
Output Current ICP1
"1.2 mA"
ICP1
-20%
1.2
+20%
mA
"2.0 mA"
ICP1
-20%
2.0
+20%
mA
"2.8 mA"
ICP1
-20%
2.8
+20%
mA
"4.0 mA"
ICP1
-20%
4.0
+20%
mA
"Tristate"
/ICP1/
0.1
10*)
nA
+20%
mA
0.1
10*)
nA
VPD1=3.6V,
VCP1=VPD1/2
IREF=100µA
5.1
5.2
5.3
5.4
5.5
Output Current ICP2
"1.0 mA"
ICP2
"Tristate"
/ICP2/
-20%
VPD1=3.6V,
VCP2=VPD2/2
IREF=100µA
Output Current Offset CP1 & CP2
CP Supply Voltage
VPD1/2
2.7
3.6
5.0
V
CP Current Offsett
ICP-OFF
-4
0
+13
%
VCP1/2 = VPD1/2/2
Current Mismatch
"1.2 mA"
ICPMM
%
"2.0 mA"
ICPMM
%
"2.8 mA"
ICPMM
%
"4.0 mA"
ICPMM
%
VPD1=3.6V,
VCP1 = VPD1/2
IREF=100 µA
Output Rext
VRext
VRext
1.2
V
VCC2 = 3.6V, Rext=12k
IRext
IRext
100
µA
VCC2 = 3.6V, Rext=12k
0.4
V
VCC1 = 2.7 - 3.6V,
IOL = 0.3 mA
10
ns
VCC1 = 3.6V,
CI = 10pF
10.1
Output Signal BSW at BSW/LD-Pin (n-channel open drain)
L-output voltage
VOL
Fall time
tF
3
these values are guaranteed by design
see chapter 5.5.2 (Charge Pump Performance - Typical Performance) for
Wireless Components
5-5
VCP-range CONSERVATIVE
Specification, May 2000
PMB 2349
preliminary
Reference
Confidential
5.2 Serial Control Data Format Timing
tR
tF
≈
tWHCL
VIH
CLK
VIL
tWLCL
≈
VIL
≈
tDS
VIH
DA
tCLE
tECL
VIH
VIL
≈
EN
≈ ≈
tWHEN
VIH
PORT
VIL
tDEP
Table 5-5
Parameter
Symbol
Limit Values
min.
ƒCL
Clock frequency
Unit
max.
15
MHz
H-pulsewidth (CLK)
tWHCL
30
ns
L-pulsewidth (CLK)
tWLCL
30
ns
Data setup
tDS
20
ns
Setup time Clock-Enable
tCLE
20
ns
Setup time Enable-Clock
tECL
20
ns
H-pulsewidth (Enable)
tWHEN
60
ns
Rise, fall time
tR, tR
10
µs
Propagation delay time EN-PORT
tDEP
1
µs
Wireless Components
5-6
Specification, May 2000
PMB 2349
preliminary
Reference
Confidential
5.3 Serial Control Data Formats
Table 5-6 Address of Data Formats
Address
Data Format
Addressed PLL
a2
a1
a0
0
0
0
Short Control Data Format
PLL1 (RF)
0
1
0
Long Control Data Format
PLL1 (RF)
1
0
0
A-/N-Counter
PLL1 (RF)
1
1
0
R-Counter
PLL1 (RF)
0
0
1
Short Control Data Format
PLL2 (IF)
0
1
1
Long Control Data Format
PLL2 (IF)
1
0
1
A-/N-Counter
PLL2 (IF)
1
1
1
R-Counter
PLL2 (IF)
In general each PLL can independently be addressed without affecting the
other PLL (See also Test Modes).
NOTE: MSB of all serial data is shifted first
Table 5-7 Short Control Data Formats
PLL 1
Bit
PLL 2
Bit
Function
Bit
Bit
Function
LSB
0
0
a0
Address
LSB
0
1
a0
Address
1
0
a1
Address
1
0
a1
Address
2
0
0
a2
Address
2
a2
Address
3
c0
LD InActive
3
c0
reserved
4
c1
CP current 2
4
c1
reserved
5
c2
CP current 1
5
c2
CP current
6
MSB
c3
PLLSel
6
MSB
c3
reserved
Table 5-8 Long Control Data Formats
PLL 1
Bit
PLL 2
Bit
Function
Bit
Bit
Function
LSB
0
0
a0
Address
LSB
0
1
a0
Address
1
1
a1
Address
1
1
a1
Address
2
0
0
a2
Address
2
a2
Address
3
c0
LD inactive
3
c0
RiAmp 2
4
c1
CP current 2
4
c1
RiAmp 1
5
c2
CP current 1
5
c2
CP current 1
6
c3
PLLSel
6
c3
Data-Reg Select
7
c4
PSC Div. Ratio
7
c4
PSC Div. Ratio
Wireless Components
5-7
Specification, May 2000
PMB 2349
preliminary
Reference
Confidential
Table 5-8 Long Control Data Formats (continued)
PLL 2
PLL 1
Bit
Bit
Function
Bit
Bit
Function
8
c5
reserved
8
c5
MFO
9
c6
CPP width 2
9
c6
CPP width 2
10
c7
CPP width 1
10
c7
CPP width 1
11
c8
standby 2
11
c8
standby 2
12
c9
standby 1
12
c9
standby 1
13
c10
CP polarity
13
c10
CP polarity
14
c11
Mode 2
14
c11
IBip 2
15
c12
Mode 1
15
c12
IBip 1
16
MSB
c13
Sync/Async
Mode
16
MSB
c13
Rext / Rint
Table 5-9 A/N-counter Data Formats
PLL 2
PLL 1
Bit
Bit
Function
Bit
Bit
Function
LSB
0
0
a0
Address
LSB
0
1
a0
Address
1
1
a1
Address
1
0
a1
Address
2
0
a2
Address
2
1
a2
Address
3
LSB
LSB
n0
n0
3
4
n1
4
n1
5
n2
5
n2
6
n3
6
n3
7
n4
7
n4
8
n5
8
n5
9
n6
9
n6
10
n7
10
n7
11
n8
11
n8
12
n9
12
n9
13
n10
13
n10
14
n11
14
n11
N1-Counter
n12
15
16
MSB
n13
16
MSB
n13
17
LSB
ac0
17
LSB
ac0
18
ac1
18
ac1
19
ac2
19
ac2
20
ac3
21
ac4
15
22
MSB
Wireless Components
A1-Counter
20
N2-Counter
n12
MSB
A2-Counter
ac3
ac5
5-8
Specification, May 2000
PMB 2349
preliminary
Reference
Confidential
Table 5-10 R-counter Data Formats
PLL 2
PLL 1
Bit
Function
Bit
a0
Address
LSB
0
Bit
Function
1
a0
Address
1
a1
Address
2
1
a2
Address
1
1
a1
Address
2
1
a2
Address
3
LSB
r0
3
LSB
r0
4
r1
4
r1
5
r2
5
r2
6
r3
6
r3
7
r4
7
r4
8
r5
8
r5
9
r6
9
r6
10
r7
10
r7
11
r8
11
r8
12
r9
12
r9
13
r10
13
r10
14
r11
14
r11
15
r12
15
r12
r13
16
MSB
Bit
LSB
0
0
1
MSB
16
MSB
R1-Counter
MSB
R2-Counter
r13
Table 5-11 Programming of Operation and Test Modes
c12
Mode 1
c11
Mode 2
c3
PLLSel
Functional Mode
Affected Output:
0
0
0
TEST MODE FVN - N/A-Counter
CP1 + CP2
1
0
0
TEST MODE FRN - R-Counter
CP1 + CP2
0
1
0
NORMAL OPERATION, MFO active
LD / MFO Pin
1
1
0
NORMAL OPERATION, LD of PLL1 active
LD / MFO Pin
0
0
1
TEST MODE FVN - N/A-Counter
CP1 + CP2
1
0
1
TEST MODE FRN - R-Counter
CP1 + CP2
0
1
1
NORMAL OPERATION, MFO active
LD / MFO Pin
1
1
1
NORMAL OPERATION, LD of PLL2 active
LD / MFO Pin
Table 5-12 Programming of CP Current of PLL1
c2
CP current 1
c1
Mode 2
CP Current [mA]
0
0
1.2 mA
1
0
2.0 mA
0
1
2.8 mA
1
1
4.0 mA
Wireless Components
5-9
Remark
with 100µA reference current
( Rext = 12k ohms )
Specification, May 2000
PMB 2349
preliminary
Reference
Confidential
Table 5-13 Programming of CP Current of PLL2
c2
CP current 1
CP Current [mA]
0
Tristate
1
1.0 mA
Remark
with 100µA reference current
Table 5-14 Programming of Charge Pump Pulse Width of both PLLs
c7
CPP width 1
c6
CPP width 2
Pulse Width [ns] typ.
0
0
1.8 ns
1
0
2.7 ns
0
1
3.6 ns
1
1
4.5 ns
Remark
Table 5-15 Standby of Power Down Programming of both PLLs
Control Bits
Mode
Affected Output Pins
Z: High Impedance (Tristate)
c9
standby 1
c8
standby 2
Pin 11
LD/fo
Pin 3
CP1
Pin 18
CP2
0
0
standby1
off
Z
Z
1
0
standby2
off
Z
Z
0
1
standby1
off
Z
Z
1
1
Operation Mode
active
active
active
Table 5-16 Programming of Synchronous/Asynchronous Mode of PLL1
c13
Sync/Async
Synchronous/Asynchronous Mode
0
Asynchronous Mode of PLL 1
1
Synchronous Mode of PLL 1
Table 5-17 Programming of PD Polarity of both PLLs
Control Bit
PD Polarity
c10
PD Polarity
0
negative Polarity
1
positive Polarity
Wireless Components
5 - 10
Specification, May 2000
PMB 2349
preliminary
Reference
Confidential
Table 5-18 Programming of Prescaler Divide Ratio of both PLLs
Prescaler Divide Ratio
Control Bit
c4
PSC Div. Ratio
0
PLL1: 32/33
PLL2: 8/9
1
PLL1: 64/65
PLL2: 16/17
Table 5-19 Programming of PLL Select
PLL Select (LD mode)
Control Bit
c3 of PLL1
0
PLL1 (RF)
1
PLL2 (IF)
Table 5-20 Programming of Data Register Select
Control Bits
IF Data Register Select
c3 of PLL2
0
Data Register 1
1
Data Register 2
Table 5-21 Programming of Reference Input Amplifier - RiAmp
c0 of PLL2
RiAmp 2
c1 of PLL2
RiAmp 1
RiAmp Resonance
Pole Position typical
VCC1=VCC2= 2V7 (2V8)
0
0
9.0 MHz
nominal / recommended
1
0
11.2 MHz
0
1
19.5 MHz
1
1
28.2 MHz
Remark
Table 5-22 Programming of Bipolar Power Mode - IBip
c11 of PLL2
IBip 2
c12 of PLL2
IBip 1
Bipolar Power
Consumtion
ƒRF MAX
ƒIF MAX
Remark
0
0
nominal
2.8 GHz
0.6 GHz
nominal / recommended
1
0
nominal + 20 %
2.8 GHz
0.6 GHz
not recommended
0
1
nominal - 40 %
2.0 GHz
0.4 GHz
powersave mode II
1
1
nominal - 20 %
2.5 GHz
0.5 GHz
powersave mode I
Table 5-23 Programming of Rext / Rint Mode
c13 of PLL2
Rext / Rint
External or Internal Reference Resistor
0
External @ Pin 12 - recommended
1
Internal Polysilicone Resistor - not recommended
Wireless Components
5 - 11
Specification, May 2000
PMB 2349
preliminary
Reference
Confidential
5.4 Input Sensitivity
The following sections show the typical performance at +25°C.
5.4.1
Typical RF Sensitivity
The PLL setup is: Psc:32/33. N:3, A:1, IF-PLL is in standby mode. VCC is 2.7 V.
Chip Mode is set to ’TEST MODE FVN’. This causes the N/A divider output to be fed to
the SINK part of the chargepump (source is switched off all time.) Therefore a resistor
which provides a current path from pin CPx to VCP (CP supply) is needed.
SENSITIVITY - 32/33 N:3 A:1 - 2V7 - Rext - RF POW ER [dBm ] vs RF FREQUENCY [MHz] vs IBip[%]
5
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
0
500
1000
100% + Rext - N ominal Mode
5.4.2
1500
2000
2500
-40% + Rext - Powersave II
3000
-20% + Rext - Powersave I
Typical IF Sensitivity:
The PLL setup is: Psc:16/17. N:3, A:1, RF-PLL is in standby mode. VCC is 2.7 V..
SENSITIVITY - 16/17 N:3 A:1 - 2V5 - Rext - IF POW ER [dBm] vs IF FREQ UENCY [M Hz] vs IBip[%]
5
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
0
100
200
300
Ibip: 100% - Rext - Nominal
Wireless Components
5 - 12
400
500
Ibip: -40% - Rext - Powersave II
600
700
800
Ibip: -20% - Rext - Powersave I
Specification, May 2000
PMB 2349
preliminary
Reference
Confidential
5.4.3
Typical Ri Sensitivity
The PLL setup is: R:50. VCC is 2.7V.
Chip Mode is set to ’TEST MODE FRN’. This causes the R divider output to be fed to the
SOURCE part of the chargepump (sink is switched off all time.) Therefore a resistor
which provides a current path from pin CPx to GND (CP gnd) is needed.
SENSITIVITY S1004K2#1 - R:50 - 2V7 - Rext - Ri Power [dBm] vs Ri Frequency [MHz] vs RiAmp
CP->6.22kOhm->Gnd - HPcounter50ohm
5
-5
-15
-25
-35
-45
-55
-65
0
5
10
15
RiAmp=00b - RiRes=9.0MHz - Nominal
RiAmp=10b - RiRes=19.5MHz
Wireless Components
5 - 13
20
25
30
35
40
RiAmp=01b - RiRes=11.2MHz
RiAmp=11b - RiRes=28.2MHz
Specification, May 2000
PMB 2349
preliminary
Reference
Confidential
5.5 Charge Pump Performance
5.5.1
Charge Pump Definition
Isnkmax
Isnktyp
Isnkmin
∆Vsrc
VPD/2
∆Vsnk
VCP
Isrcmin
Isrctyp
Isrcmax
Figure 5-1
Definition of Charge Pump Currents
Terms and Abbreviations:
VPD
∆Vsrc/snk
Isnkmax
Isrcmax
Isnktyp
Isrctyp
Isnkmin
Isrcmin
Supply Voltage of Charge Pump
Offset Voltage from GND or VPD
Maximum Sink Current @ VPD-∆VSRC
Maximum Source Current @ GND+∆VSNK
Typical Sink Current @ VPD/2
Typical Source Current @ VPD/2
Minimum Sink Current @ GND+∆VSNK
Minimum Source Current @ VPD-∆VSRC
Specification of Charge Pump Characteristics:
Charge Pump Output Magnitude Variation CPMV:
Isnk
– Isnk
max
min
--------------------------------------------------2
---------------------------------------------------- ⋅ 100%
Isnk
+ Isnk
max
min
--------------------------------------------------2
Isrc
– Isrc
max
min
-----------------------------------------------2
------------------------------------------------- ⋅ 100%
Isrc
+ Isrc
max
min
------------------------------------------------2
Charge Pump Current Mismatch CPCM:
Isnk
– Isrc
typ
typ
--------------------------------------------2
---------------------------------------------- ⋅ 100%
Isnk
+ Isrc
typ
typ
---------------------------------------------2
Wireless Components
5 - 14
Specification, May 2000
PMB 2349
preliminary
Reference
Confidential
5.5.2
Typical Performance
VCP is intended to be within ∆VSNK and VPD−∆VSRC
System: standard GSM-application
RF: 900MHz, PD frequency: 200kHz, Vcc: 3.6V, TA.: -40...+85’C
Kvco: 10MHz/V, Icp: 4mA
Loopfilter (C1,R2-C2,R3,C3): 270pF,18kΩ-2.2uF,12kΩ,100pF
The following typical performance can be expected:
Table 5-24 Typical Performance
VCP-range #1 - LIBERAL
∆VSNK = 200mV
∆VSRC = 500mV
spurious suppression @200 kHz - better than -80 dB
phase noise @ 1kHz / 2V7 - typical 85 dBc/Hz
phase noise @ 1kHz / 3V6 - typical 88 dBc/Hz
VCP-range #2 - CONSERVATIVE
∆VSNK = 600mV
∆VSRC = 900mV
performance of VPD-range #1
CP current variation below +/-20%
5.6 Threshold Voltages of Schmitt-Trigger Input
Typical Vin Thresholds of 3W-Bus
1,32
1,22
1,12
typ. High min.
typ. Low max.
1,02
0,92
0,82
2,5
3
3,5
4
4,5
5
VCC
Wireless Components
5 - 15
Specification, May 2000