Wireless Components TV Mixer-Oscillator-PLL TUA 6010XS Version 1.0 Specification August 1999 preliminary Revision History: Current Version: 08.99 Previous Version:Data Sheet Page (in previous Version) Page (in current Version) Subjects (major changes since last revision) ABM®, AOP®, ARCOFI®, ARCOFI®-BA, ARCOFI®-SP, DigiTape®, EPIC®-1, EPIC®-S, ELIC®, FALC®54, FALC®56, FALC®-E1, FALC®-LH, IDEC®, IOM®, IOM®-1, IOM®-2, IPAT®-2, ISAC®-P, ISAC®-S, ISAC®-S TE, ISAC®-P TE, ITAC®, IWE®, MUSAC®-A, OCTAT®-P, QUAT®-S, SICAT®, SICOFI®, SICOFI®2, SICOFI®-4, SICOFI®-4µC, SLICOFI® are registered trademarks of Infineon Technologies AG. ACE™, ASM™, ASP™, POTSWIRE™, QuadFALC™, SCOUT™ are trademarks of Infineon Technologies AG. Edition 03.99 Published by Infineon Technologies AG i. Gr., SC, Balanstraße 73, 81541 München © Infineon Technologies AG i. Gr. 24.08.99. All Rights Reserved. Attention please! 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TUA 6010XS preliminary Product Info Product Info General Description Features Application The TUA 6010XS device combines a Package digitally programmable phase locked loop (PLL), with a mixer-oscillator block including two balanced mixers and oscillators for use in TV tuners. ■ PLL with short lock-in time; no asynchronous divider stage ■ Fast I2C bus mode possible ■ 4 programmable chip addresses ■ Short pull-in time for quick channel access and optimized loop stability ■ 3 high-current switch outputs ■ 2 TTL inputs ■ 5-level A/D converter ■ Lock-in flag ■ Power-down flag ■ Few external components ■ Frequency and amplitude-stable balanced oscillator for the VHF, HYPER and UHF frequency range ■ Optimum decoupling of input frequency from oscillator ■ ■ Double balanced mixer with wide dynamic range and low-impedance inputs for the VHF, HYPER and UHF frequency range ■ Internal band switch ■ Internal low-noise reference voltage source ■ Package TSSOP 28 ■ Full ESD protection The IC is suitable for all tuners in TV- and VCR-sets or cable set-top receivers for analog TV an Digital Video Broadcasting. Ordering Information Type Ordering Code Q67007-A5211 TUA 6010 XS Wireless Components Product Info Package P-TSSOP-28-1 Specification, August 1999 1 Table of Contents 1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 2 2.1 2.2 2.3 2.4 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 3 3.1 3.2 3.3 3.4 3.4.1 3.4.2 3.4.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Mixer-Oscillator block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 PLL block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 I2C-Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 4 4.1 4.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 5 5.1 5.1.1 5.1.2 5.1.3 5.2 5.3 5.4 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 Bit Allocation Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 I2C Bus Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 2 Product Description Contents of this Chapter 2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 TUA 6010XS preliminary Product Description 2.1 Overview The TUA 6010XS device combines a digitally programmable phase locked loop (PLL), with a mixer-oscillator block including two balanced mixers and oscillators for use in TV tuners. The PLL block with four hard-switched chip addresses forms a digitally programmable phase locked loop. With a 4 MHz quartz crystal, the PLL permits precise setting of the frequency of the tuner oscillator up to 900 MHz in increments of 62.5 kHz. The tuning process is controlled by a microprocessor via an I2C bus. The device has three output ports, which all can also be used as input ports (two TTL inputs and one A/D converter input). A flag is set when the loop is locked. The input ports and lock flag can be read by the processor via the I2C bus. The mixer-oscillator block includes two balanced mixers (double balanced mixer with low-impedance input), two frequency and amplitude-stable balanced oscillators for VHF, HYPER and UHF, a low-noise reference voltage source and a band switch. 2.2 Features Wireless Components ■ PLL with short lock-in time; no asynchronous divider stage ■ Fast I2C bus mode possible ■ 4 programmable chip addresses ■ Short pull-in time for quick channel access and optimized loop stability ■ 3 high-current switch outputs ■ 2 TTL inputs ■ 5-level A/D converter ■ Lock-in flag ■ Power-down flag ■ Few external components ■ Frequency and amplitude-stable balanced oscillator for the VHF, HYPER and UHF frequency range ■ Optimum decoupling of input frequency from oscillator ■ Double balanced mixer with wide dynamic range and low-impedance inputs for the VHF, HYPER and UHF frequency range ■ Internal band switch ■ Internal low-noise reference voltage source ■ Package TSSOP 28 ■ Full ESD protection 2-2 Specification, August 1999 TUA 6010XS preliminary Product Description 2.3 Application ■ The IC is suitable for all tuners in TV- and VCR-sets or cable set-top receivers for analog TV an Digital Video Broadcasting. 2.4 Package Outlines P-TSSOP-28-1 Wireless Components 2-3 Specification, August 1999 3 Functional Description Contents of this Chapter 3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 3.4 Circuit Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 TUA 6010XS preliminary Functional Description 3.1 Pin Configuration MIXU 1 28 OU-B2 MIXUx 2 27 OU-C1 MIXV 3 26 OU-C2 MIXVx 4 25 OU-B1 VVCCA 5 24 OV-B2 CAS 6 23 OV-C1 IFout 7 22 OV-C2 IFoutx 8 21 OV-B1 GNDD 9 20 GNDA SDA 10 19 TUNE TUA 6010XS SCL 11 18 CHGPMP VVCCD 12 17 P0 / I0 Q 13 16 P1 / I1 QX 14 15 P2 / ADC Pin_config.wmf Figure 3-1 Wireless Components Pin Configuration 3-2 Specification, August 1999 TUA 6010XS preliminary Functional Description 3.2 Pin Definition and Function Table 3-1 Pin Definition and Function Pin No. Symbol Function 1 MIXU UHF mixer input, low-impedance, symmetrical to MIXUx 2 MIXUx UHF mixer input, low-impedance, symmetrical to MIXU 1 3 MIXV 4 MIXVx 2 VHF or HYPER mixer input, low-impedance, symmetrical to MIXVx 3 5 VVCCA 6 CAS 4 VHF or HYPER mixer input, low-impedance, symmetrical to MIXV Positive supply voltage for analog block Chip address select 6 7 IFout 8 IFoutx Inverse open collector mixer output, highimpedance, symmetrical to IFout 9 GNDD Digital Ground Wireless Components 8 Open collector mixer output, high-impedance, symmetrical to IFoutx 7 3-3 Specification, August 1999 TUA 6010XS preliminary Functional Description 10 SDA Data input/output for the I2C bus 10 11 SCL Clock input for the I2C bus 11 12 VVCCD 13 Q Positive supply voltage for digital block (PLL) 13 14 Qx 15 P2/ADC 14 4 MHz low-impedance crystal oscillator input Inverse 4 MHz low-impedance crystal oscillator input Port output / ADC input 15 16 P1/I1 Port output / TTL input 16 Wireless Components 3-4 Specification, August 1999 TUA 6010XS preliminary Functional Description 17 P0/I0 Port output / TTL input 17 18 CHGPMP Charge pump output / loop filter 18 19 19 TUNE VCO tuning voltage output 20 GNDA Analog Ground 21 OV-B1 VHF oscillator amplifier, high-impedance base input, symmetrical to OV-B2 22 OV-C2 VHF oscillator amplifier, high-impedance collector output, symmetrical to OV-C1 23 OV-C1 VHF oscillator amplifier, high-impedance collector output, symmetrical to OV-C2 24 OV-B2 21 22 Wireless Components 23 24 VHF oscillator amplifier, high-impedance base input, symmetrical to OV-B1 3-5 Specification, August 1999 TUA 6010XS preliminary Functional Description 25 OU-B1 26 OU-C2 UHF oscillator amplifier, high-impedance base input, symmetrical to OU-B2 UHF oscillator amplifier, high-impedance collector output, symmetrical to OU-C1 27 OU-C1 UHF oscillator amplifier, high-impedance collector output, symmetrical to OU-C2 28 OU-B2 25 26 27 28 UHF oscillator amplifier, high-impedance base input, symmetrical to OU-B1 Wireless Components 3-6 Specification, August 1999 TUA 6010XS preliminary Functional Description 28 27 26 25 24 23 22 21 20 18 P2/ADC P1/ I1 P0/IO 19 PhaseDet.& ChgPmp Oscillator VHF/HYP Oscillator UHF CHGPMP TUNE GNDA OV-B1 OV-C2 OV-C1 OV-B2 OU-B1 OU-C2 OU-B2 OU-C1 3.3 Block Diagram 17 16 15 I/O-PORTS VCO VCOx Cy I2C-Bus Interface Figure 3-2 Wireless Components 9 GNDD 8 IFoutx 7 IFout 6 CAS 5 VVCCA 4 MIXVx 3 MIXV 2 MIXUx MIXU 1 10 Crystal Oscillator 11 12 13 14 Qx V/U Q Mixer VHF HYP Ref.Divider VVCCD Mixer UHF Progr. Divider SCL Isolation Amplifier SDA Isolation Amplifier fref Block Diagram 3-7 Specification, August 1999 TUA 6010XS preliminary Functional Description 3.4 Circuit Description 3.4.1 Mixer-Oscillator block The mixer oscillator section includes two balanced mixers (double balanced mixer), two balanced oscillators for VHF and/or HYPER and UHF, a reference voltage source and a band switch. Filters between tuner input and IC separate the TV frequency signals into two bands. The band switch ensures that only one mixer-oscillator block at a time is activated. In the activated band the signal passes a frontend stage with MOSFET amplifier, a double-tuned bandpass filter and is then fed to the balanced mixer input of the IC which has a low-impedance input. The input signal is mixed there with the on chip oscillator signal from the activated oscillator section. 3.4.2 PLL block The mixer-oscillator signal VCO/VCOx is internally DC-coupled as a differential signal at the programmable divider inputs. The signal subsequently passes through a programmable divider with ratio N = 256 through 32767 and is then compared in a digital frequency / phase detector to a reference frequency fref = 62.5 kHz. This frequency is derived from a balanced, low-impedance 4 MHz crystal oscillator (pin Q, Qx) divided by Q = 64. The phase detector has two outputs UP and DOWN that drive two current sources I+ and I- of a charge pump. If the negative edge of the divided VCO signal appears prior to the negative edge of the reference signal, the I+ current source pulses for the duration of the phase difference. In the reverse case the I- current source pulses. If the two signals are in phase, the charge pump output (CHGPMP) goes into the high-impedance state (PLL is locked). An active lowpass filter integrates the current pulses to generate the tuning voltage for the VCO (internal amplifier, external pullup resistor at TUNE and external RC circuitry). The charge pump output is also switched into the high-impedance state when the control bit T0 = 1. Here it should be noted, however, that the tuning voltage can alter over a long period in the high-impedance state as a result of self-discharge in the peripheral circuity. TUNE may be switched off by the control bit OS to allow external adjustments. When the VCO is not working the PLL locks to a tuning voltage of 33V. By means of control bit 5I the pump current can be switched between two values by software. This programmability permits alteration of the control response of the PLL in the locked-in state. In this way different VCO gains can be compensated, for example. Wireless Components 3-8 Specification, August 1999 TUA 6010XS preliminary Functional Description The software-switched ports P0, P1, P2 are general-purpose open-collector outputs. The test bit T1 = 1, switches the test signals fref (4 MHz / 64) and Cy (divided input signal) to P0 and P1 respectively. P0, P1, P2 are bidirectional. The lock detector resets the lock flag FL when the width of the charge pump current pulses is greater than the period of the crystal oscillator (i.e. 250 ns). Hence, when FL = 1, the maximum deviation of the input frequency from the programmed frequency is given by ∆f = ± IP (KVCO / fQ) (C1+C2) / (C1C2) where IP is the charge pump current, KVCO the VCO gain, fQ the crystal oscillator frequency and C1, C2 the capacitances in the loop filter (see application circuit). As the charge pump pulses at 62.5 kHz (= f ref), it takes a maximum of 16 µs for FL to be reset after the loop has lost lock state. Once FL has been reset, it is set only if the charge pump pulse width is less than 250 ns for eight consecutive fref periods. Therefore it takes between 128 and 144 µs for FL to be set after the loop regains lock. 3.4.3 I2C-Bus Interface Data is exchanged between the processor and the PLL via the I2C bus. The clock is generated by the processor (input SCL), while pin SDA functions as an input or output depending on the direction of the data (open collector, external pull-up resistor). Both inputs have hysteresis and a low-pass characteristic, which enhance the noise immunity of the I2C bus. The data from the processor pass through an I2C bus controller. Depending on their function the data are subsequently stored in registers. If the bus is free, both lines will be in the marking state (SDA, SCL are HIGH). Each telegram begins with the start condition and ends with the stop condition. Start condition: SDA goes LOW, while SCL remains HIGH. Stop condition: SDA goes HIGH while SCL remains HIGH. All further information transfer takes place during SCL = LOW, and the data is forwarded to the control logic on the positive clock edge. The table 1 ”bit allocation” should be referred to the following description. All telegrams are transmitted byte-by-byte, followed by a ninth clock pulse, during which the control logic returns the SDA line to LOW (acknowledge condition). The first byte is comprised of seven address bits. These are used by the processor to select the PLL from several peripheral components (chip select). The LSB bit (R/W) determines whether data are written into (R/W = 0) or read from (R/W = 1) the PLL. In the data portion of the telegram during a WRITE operation, the MSB bit of the first or third data byte determines whether a divider ratio or control information is to follow. In each case the second byte of the same data type has to follow the first byte. If the address byte indicates a READ operation, the PLL generates an acknowledge and then shifts out the status byte onto the SDA line. If the processor generates an acknowledge, a further status byte is output; otherwise the data line Wireless Components 3-9 Specification, August 1999 TUA 6010XS preliminary Functional Description is released to allow the processor to generate a stop condition. The status word consists of two bits from the TTL input ports, three bits from the A/D converter, the lock flag and the power-on flag. Four different chip addresses can be set by appropriate connection of pin CAS (see table 2 ”address selection”). When the supply voltage is applied, a power-on reset circuit prevents the PLL from setting the SDA line to LOW, which would block the bus. The power-on reset flag POR is set at power-on and when VVCCD goes below 3.2 V. It will be reset at the end of a READ operation. Wireless Components 3 - 10 Specification, August 1999 4 Applications Contents of this Chapter 4.1 Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 TUA 6010XS preliminary Applications 4.1 Application Circuit +33V 4.7n 1k 1k BB639C 4.7n 4.7n 82p 1k 2.2k 2.2k 4.7k 4.7n 470p 33k 3.3k BA 592 4.7p 4.7p 1.2p 28 2.2p BB639C 1.2p 27 100p 1.2p 26 1k 1.2p 25 2.7p 24 2.2p 23 2.2p 22 4.7n 2.7p 21 100k 22k 4.7n 22n 20 19 18 17 16 15 11 12 13 14 TUA 6010XS 1 2 3 4 5 6 7 2.2p 22p 1 9 10 47 1n 22p 3 8 3 1n 4.7n 4MHz 4.7n 100p 220 1:1 *) 6 4 UHF 18p 100p 1 1:1 *) 47p 4 6 VHF 27p 220 4.7n 12p VVCCA CAS IF output SDA SCL V VCCD *) TOKO B4F Type 617DB-1023 Figure 4-1 Wireless Components Evaluation Board 4-2 Specification, August 1999 TUA 6010XS preliminary Applications 4.2 Hints See separate available Application Note TUA 6010XS. Wireless Components 4-3 Specification, August 1999 5 Reference Contents of this Chapter 5.1 5.1.1 5.1.2 5.1.3 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.2 Bit Allocation Read / Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.3 I2C Bus Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.4 Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 TUA 6010XS preliminary Reference 5.1 Electrical Data 5.1.1 Absolute Maximum Ratings WARNING The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result. Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=-20°C ... + 80°C Parameter Symbol Limit Values Unit min max +6 V 1 V mA Remarks PLL Supply voltage VVCCD -0.3 CHGPMP VCHGPMP ICHGPMP -0.3 Crystal oscillator pins Q, Qx VQ IQ VVCCD V mA -5 Bus input/output SDA Bus output current SDA VSDA ISDA(L) -0.3 +6 5 V mA Bus input SCL VSCL -0.3 +6 V Port outputs P0, P1, P2 VP -0.3 +13 V Chip address switch CAS VCAS -0.3 VVCCD V VCO tuning output (loop filter) VTUNE -0.3 +35 V Bus output SDA ISDAL -1 5 mA open collector Port outputs P0, P1, P2 IP(L) -1 15 mA open collector Total port output current ΣIP(L) 20 mA tmax = 0,1 sec. at 6 V Junction temperature TJ +125 °C Storage temperature TStg +125 °C Thermal resistance (junction to ambient) RthSA 130 K/W Wireless Components -40 5-2 Specification, August 1999 TUA 6010XS preliminary Reference Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=-20°C ... + 80°C (continued) Symbol Parameter Limit Values Unit min max -0.3 +6 V -5 2 6 V mA -0.3 3 V VVCCA V 6 V Remarks Mixer-Oscillator Supply voltage VVCCA Mix inputs VHF/UHF VMIX V/U IMIX V/U VCO base voltage VOU-B/OV-B VCO collector voltage VOU-C/OV-C IF output VIFout VIFoutx All values are referred to ground (pin), unless stated otherwise. Currents with a positive sign flows into the pin and currents with a negative sign flows out of pin. ESD-Protection* all pins unless otherwise specified VESD -1 1 kV Mixer inputs MIXU / MIXV VESD MIX -500 500 V Pin 1, 2, 3, 4 Mixer outputs IFout / IFoutx VESD IF -500 500 V Pin 7, 8 Ports VESD P -500 500 V Pin 15, 16, 17 Charge pump VESD CP -500 500 V Pin 18 *according to MIL STD 883D, method 3015.7 and EOS/ESD assn. standard S5.1 - 1993 5.1.2 Operating Range Within the operational range the IC operates as described in the circuit description. The AC / DC characteristic limits are not guaranteed. Table 5-2 Operating Range Parameter Symbol Limit Values min max Unit Supply voltage VVCCD +4.5 +5.5 V Supply voltage VVCCA +4.5 +5.5 V Mixer output voltage VIFout VIFoutx +4.5 +5.5 V Programmable divider factor N 256 32767 VHF Mixer input frequency range fMIXV 30 500 MHz UHF Mixer input frequency range fMIXU 400 900 MHz VHF Oscillator frequency range fOV 30 500 MHz UHF Oscillator frequency range fOU 400 900 MHz Ambient temperature Tamb -20 +80 °C Wireless Components 5-3 Test Conditions L Item open collector Specification, August 1999 TUA 6010XS preliminary Reference 5.1.3 AC/DC Characteristics Table 5-3 AC/DC Characteristics with Tamb 25 °C, VVCCA = 5 V, VVCCD = 5 V Symbol Limit Values min typ Unit Test Conditions L Item max Digital Unit PLL Supply current 1.1 IVCCD 19 24 29 mA VVCCD = 5 V 4.0 4.8 MHz series resonance 100 Ω series resonance MHz fQ = 4 MHz Ω fQ = 4 MHz dB fQ = 4 MHz Crystal oscillator connections Q, Qx Crystal frequency fQ 3.2 Crystal resistance RQ 10 Oscillation frequency fQ 3,99975 4,000 4,00025 Input impedance ZQ -600 -750 -900 Margin from 1st (fundamental) to 2nd and 3rd harmonics aH 20 Charge pump output CHGPMP HIGH output current ICPH ±90 ±220 ±300 µA 5I = 1, VCP = 2 V LOW output current ICPL ±22 ±50 ±75 µA 5I = 0, VCP = 2 V Tristate current ICPZ nA T0 = 1, VCP = 2 V Output voltage VCP 2.5 V locked +1 1.0 Drive output TUNE (open collector) HIGH output current ITH 10 µA VTH = 33 V, T0 = 1 LOW output voltage VTL 0.5 V ITL = 1.0 mA 1.2 I2C-Bus Bus inputs SCL, SDA HIGH input voltage VIH 3 5.5 V LOW input voltage VIL 0 1.5 V HIGH input current IIH 10 µA VIH = VS LOW input current IIL µA VIL = 0 V -10 Bus output SDA (open collector) HIGH output current IOH 10 µA VOH = 5.5 V LOW output voltage VOL 0.4 V IOL = 3 mA Rise time tr 300 ns Fall time tf 300 ns Edge speed SCL,SDA Wireless Components 5-4 Specification, August 1999 TUA 6010XS preliminary Reference Table 5-3 AC/DC Characteristics with Tamb 25 °C, VVCCA = 5 V, VVCCD = 5 V (Continued) Symbol Limit Values min typ Unit Test Conditions L Item max Clock timing SCL Frequency fSCL HIGH pulse width tH 0.6 µs LOW pulse width tL 1.3 µs Set-up time tsusta 0.6 µs Hold time thsta 0.6 µs Set up time tsusto 0.6 µs Bus free tbuf 1.3 µs Set-up time tsudat 0.1 µs Hold time thdat 0 µs Input hysteresis SCL, SDA (1) Vhys Pulse width of spikes which are suppressed tsp Capacitive load for each bus line CL 0 400 kHz Start condition Stop condition Data transfer 200 0 mV 50 ns 400 pF Port outputs P0, P1, P2 (open collector) HIGH output current IPOH 1 µA VPOH = 5 V LOW output voltage VPOL 0.5 V IPOL = 15 mA TTL port inputs P0, P1 HIGH input voltage VPIH 2.7 V LOW input voltage VPIL 0.8 V HIGH input current IPIH 10 µA VPIH = 13.5 V LOW input current IPIL µA VPIL = 0 V -10 ADC port input P2 HIGH input current IADCH LOW input current IADCL 10 µA µA -10 Address selection input CAS HIGH input current ICASH LOW input current ICASL Wireless Components 50 -50 5-5 µA VCASH = 5 V µA VCASL = 0 V Specification, August 1999 TUA 6010XS preliminary Reference Table 5-3 AC/DC Characteristics with Tamb 25 °C, VVCCA = 5 V, VVCCD = 5 V (Continued) Symbol Limit Values min typ Unit Test Conditions L Item max Analog Unit Mixer-Oscillator Current consumption 2.1 IVCCA 11 15 19 mA Bit V/U = Low IVCCA 14 18 22 mA Bit V/U = High Mixer current IIF-V/IF-U 4 6 8 mA Mixer output impedance RIFout,IF outx 20 kΩ Parallel equivalent circuit, fIF = 38,9 MHz CIFout,IF outx 0.5 pF Parallel equivalent circuit, fIF = 38,9 MHz VHF and Hyper Band Section Oscillator frequency range Oscillator drift Oscillator pulling Oscillator phase noise 2.2 fOscV 80 170 MHz Vd = 0,5..28 V; VHF fOscH 140 450 MHz Vd = 0,5..28 V; HYP ∆fOscV 400 kHz VS = 5 V±10% ∆fOscV 500 kHz ∆T = 25 °C ∆fOscV 100 kHz t = 5 s up to 15 min after switching on VMIXV 100 108 dBµV ∆f = 10 kHz in channel E2 VMIXV 100 108 dBµV ∆f = 10 kHz in channel S10 VMIXV 80 88 dBµV ∆fint = E2 + N + 5 1 MHz VMIXV 80 88 dBµV ∆fint = S10 + N + 5 1 MHz L(fm)VH -80 -86 dBc/ Hz fm = 10 kHz, application circuit 11 14 17 dB F Mixer gain GMixV Mixer noise figure FMixV 5 8 dB Channel E2 (DSB) FMixV 5 8 dB Channel 10 (DSB) mVrms max. input level for 10 dB distance fin/LO Crosstalk fin/LO Wireless Components VMixV 150 1000 5-6 Specification, August 1999 TUA 6010XS preliminary Reference Table 5-3 AC/DC Characteristics with Tamb 25 °C, VVCCA = 5 V, VVCCD = 5 V (Continued) Symbol Limit Values min Mixer input impedance IF suppression typ Unit Test Conditions RMixV 20 W serial equivalent circuit, fMixV = 300 MHz LMixV 10 nH serial equivalent circuit, fMixV = 300 MHz aIF 20 dB VMixB = 80 dBµV 2.3 Oscillator frequency range fOscU Oscillator drift Oscillator phase noise 440 900 MHz Vt = 0,5...28 V ∆fOscU 400 kHz VS = 5 V±10% ∆fOscU 800 kHz ∆T = 25 °C ∆fOscU 100 kHz t = 5 s up to 15 min after switching on VMIXU 100 108 dBµV ∆f = 10 kHz in channel E21 VMIXU 100 108 dBµV ∆f = 10 kHz in channel E68 VMIXU 80 88 dBµV ∆fint = E21 + N + 5 1 MHz VMIXU 80 88 dBµV ∆fint = E68 + N + 5 1 MHz L(fm)UH -80 -86 dBc/ Hz fm = 10 kHz, application circuit 11 14 17 dB 6 9 dB Channel E21 (DSB) 7 10 dB Channel E68 (DSB) mVrms max. input level for 10 dB distance fin/LO F Mixer gain GMixU Mixer noise figure FMixU Crosstalk fin/LO VMixU Mixer input impedance RMixU 20 W serial equivalent circuit, fMixU = 600 MHz LMixU 10 nH serial equivalent circuit, fMixU = 600 MHz aIF 20 dB VMixB = 80 dBµV IF suppression Item max UHF Section Oscillator pulling L 150 1000 ■ This value is only guaranteed in lab. Wireless Components 5-7 Specification, August 1999 TUA 6010XS preliminary Reference 5.2 Bit Allocation Read / Write Table 5-4 Byte MSB*) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 LSB Ack Address Byte 1 1 0 0 0 MA1 MA0 0 A Progr. Divider Byte 1 0 n14 n13 n12 n11 n10 n9 n8 A Progr. Divider Byte 2 n7 n6 n5 n4 n3 n2 n1 n0 A Control Byte 1 1 5I T1 T0 1 1 1 OS A Control Byte 2 V/U x x x x P2 P1 P0 A 1 1 0 0 0 MA1 MA0 1 A POR FL x I1 I0 A2 A1 A0 A Remarks Write Data Read Data Address Byte Status Byte *) MSB shifted first. Divider ratio: N = 16384 x n14 + 8192 x n13 + 4096 x n12 + 2048 x n11 + 1024 x n10 + 512 x n9 + 256 x n8 +128 x n7 + 64 x n6 + 32 x n5 + 16 x n4 + 8 x n3 + 4 x n2 + 2 x n1 + n0 Control Bytes: ■ Ports P0, P1, P2: P0...P2=1 P0...P2=0 ■ Bandswitch V/U: V/U=1 V/U=0 ■ high PD output current low PD output current Disabling tuning voltage OS: OS=1 OS=0 Wireless Components switch to OSC/MIX UHF switch to OSC/MIX VHF Pump current 5I: 5I=1 5I=0 ■ open-collector output is active open-collector output is inactive, TTL-inputs I1, I0 and ADC available disables TUNE enables TUNE 5-8 Specification, August 1999 TUA 6010XS preliminary Reference Status Byte: ■ Power On Reset flag POR: flag is set at power-on and reset at the end of READ operation ■ PLL lock flag FL: flag is set to 1 when loop is locked ■ TTL-inputs I1, I0: input data from pins P1/I1, P0/I0 ■ ADC bits A2,A1,A0: digital outputs of the 5-level ADC Table 5-5 Address Selection Voltage at CAS MA1 MA0 (0...0.1) * VVCC 0 0 open circuit 0 1 (0.4...0.6) * VVCC 1 0 (0.9...1) * VVCC 1 1 T1 T0 Normal operation 0 0 P1 = Cy output, P0 = fref output 1 0 Charge pump output, CHGPMP is in high-impedance state 0 1 TTL-inputs I1/I0 are Cy/fref inputs of phase detector 1 1 A2 A1 A0 (0...0.15) * VVCC 0 0 0 (0.15...0.3) * VVCC 0 0 1 (0.3...0.45) * VVCC 0 1 0 (0.45...0.6) * VVCC 0 1 1 (0.6...1) * VVCC 1 0 0 Table 5-6 Test Modes Test mode Table 5-7 A/D Converter Levels Voltage at P2 / ADC Wireless Components 5-9 Specification, August 1999 Wireless Components 5 - 10 SCL MA MA Start-Addr-DR1-DR2-CW1-CW2-Stop Start-Addr-CW1-CW2-DR1-DR2-Stop Start-Addr-DR1-DR2-Stop Start-Addr-CW1-CW2-Stop Telegram examples: Note: SDA Addressing R/W Ack. 1st Byte Start Addr DR1 DR2 CW1 CW2 Stop 2nd Byte Ack. = start condition = address byte = prog. divider byte 1 = prog. divider byte 2 = control byte 1 = control byte 2 = stop condition Ack. 3rd Byte Ack. 4th Byte TUA 6010XS preliminary Reference 5.3 I2C Bus Timing Diagram Specification, August 1999 TUA 6010XS preliminary Reference 5.4 Test Circuits +33V 1n 33k 33k BB639C 4.7n 470n 82p 1k 33k 33k 470p 1n 1k 100p 3.3k BB639C BA 592 39k 2.2p 4.7p 5.6p 1k 100p 12k 10n 100k 1.2p 28 1.2p 27 1.2p 26 1.2p 25 2.2p 24 2.2p 23 2.2p 22 2.2p 21 56n 20 19 18 17 16 15 11 12 13 14 TUA 6010XS 1 2 22p 2 3 22p 4 1n 4 SMT4 1:1 2 5 1 5 6 7 22p 10 1n 4 SMT4 1:1 8 9 22p 10 18p 100p 4.7n 100 100 470n 33p 1 5 1n IF output UHF VHF VVCCA CAS Figure 5-1 Wireless Components SDA SCL V VCCD DC and RF Parameter Measurement 5 - 11 Specification, August 1999 TUA 6010XS preliminary Reference Test mode: VVCC 5V IVCC 5k Q 18 pF 4 MHz fref P0 TUA 6010XS T1 = HIGH T0 = LOW Counter fQ = fref * 64 Counter fVCO = fcy * N N: divider ratio 5k P1 fcy GNDD Figure 5-2 Wireless Components Measurement of Crystal Oscillator Frequency 5 - 12 Specification, August 1999