INFINEON V23815-U1306-M136

Fiber Optics
Parallel Optical Link:
PAROLI ® Tx AC, 1.6 Gbit/s
Parallel Optical Link:
PAROLI ® Rx AC, 1.6 Gbit/s
V23814-U1306-M136
V23815-U1306-M136
Preliminary
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Power supply 3.3 V
Multistandard differential signal electrical interface
12 electrical data channels
Asynchronous, AC-coupled optical link
12 optical data channels
Transmission data rate of up to 1600 Mbit/s per
channel, total link data rate up to 19 Gbit/s
850 nm VCSEL array technology
PIN diode array technology
62.5 µm graded index multimode fiber ribbon
MT based optical port
SMD technology
IEC Class 1M laser safety compliant
GBE mask compliant modules available
Optical Port
• Designed for the Simplex MT Connector (SMC)
• Port outside dimensions: 15.4 mm x 6.8 mm (width x height)
• MT compatible (IEC 61754-5) fiber spacing (250 µm) and
alignment pin spacing (4600 µm)
• Alignment pins fixed in module port
• Integrated mechanical keying
• Process plug (SMC dimensions) included with every module
PAROLI ® is a registered trademark of Infineon Technologies AG
Data Sheet
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Applications
Features of the Simplex MT Connector (SMC)
(as part of optional PAROLI fiber optic cables)
•
•
•
•
•
Uses standardized MT ferrule (IEC 61754-5)
MT compatible fiber spacing (250 µm) and alignment pin spacing (4600 µm)
Snap-in mechanism
Ferrule bearing spring loaded
Integrated mechanical keying
Applications
Telecommunication
• Switching equipment
• Access network
Data Communication
• Interframe (rack-to-rack)
• Intraframe (board-to-board)
• On board (optical backplane)
Data Sheet
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Pin Configuration
Pin Configuration
The numbering conventions for the Tx and Rx modules are the same.
Numbering Conventions Transmitter/Receiver
Figure 1
Pin Description Transmitter
Pin
No.
Symbol
1
VCC
Power supply voltage of laser driver
2
t.b.l.o.
to be left open
3
t.b.l.o.
to be left open
4
t.b.l.o.
to be left open
5
t.b.l.o.
to be left open
6
LCU
7
Ground
8
VEE
VIN
9
t.b.l.o.
to be left open
10
t.b.l.o.
to be left open
11
VEE
VEE
Ground
12
Data Sheet
Level/Logic
Description
LVCMOS Out Laser Controller Up.
High = normal operation.
Low = laser fault or –RESET low.
Input VIN rail.
CML: VIN = Reference supply (e.g. VCC).
LVPECL, LVDS: VIN = VEE.
Ground
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Pin Configuration
Pin Description Transmitter (cont’d)
Pin
No.
Symbol
Level/Logic
Description
13
DI01N
Data In
Data Input #1, inverted
14
DI01P
Data In
Data Input #1, non-inverted
15
16
VEE
VEE
17
DI02N
Data In
Data Input #2, inverted
18
DI02P
Data In
Data Input #2, non-inverted
19
20
VEE
VEE
21
DI03N
Data In
Data Input #3, inverted
22
DI03P
Data In
Data Input #3, non-inverted
23
Ground
24
VEE
VEE
25
t.b.l.o.
to be left open
26
DI04N
Data In
Data Input #4, inverted
27
DI04P
Data In
Data Input #4, non-inverted
28
VEE
29
DI05N
Data In
Data Input #5, inverted
30
DI05P
Data In
Data Input #5, non-inverted
31
32
VEE
VEE
33
DI06N
Data In
Data Input #6, inverted
34
DI06P
Data In
Data Input #6, non-inverted
35
36
VEE
VEE
37
DI07N
Data In
Data Input #7, inverted
38
DI07P
Data In
Data Input #7, non-inverted
39
40
VEE
VEE
41
DI08N
Data In
Data Input #8, inverted
42
DI08P
Data In
Data Input #8, non-inverted
Data Sheet
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
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Pin Configuration
Pin Description Transmitter (cont’d)
Pin
No.
Symbol
43
45
VEE
VEE
VEE
46
DI09N
Data In
Data Input #9, inverted
47
DI09P
Data In
Data Input #9, non-inverted
48
t.b.l.o.
to be left open
49
Ground
50
VEE
VEE
51
DI10N
Data In
Data Input #10, inverted
52
DI10P
Data In
Data Input #10, non-inverted
53
54
VEE
VEE
55
DI11N
Data In
Data Input #11, inverted
56
DI11P
Data In
Data Input #11, non-inverted
57
58
VEE
VEE
59
DI12N
Data In
Data Input #12, inverted
60
DI12P
Data In
Data Input #12, non-inverted
61
Ground
62
VEE
VIN
63
t.b.l.o.
to be left open
64
–RESET LVCMOS In
High = laser diode array is active.
Low = switches laser diode array off.
This input has an internal pull-down to ensure laser
safety switch off in case of unconnected –RESET
input.
65
VEE
VEE
Ground
44
66
Data Sheet
Level/Logic
Description
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Input VIN rail.
CML: VIN = Reference supply (e.g. VCC).
LVPECL, LVDS: VIN = VEE.
Ground
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Pin Configuration
Pin Description Transmitter (cont’d)
Pin
No.
Symbol
Level/Logic
Description
67
LE
LVCMOS In
Laser ENABLE. High active.
High = laser array is on if –LE is also active.
Low = laser array is off. This input has an internal
pull-up, therefore can be left open.
68
–LE
Laser ENABLE. Low active.
Low = laser array is on if LE is also active. This input
has an internal pull-down, therefore can be left open.
69
t.b.l.o.
to be left open
70
t.b.l.o.
to be left open
71
t.b.l.o.
to be left open
72
VCC
Power supply voltage of laser driver
Data Sheet
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Pin Configuration
Pin Description Receiver
Pin
No.
Symbol
1
Ground
2
VEE
VCC
3
VCC
Power supply voltage of preamplifier and analog
circuitry
4
t.b.l.o.
to be left open
5
OEN
LVCMOS In
6
SD1
LVCMOS Out Signal Detect on fiber #1.
High = signal of sufficient AC power is present on
fiber #1.
Low = signal on fiber #1 is insufficient.
7
Power supply voltage of output stages
8
VCCO
VEE
9
t.b.l.o.
to be left open
10
Ground
12
VEE
VEE
VEE
13
DO01P
LVDS Out
Data Output #1, non-inverted
14
DO01N
LVDS Out
Data Output #1, inverted
15
16
VEE
VEE
17
DO02P
LVDS Out
Data Output #2, non-inverted
18
DO02N
LVDS Out
Data Output #2, inverted
19
20
VEE
VEE
21
DO03P
LVDS Out
Data Output #3, non-inverted
22
DO03N
LVDS Out
Data Output #3, inverted
23
VEE
11
Data Sheet
Level/Logic
Description
Power supply voltage of preamplifier and analog
circuitry
Output Enable.
High = normal operation.
Low = sets all Data Outputs to low.
This input has an internal pull-up which pulls to high
level when this input is left open.
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
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Pin Configuration
Pin Description Receiver (cont’d)
Pin
No.
Symbol
24
VEE
Ground
25
t.b.l.o.
to be left open
26
DO04P
LVDS Out
Data Output #4, non-inverted
27
DO04N
LVDS Out
Data Output #4, inverted
28
VEE
29
DO05P
LVDS Out
Data Output #5, non-inverted
30
DO05N
LVDS Out
Data Output #5, inverted
31
32
VEE
VEE
33
DO06P
LVDS Out
Data Output #6, non-inverted
34
DO06N
LVDS Out
Data Output #6, inverted
35
36
VEE
VEE
37
DO07P
LVDS Out
Data Output #7, non-inverted
38
DO07N
LVDS Out
Data Output #7, inverted
39
40
VEE
VEE
41
DO08P
LVDS Out
Data Output #8, non-inverted
42
DO08N
LVDS Out
Data Output #8, inverted
43
45
VEE
VEE
VEE
46
DO09P
LVDS Out
Data Output #9, non-inverted
47
DO09N
LVDS Out
Data Output #9, inverted
48
t.b.l.o.
to be left open
49
Ground
50
VEE
VEE
51
DO10P
LVDS Out
Data Output #10, non-inverted
52
DO10N
LVDS Out
Data Output #10, inverted
53
VEE
44
Data Sheet
Level/Logic
Description
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
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Pin Configuration
Pin Description Receiver (cont’d)
Pin
No.
Symbol
54
VEE
55
DO11P
LVDS Out
Data Output #11, non-inverted
56
DO11N
LVDS Out
Data Output #11, inverted
57
58
VEE
VEE
59
DO12P
LVDS Out
Data Output #12, non-inverted
60
DO12N
LVDS Out
Data Output #12, inverted
61
Ground
63
VEE
VEE
VEE
64
t.b.l.o.
to be left open
65
Ground
66
VEE
VCCO
67
–SD12
LVCMOS Out Signal Detect on fiber #12.
low active
Low = signal of sufficient AC power is present on
fiber #12.
High = signal on fiber #12 is insufficient.
68
ENSD
LVCMOS In
69
t.b.l.o.
to be left open
70
VCC
Power supply voltage of preamplifier and analog
circuitry
71
VCC
Power supply voltage of preamplifier and analog
circuitry
72
VEE
Ground
62
Data Sheet
Level/Logic
Description
Ground
Ground
Ground
Ground
Ground
Power supply voltage of output stages
Enable Signal Detect.
High = SD1 and SD12 function enabled.
Low = SD1 and SD12 are set to permanent active.
This input has an internal pull-up which pulls to high
level when this input is left open.
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Description
Description
PAROLI is a parallel optical link for high-speed data transmission. A complete PAROLI
system consists of a transmitter module, a 12-channel fiber optic cable, and a receiver
module. The transmitter supports LVDS, CML and LVPECL differential signals. The
receiver module is described for the LVDS electrical output only. A specification for
Infineon’s adjustable CML output can be provided separately.
Transmitter V23814-U1306-M136
The transmitter module converts parallel electrical input signals via a laser driver and a
Vertical Cavity Surface Emitting Laser (VCSEL) diode array into parallel optical output
signals. All input data signals are Multistandard Differential Signals (LVDS compatible;
they also support LVPECL and CML because of the wide common input range). The
electrical interface (LVDS, LVPECL or CML) is selected by the supply inputs VIN. The
data rate is up to 1600 Mbit/s for each channel. The transmitter module’s min. data rate
of 500 Mbit/s is specified for the CID1) worst case pattern (disparity 72) or any pattern with
a lower disparity.
A logic low level at –RESET switches all laser outputs off. During power-up –RESET
must be used as a power-on reset which disables the laser driver and laser control until
the power supply has reached a 3.135 V level.
The Laser Controller Up (LCU) output is low if a laser fault is detected or –RESET is
forced to low.
All non data signals have LVCMOS levels.
Transmission delay of the PAROLI system is ˆ 1 ns for the transmitter, ˆ 1 ns for the
receiver and approximately 5 ns per meter for the fiber optic cable.
Optical
Output
LE -LE laser enable
Electrical
Input
12
Data In
12
Input
Stage
Laser
Driver
12
Laser
Diode
Array
12
Data
Laser
Control
VIN
Figure 2
1)
Laser Controller
Up (LCU)
-RESET
Transmitter Block Diagram
Consecutive Identical Digit (CID) immunity test pattern for STM-N signals,
ITU-T recommendation G.957 sec. II.
Data Sheet
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Description
Receiver V23815-U1306-M136
The PAROLI receiver module converts parallel optical input signals into parallel electrical
output signals. The optical signals received are converted into voltage signals by PIN
diodes, transimpedance amplifiers, and gain amplifiers. There are two different modules
available for LVDS and Infineon’s adjustable CML output. This description only refers to
a module with LVDS output. A module description for CML output can be provided
separately.
The data rate is up to 1600 Mbit/s for each channel. The receiver module’s min. data rate
of 500 Mbit/s is specified for the CID1) worst case pattern (disparity 72) or any pattern with
a lower disparity.
Additional Signal Detect outputs (SD1 active high / SD12 active low) show whether an
optical AC input signal is present at data input 1 and/or 12. The signal detect circuit can
be disabled with a logic low at ENSD. The disabled signal detect circuit will permanently
generate an active level at Signal Detect outputs, even if there is insufficient signal input.
This could be used for test purposes.
A logic low at LVDS Output Enable (OEN) sets all data outputs to logic low. SD outputs
will not be effected.
All non data signals have LVCMOS levels. Transmission delay of the PAROLI system is
at a maximum 1 ns for the transmitter, 1 ns for the receiver and approximately 5 ns per
meter for the fiber optic cable.
Optical
Input
Electrical
Output
12
12
Data
Pin
Diode
Array
Gain
Amplifier
Amplifier
12
LVDS
Output
Stage
12
Signal
Detect
Circuit
ENSD
Figure 3
1)
Data out
SD1
-SD12
Output Enable (OEN)
Receiver Block Diagram
Consecutive Identical Digit (CID) immunity test pattern for STM-N signals,
ITU-T recommendation G.957 sec. II.
Data Sheet
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Laser Safety
Laser Safety
The transmitter of the AC coupled Parallel Optical Link (PAROLI) is an IEC 60825-1
Amend. 2 Class 1M laser product. It complies with FDA performance standards (21 CFR
1040.10 and 1040.11) for laser products except for deviations pursuant to Laser Notice
No. 50, dated July 26, 2001. To avoid possible exposure to hazardous levels of invisible
laser radiation, do not exceed maximum ratings.
The PAROLI module must be operated under the specified operating conditions (the
supply voltage range can be adjusted between 3.0 V and 3.6 V) under any
circumstances to ensure laser safety.
Class 1M Laser Product
Attention: Invisible laser radiation. Do not view directly with optical instruments.
Note: Any modification of the module will be considered an act of “manufacturing”, and will
require, under law, recertification of the product under FDA (21 CFR 1040.10 (i)).
Laser aperture
and beam
Figure 4
Laser Emission
Laser Safety Design Considerations
To ensure laser safety for all input data patterns each channel is controlled internally and
will be switched off if the laser safety limits are exceeded.
A channel alerter switches the respective data channel output off if the input duty cycle
permanently exceeds 57%. The alerter will not disable the channel below an input duty
cycle of 57% under all circumstances.
The minimum alerter response time is 1 µs with a constant high input, i.e. in the input
pattern the time interval of excessive high input (e.g. ’1’s in excess of a 57% duty cycle,
consecutive or non-consecutive) must not exceed 1 µs, otherwise the respective channel
will be switched off. The alerter switches the respective channel from off to on without
the need of resetting the module if the input duty cycle is no longer violated.
All of the channel alerters operate independently, i.e. an alert within a channel does not
affect the other channels. To decrease the power consumption of the module unused
channel inputs can be tied to high input level. In this way a portion of the supply current
in this channel is triggered to shut down by the corresponding alerter.
Data Sheet
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Technical Data
Technical Data
Stress beyond the values stated below may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods of time may affect
device reliability.
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
min.
max.
–0.3
4.5
V
–0.5
VCC+0.5
V
2.0
V
0
80
°C
–20
100
°C
Operating Moisture
20
85
%
Storage Moisture
20
85
%
1
kV
VCC–VEE
VIN
|VID|
TCASE
TSTG
Supply Voltage
Data/Control Input Levels 1)
Data Input Differential Voltage 2)
Operating Case Temperature 3)
Storage Ambient Temperature
ESD Resistance
(all pins to VEE, human body model) 4)
1)
2)
3)
4)
At Data and LVCMOS inputs.
|VID| = |(input voltage of non-inverted input minus input voltage of inverted input)|.
Measured at case temperature reference point (see Package Outlines Figure 15).
To avoid electrostatic damage, handling cautions similar to those used for MOS devices must be observed.
Data Sheet
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Technical Data
Recommended Operating Conditions
Parameter
Symbol
Limit Values
Unit
min.
max.
VCC
NPS1
NPS2
VDATAI
|VID|
tSPN
tR , tF
VLVCMOSIH
VLVCMOSIL
tR , tF
3.135
3.6
V
50
mV
100
mV
500
VCC
mV
80
1000
mV
VCC
NPS1
NPS2
Rt
3.0
Transmitter
Power Supply Voltage
Noise on Power Supply 1)
Noise on Power Supply 2)
Data Input Voltage Range 3), 4)
Data Input Differential Voltage 4), 5)
Data Input Skew 6)
Data Input Rise/Fall Time 7)
LVCMOS Input High Voltage
LVCMOS Input Low Voltage
LVCMOS Input Rise/Fall Time
8)
0.5 x tR, tF ps
50
300
ps
2.0
VCC
V
VEE
0.8
V
20
ns
3.6
V
50
mV
100
mV
120
W
VCC
V
0.8
V
20
ns
320
ps
Receiver
Power Supply Voltage
Noise on Power Supply 1)
Noise on Power Supply 2)
Differential LVDS
Termination Impedance
80
Optical Input Rise/Fall Time 9)
VLVCMOSIH 2.0
VLVCMOSIL VEE
tR , tF
tR , tF
Input Extinction Ratio
ER
6.0
Input Center Wavelength
lC
830
LVCMOS Input High Voltage
LVCMOS Input Low Voltage
LVCMOS Input Rise/Fall Time 8)
dB
860
nm
Voltages refer to VEE = 0 V.
1)
2)
3)
4)
5)
6)
7)
8)
9)
Noise frequency is 1 kHz to 10 MHz. Voltage is peak-to-peak value.
Noise frequency is > 10 MHz. Voltage is peak-to-peak value.
This implies that the input stage can be AC coupled.
Input level diagram: see Figure 5.
|VID| = |(input voltage of non-inverted input minus input voltage of inverted input)|.
Skew between positive and negative inputs measured at 50% level.
20% - 80% level.
Measured between 0.8 V and 2.0 V.
20% - 80% level. Non filtered values.
Data Sheet
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Technical Data
mV
VCC
|VID|
500
Time
Figure 5
Input Level Diagram
Transmitter Module
VCC
Data In P
internal P
Rin/2
Rin/2
Data In N
V
internal N
IN
>6 K
1.95 V
Figure 6
Data Sheet
Input Stage
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Technical Data
The electro-optical characteristics described in the following tables are valid only for use
under the recommended operating conditions.
Transmitter Electrical Characteristics
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Supply Current
ICC
350
450
mA
Power Consumption
P
1.2
1.6
W
Data Rate per Channel
DR
1600
Mbit/s
LVCMOS Output Voltage Low
VLVCMOSOL
VLVCMOSOH 2.5
ILVCMOSI –500
0.4
V
LVCMOS Output Voltage High
LVCMOS Input Current
High/Low
500 1)
LVCMOS Output Current High 2) ILVCMOSOH
LVCMOS Output Current Low 3)
Data Differential Input
Impedance 4)
Data Input Differential Current
1)
2)
3)
4)
V
500
µA
0.5
mA
ILVCMOSOL
RIN
80
4.0
mA
120
W
|II|
5.5
mA
Specified for CID worst case pattern (disparity 72) or any pattern with a smaller disparity.
Source current.
Sink current.
Data input stage.
Data Sheet
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Technical Data
Transmitter Electro-Optical Characteristics
Parameter
Symbol
Limit Values
min.
typ.
Unit
max.
Launched Power Shutdown
tR
tF
JT
JD
tCSK
PAVG
PSD
Center Wavelength
lC
Spectral Width (FWHM)
Dl
2
nm
Spectral Width (rms)
Dl
0.85
nm
Relative Intensity Noise
RIN
–117
dB/Hz
Extinction Ratio (dynamic)
ER
6.0
Optical Modulation Amplitude 4)
OMA
0.15 5)
Optical Rise Time
Optical Fall Time
1)
1)
Total Jitter 2)
Deterministic Jitter
Channel-to-channel skew 3)
Launched Average Power
–9.0
–5.0
830
200
ps
200
ps
0.284
UI
0.1
UI
100
ps
–3.0
dBm
–30.0
dBm
860
nm
dB
0.46 6)
mW
to be defined 7)
Eye mask compliance
Optical parameters valid for each channel.
1)
2)
3)
4)
5)
6)
7)
20% - 80% level, non filtered values.
Measured using a filter as defined in IEEE 802.3 (2000-edition) Gigabit Ethernet specification, section 38.6.5.
With input channel-to-channel skew 0 ps and a maximum data channel-to-channel average deviation and
swing deviation of 5%.
Peak to peak values.
Corresponds to a minimum extinction ratio of 6 dB.
Corresponds to a typical extinction ratio of 8 dB.
GBE mask (IEEE 802.3, sec. 38.6.5.) adopted for data rate available.
Data Sheet
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Technical Data
VCC
-RESET
3.6 V
3.135 V
2.0 V
0.8 V
t3
Data
data valid
data invalid
t2
t1
Figure 7
Timing Diagram
Parameter
Symbol
Limit Values
min.
t1
t2
t3
–RESET on Delay Time
–RESET off Delay Time
–RESET Low Duration 1)
1)
Unit
max.
100
ms
50
µs
10
µs
Only when not used as power on reset. At any failure recovery, –RESET must be brought to low level for at
least t3.
Receiver Electrical Characteristics
Parameter
Symbol
Limit Values
min.
typ.
max.
Unit
Supply Current
ICC
250
350
mA
Power Consumption
P
0.8
1.3
W
LVDS Output Low Voltage 1), 2)
VLVDSOL
VLVDSOH
|VOD|
LVDS Output High Voltage 1), 2)
LVDS Output Differential
Voltage 1), 2), 3)
925
LVDS Output Offset Voltage 1), 2), 4) VOS
LVDS Rise/Fall Time 5)
LVCMOS Output Voltage Low
LVCMOS Output Voltage High
Data Sheet
1475
mV
250
400
mV
1125
1275
mV
400
ps
400
mV
tR , tF
VLVCMOSOL
VLVCMOSOH 2500
18
mV
mV
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V23814-U1306-M136
V23815-U1306-M136
Technical Data
Receiver Electrical Characteristics (cont’d)
Parameter
Symbol
Limit Values
min.
LVCMOS Input Current High/Low ILVCMOSI
LVCMOS Output Current High 6)
LVCMOS Output Current Low 7)
Total Jitter 8), 9)
Deterministic Jitter 8)
Channel-to-channel skew 10)
1)
2)
3)
4)
5)
6)
7)
8)
9)
10)
typ.
–500
ILVCMOSOH
ILVCMOSOL
JT
JD
tCSK
Unit
max.
500
µA
0.5
mA
4.0
mA
0.39
UI
0.12
UI
100
ps
Output level diagram: see Figure 8.
LVDS output must be terminated differentially with Rt.
|VOD| = |(output voltage of non-inverted output minus output voltage of inverted output)|.
VOS = 1/2 (output voltage of inverted output + output voltage of non-inverted output).
Measured between 20% and 80% level with a maximum capacitive load of 5 pF.
Source current.
Sink current.
With no optical input jitter.
At sensitivity limit of 0.032 mW OMA.
With input channel-to-channel skew 0 ps.
mV
1475
|VOD|
925
Time
Figure 8
Output Level Diagram
.
Data Sheet
19
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V23815-U1306-M136
Technical Data
Receiver Electro-Optical Characteristics
Parameter
Symbol
Limit Values
Unit
min.
max.
500 1)
1600
Mbit/s
–18.0
dBm
Data Rate per Channel
DR
Sensitivity (Average Power) 2)
PIN
Optical Modulation Amplitude 3)
OMA
0.032 4)
mW
Saturation (Average Power)
PSAT
PSDA
PSDD
PSDA
–PSDD
ARL
–3.0
dBm
Signal Detect Assert Level 5)
Signal Detect Deassert Level 5)
Signal Detect Hysteresis 5)
Return Loss of Receiver
–19.0
–29.0
1.0
12
dBm
dBm
4.0
dB
dB
Optical parameters valid for each channel.
1)
2)
3)
4)
5)
Specified for CID worst case pattern (disparity 72) or any pattern with a smaller disparity.
BER = 10–12, Extinction ratio = infinite, Specified for CID worst case pattern (disparity 72) or any pattern with a
smaller disparity.
Peak to peak value.
Corresponds to a maximum sensitivity (average power) of –18.0 dBm at an infinite extinction ratio.
Extinction ratio = infinite,
PSDA: Average optical power when SD switches from inactive to active.
PSDD: Average optical power when SD switches from active to inactive.
Data Sheet
20
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Technical Data
Data Out 1, 12
t2
t1
Signal Detect 1
Signal Detect 12
Output Enable OEN
Data Out
2.0 V
0.8 V
data valid
t3
Figure 9
data valid
data Low
t4
Timing Diagrams
Parameter
Symbol
Max.
Unit
Signal Detect Deassert Time
t1
t2
t3
t4
10
µs
10
µs
20
ns
20
ns
Signal Detect Assert Time
LVDS Output Enable off Delay Time
LVDS Output Enable on Delay Time
Data Sheet
21
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V23815-U1306-M136
Assembly
Assembly
On the next pages are some figures to assist the customer in designing his printed circuit
board (PCB). Figure 10 shows the mechanical dimensions of the PAROLI transmitter
and receiver modules and Figure 11 to Figure 13 give the dimensions of the holes and
solder pads on a customer PCB that are necessary to mount the modules on this PCB.
Keeping the tolerances for the PCB given in Figure 11 to Figure 13 is required to
properly attach the PAROLI transmitter and receiver module to the PCB.
Attachment to the customer PCB should be done with four M2 screws torqued to
0.25 Nm +0.05 Nm (see Figure 10, cross section B-B). The screw length a should be 3
to 4 mm plus the thickness b of the customer PCB.
Special care must be taken to remove residues from the soldering and washing process
which can impact the mechanical function. Avoid the use of aggressive organic solvents
like ketones, ethers, etc. Consult the supplier of the PAROLI modules and the supplier
of the solder paste and flux for recommended cleaning solvents.
The following common cleaning solvents will not affect the module: deionized water,
ethanol, and isopropyl alcohol. Air-drying is recommended to a maximum temperature
of 150°C. Do not use ultrasonics.
During soldering, heat must be applied to the leads only, to ensure that the case
temperature never exceeds 150°C. The module must be mounted with a hot-air or hotbar soldering process using a SnPb solder type, e.g. Sn62Pb36Ag2, in accordance with
ISO 9435.
Data Sheet
22
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V23815-U1306-M136
Assembly
Dimensions in [mm] inches
Figure 10
Data Sheet
Drawing of the PAROLI Transmitter and Receiver Module
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V23815-U1306-M136
Assembly
Dimensions in [mm] inches
Figure 11
Data Sheet
Recommended Circuit Board Layout: Transmitter
24
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V23814-U1306-M136
V23815-U1306-M136
Assembly
Dimensions in [mm] inches
Figure 12
Recommended Circuit Board Layout: Receiver
No electronic components are allowed on the customer PCB within the area covered by
the PAROLI module and the jumper used to attach a ribbon fiber cable.
Data Sheet
25
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V23814-U1306-M136
V23815-U1306-M136
Assembly
Dimensions in [mm] inches
Figure 13
Data Sheet
Mounting Hole, Detail Y (see Figure 11 and Figure 12)
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V23815-U1306-M136
Assembly
CML, LVDS or LVPECL
SMC
Port
Link
Controller
PAROLI Tx module
Ribbon
Cables
PAROLI Rx module
Board-to-Board
Passive Optical
Backplane
PAROLI
Tx
Rx
Optical
Feed Through
I/O Board
Backplane
PAROLI
SMC
Port
SMC
Port
Tx module
Rx module
Ribbon Cable
CML,
LVDS or
LVPECL
CML,
LVDS or
LVPECL
Point-to-Point
Figure 14
Data Sheet
Applications
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Package Outlines
Package Outlines
Dimensions in [mm] inches
Figure 15
Data Sheet
28
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V23815-U1306-M136
Revision History:
2002-05-14
Previous Version:
2001-12-01
Page
Subjects (major changes since last revision)
12
Class 1 Laser Product changed to Class 1M Laser Product;
Caution: ... added
DS1
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com.
Edition 2002-05-14
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
D-81541 München, Germany
© Infineon Technologies AG 2002.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as warranted
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life-support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.