V23814-U1306-M130 Parallel Optical Link: PAROLI Tx AC, 1.6 Gbit/s V23815-U1306-M130 Parallel Optical Link: PAROLI Rx AC, 1.6 Gbit/s Preliminary Dimensions in (mm) inches A (58.1) 2.287 A—A (1.5) .059 Reference point for case temperature measurement (center of fin width) (1.5) .059 (.13) (6.8) .268 .005 (∅1.3 max) ∅.051 max (13.5) 0.531 (7.5) .295 (∅3) ∅.118 (0.27) 4xM2 .011 (7) .276 (33.89) 1.334 (22.7) .894 A (14) .551 (12.73) .501 (1.2) .047 (∅2.5) ∅.098 (14.9) .587 (1.0) .039 (17.9) .705 APPLICATIONS Telecommunication • Switching equipment • Access network Data Communication • • • • Interframe (rack-to-rack) Intraframe (board-to-board) On board (optical backplane) Interface to SCI and HIPPI 6400 standards Absolute Maximum Ratings FEATURES • Power supply 3.3 V • Low voltage differential signal electrical interface (LVDS) • 12 electrical data channels • Asynchronous, AC-coupled optical link • 12 optical data channels • Transmission data rate of 250-1600 Mbit/s per channel, total link data rate up to 19 Gbit/s • Transmission distance up to 200m • Transmitter: 840 nm VCSEL (Vertical Cavity Surface Emitting Laser) technology • Receiver: 840 nm PIN diode array • Fiber ribbon: 62.5 µm graded index multimode fiber • MT based optical port • SMD technology • Transmitter: Class 1 FDA and Class 3A IEC laser safety compliant Fiber Optics Stress beyond the values stated below may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Supply Voltage (VCC–VEE).................................... –0.3 V to 4.5 V Data/Control Input Levels (VIN)(1) ................ –0.5 V to VCC+0.5 V LVDS Input Differential Voltage (|VID|)(2) .............................. 2.0 V Operating Case Temperature (TCASE)(3) ............... 0°C to 80°C Storage Ambient Temperature (TSTG)................ –20°C to 100°C Operating Moisture ............................................... 20% to 85% Storage Moisture.................................................... 20% to 85% Soldering Conditions Temp/Time (TSOLD, tSOLD)(4) ....260°C/10s ESD Resistance (all pins to V EE, human body model)(5) ...... 1 kV Notes 1. At LVDS and LVCMOS inputs. 2. |VID|=|(input voltage of non-inverted input minus input voltage of inverted input)|. 3. Measured at case temperature reference point (see dimensional drawing). 4. Hot bar soldering. 5. To avoid electrostatic damage the handling precautions as for MOS devices must be taken into account. SEPTEMBER 1999 DESCRIPTION Laser Emission PAROLI is a parallel optical link for high-speed data transmission. A complete PAROLI system consists of a transmitter module, a 12-channel fiber optic cable, and a receiver module. Indication of laser aperture and beam Transmitter V23814-U1306-M130 The transmitter module converts parallel electrical input signals via a laser driver and a Vertical Cavity Surface Emitting Laser (VCSEL) diode array into parallel optical output signals. All input data signals are Low Voltage Differential Signals (LVDS). The data rate is 250-1600 Mbit/s for each channel. Electrical input data should be DC balanced within 144 bits. The maximum time interval of consecutive 0’s and 1’s (run length) should not exceed 72 bits. This will ensure that the output jitter values given for the transmitter and receiver in this data sheet will be met. Otherwise, jitter values will be exceeded. A logic low level at -RESET switches all laser outputs off. During power-up -RESET must be used as a power-on reset which disables the laser driver and laser control until the power supply has reached a 3 V level. An additional Laser Active output is low if a laser fault is detected or -RESET is forced to low. All nondata signals have LVCMOS levels. Transmission delay of the PAROLI system is at a maximum 1 ns for the transmitter, 1 ns for the receiver and approximately 5 ns per meter for the fiber optic cable. Laser safety design considerations To ensure laser safety for all input data patterns each channel is controlled internally and will be switched off if the laser safety limits are exceeded. An internal control unit switches the respective data channel output off if the input duty cycle permanently exceeds 57%. The alerter will not disable the channel below an input duty cycle of 57% under all circumstances. The minimum alerter response time is 1 µs with a constant high input, i.e. in the input pattern the time interval of excessive high input (e.g. ’1’s in excess of a 57% duty cycle, consecutive or non-consecutive) must not exceed 1 µs, otherwise the resptive channel will be switched off. The alerter switches the respective channel from off to on without the need of resetting the module. All of the channel alerters operate independently, i.e. an alert within a channel does not affect the other channels. To decrease the power consumption of the module unused channel inputs can be tied to high input level. In this way a portion of the supply current in this channel is triggered to shut down by the corresponding alerter. Figure 1. Transmitter block diagram LE -LE laser enable Electrical Input Data In 12 12 LVDS Input Stage Laser Driver 12 Optical Output Laser Diode Array TECHNICAL DATA The electro-optical characteristics described in the following tables are valid only for use under the recommended operating conditions. 12 Data Laser Control -RESET Recommended Operating Conditions Laser Active LASER SAFETY The transmitter of the AC coupled Parallel Optical Link (PAROLI) is an FDA Class 1 laser product. It complies with FDA regulations 21 CFR 1040.10 and 1040.11. The transmitter is also an IEC Class 3A laser product as defined by IEC 825-1.To avoid possible exposure to hazardous levels of invisible laser radiation, do not exceed maximum ratings. The PAROLI module must be operated under the specified operating conditions (supply voltage between 3.0 V and 3.6 V, case temperature between 0°C and 80°C) under any circumstances to ensure laser safety. Parameter Symbol Min. Power Supply Voltage VCC 3.0 Noise on Power Supply(1) NPS1 Noise on Power Supply(2) NPS2 LVDS Input Voltage Range(6) VLVDSI 500 1900 LVDS Input Differential Voltage(3, 6) |VID| 100 1000 LVDS Input Skew(4) tSPN LVDS Input Rise/Fall Time(5) LVCMOS Input High Voltage tR, tF 3.6 V mV 100 50 100 300 VCC tR, tF Units 10 VLVCMOSIH 2.0 LVCMOS Input Low Voltage VLVCMOSIL LVCMOS Input Rise/Fall Time(7) Max. VEE ps V 0.8 20 ns Caution Do not stare into beam or view directly with optical instruments. The use of optical instruments with this product may lead to eye hazard. 1. Noise frequency is 1 kHz to 1 MHz. Voltage is peak-to-peak value. Note 2. Noise frequency is 1 MHz to 1 GHz. Voltage is peak-to-peak value. Notes Voltages refer to VEE=0 V. 3. |VID|=|(input voltage of non-inverted input minus input voltage of inverted input)|. Any modification of the module will be considered an act of “manufacturing,” and will require, under law, recertification of the product under FDA (21 CFR 1040.10 (i)). 4. Skew between positive and negative inputs measured at 50% level. 5. 20%–80% level. Fiber Optics V23814/15-U1306-M130 Parallel Optical Link: PAROLI Tx/Rx AC, 1.6 Gbit/s 2 6. Level diagram: mV 1900 |VID| 500 Time 7. Measured between 0.8 V and 2.0 V. Symbol Supply Current lCC Power Consumption P Data Rate per Channel(1) DR PAVG Launched Power Shutdown PSD Center Wavelength λC –11.0 –6.0 dBm –30.0 820 860 Spectral Width (FWHM) ∆λ 2 Relative Intensity Noise RIN –116 Extinction Ratio (dynamic) ER nm dB/Hz 5.0 dB Notes Optical parameters valid for each channel. Transmitter Electro-Optical Characteristics Parameter Launched Average Power Min. Typ. 350 1.2 250 LVCMOS Output Voltage Low VLVCMOSOL LVCMOS Output Voltage High VLVCMOSOH 2.5 LVCMOS Input Current High/Low ILVCMOSI LVCMOS Output Current High(2) 1. 20%–80% level. Max. Units 450 mA 1.6 W 2. With input channel-to-channel skew 0 ps and a maximum LVDS channel-to-channel average deviation and swing deviation of 5%. Figure 2. Timing diagram 1600 MBit/ s 0.4 V V -RESET 500 µA ILVCMOSOH 0.5 mA LVCMOS Output Current Low(3) ILVCMOSOL 4.0 mA LVDS Differential Input Impedance(4) RIN 120 Ω LVDS Input Differential Current |II| 5.0 mA –500 3.6 V 3.0 V VCC 2.0 V 0.8 V t3 data valid data invalid Data t2 t1 80 Parameter Symbol -RESET on Delay Time t1 -RESET off Delay Time t2 -RESET Low Duration(1) t3 Min. Max. Units 100 ms 50 µs 10 µs Notes Note 1. Electrical input data should be DC balanced within 144 bits. Maximum time interval of consecutive ’0’s and ’1’s (run length) should be 72 bits. 1. Only when not used as power on reset. At any failure recovery, -RESET must be brought to low level for at least t3. 2. Source current. Transmitter Pin Description 3. Sink current. 4. LVDS Input Stage. VCC 14 K Data In P Pin# Pin Name 1.2 V ± 0.2 V 1 VCC Power supply voltage of laser driver 2 t.b.l.o. to be left open 4 C Rin/2 5 Data In N 6 LA 7 VEE 8K Parameter Symbol Optical Rise Time(1) tR Optical Fall Time(1) tF Random Jitter (14σ) Deterministic Jitter Channel-to-channel Description 3 Rin/2 skew(2) Level/Logic Min. Max. Units 400 ps JR 0.23 UI JD 0.20 tCSK 75 ps Fiber Optics LVCMOS Out Laser Active High=normal operation Low=laser fault or -RESET low Ground 8 VEE Ground 9 t.b.l.o. to be left open 10 t.b.l.o. to be left open 11 VEE Ground 12 VEE 13 DI01N LVDS In Data Input #1, inverted 14 DI01P LVDS In Data Input #1, non- inverted Ground V23814/15-U1306-M130 Parallel Optical Link: PAROLI Tx/Rx AC, 1.6 Gbit/s 3 Pin# Pin Name Level/Logic Description Pin# Pin Name 15 16 VEE Ground 61 VEE Ground VEE Ground 62 VEE Ground 17 DI02N 18 DI02P LVDS In Data Input #2, inverted 63 t.b.l.o. LVDS In Data Input #2, non- inverted 64 -RESET 19 VEE Ground 20 VEE Ground 21 DI03N LVDS In Data Input #3, inverted 22 DI03P LVDS In Data Input #3, non- inverted 23 VEE Ground 24 VEE Ground 25 t.b.l.o. to be left open 65 VEE Ground 66 VEE 26 DI04N LVDS In Data Input #4, inverted Ground 27 DI04P LVDS In Data Input #4, non- inverted 67 LE 28 VEE 29 DI05N LVDS In Data Input #5, inverted 30 DI05P LVDS In Data Input #5, non- inverted 31 VEE Ground 32 VEE Ground 33 DI06N LVDS In Data Input #6, inverted 34 DI06P LVDS In Data Input #6, non- inverted 68 -LE Laser ENABLE. Low active. Low=laser array is on if LE is also active. This input can be used for connection with an Open Fiber Control (OFC) circuit to enable IEC class 1 links. Has an internal pulldown, therefore can be left open. 35 VEE Ground 36 VEE Ground 37 DI07N LVDS In Data Input #7, inverted 38 DI07P LVDS In Data Input #7, non- inverted 39 VEE Ground 40 VEE Ground 69 t.b.l.o. to be left open 41 DI08N 42 DI08P LVDS In Data Input #8, inverted 70 t.b.l.o. to be left open LVDS In Data Input #8, non- inverted 71 t.b.l.o. to be left open 43 44 VEE Ground 72 VCC VEE Ground Power supply voltage of laser driver Ground 45 VEE 46 DI09N LVDS In 47 DI09P LVDS In 48 t.b.l.o. to be left open 49 VEE Ground 50 VEE Ground 51 DI10N LVDS In Data Input #10, inverted 52 DI10P LVDS In Data Input #10, non- inverted 53 VEE Ground 54 VEE Ground 55 DI11N LVDS In Data Input #11, inverted 56 DI11P LVDS In Data Input #11, non- inverted 57 VEE Level/Logic Description to be left open LVCMOS In LVCMOS In High=laser diode array is active Low=switches laser diode array off This input has an internal pull-down resistor to ensure laser safety switch off in case of unconnected -RESET input Laser ENABLE. High active. High=laser array is on if -LE is also active. Low=laser array is off. This input can be used for connection with an Open Fiber Control (OFC) circuit to enable IEC class 1 links. Has an internal pull-up, therefore can be left open. Ground Data Input #9, inverted Data Input #9, non- inverted Ground 58 VEE 59 DI12N LVDS In Data Input #12, inverted 60 DI12P LVDS In Data Input #12, non- inverted Ground Fiber Optics V23814/15-U1306-M130 Parallel Optical Link: PAROLI Tx/Rx AC, 1.6 Gbit/s 4 DESCRIPTION TECHNICAL DATA Receiver V23815-U1306-M130 Recommended Operating Conditions The PAROLI receiver module converts parallel optical input signals into parallel electrical output signals. The optical signals received are converted into voltage signals by PIN diodes, transimpedance amplifiers, and gain amplifiers. All output data signals are Low Voltage Differential Signals (LVDS). The data rate is 250-1600 Mbit/s for each channel. Optical input data should be DC balanced within 144 bits. The maximum time interval of consecutive 0’s and 1’s (run length) should not exceed 72 bits. This will ensure that the output jitter values given for the transmitter and receiver in this data sheet will be met. Otherwise, jitter values might be exceeded. Additional Signal Detect outputs (SD1 active high / SD12 active low) show whether an optical AC input signal is present at data input 1 and/or 12. The signal detect circuit can be disabled with a logic low at ENSD. The disabled signal detect circuit will permanently generate an active level at Signal Detect outputs, even if there is insufficient signal input. This could be used for test purposes. Parameter Symbol Min Power Supply Voltage VCC 3.0 Noise on Power Supply(1) NPS1 Max Units 3.6 V 10 mV Noise on Power Supply(2) NPS2 Differential LVDS Termination Impedance Rt 80 120 Ω LVCMOS Input High Voltage VLVCMOSIH 2.0 VCC V LVCMOS Input Low Voltage VLVCMOSIL VEE 0.8 LVCMOS Input Rise/Fall Time(3) tR, tF 20 ns Optical Input Rise/Fall Time(4) tR, tF 400 ps Input Extinction Ratio ER 5.0 Input Center Wavelength λC 820 100 dB 860 nm Notes A logic low at LVDS Output Enable sets all data outputs to logic low. SD outputs will not be effected. All nondata signals have LVCMOS levels. Transmission delay of the PAROLI system is at a maximum 1 µs for the transmitter, 1 µs for the receiver and approximately 5 ns per meter for the fiber optic cable. Voltages refer to VEE=0 V. 1. Noise frequency: 1 kHz to 1 MHz. 2. Noise frequency: 1 MHz to 1 GHz. 3. Measured between 0.8 V and 2.0 V. 4. 20%–80% level. Receiver Electro-Optical Characteristics Figure 3. Receiver block diagram Optical Input 12 12 Data Parameter Electrical Outputs Pin Diode Array Amplifier Gain Amplifier 12 LVDS Output Stage ENSD Min. Typ. Max. Units Supply Current lCC 250 350 mA Power Consumption P 0.8 1.3 W Data out LVDS Output Low Voltage(1,4) VLVDSOL SD1 LVDS Output High Voltage(1,4) VLVDSOH LVDS Output Differential Voltage(1, 2, 4) |VOD| 250 400 LVDS Output Offset Voltage(1, 3, 4) VOS 1125 1275 12 Signal Detect Circuit Symbol -SD12 LVDS Output Enable Fiber Optics 925 mV 1475 LVDS Rise/Fall Time(5) tR, tF 400 ps LVCMOS Output Voltage Low ILVCMOSOL 400 mV LVCMOS Output Voltage High ILVCMOSOH 2500 LVCMOS Input Current High/Low ILVCMOSI –500 500 µA LVCMOS Output(8) Current High ILVCMOSOH 0.5 mA LVCMOS Output(9) Current Low ILVCMOSOL 4.0 Random Jitter(6, 7) (14σ) JR 0.31 Deterministic Jitter(6) JD 0.08 Channel-to-channel skew(10) tCSK 75 UI ps V23814/15-U1306-M130 Parallel Optical Link: PAROLI Tx/Rx AC, 1.6 Gbit/s 5 Notes 1. Level Diagram: LVDS Output Enable mV 2.0 V 0.8 V 1475 Data Out data valid data valid data Low |VID| t3 925 t4 Parameter Symbol Max. Units 2. |VOD|=|(output voltage of non-inverted output minus output voltage of inverted output)|. Signal Detect Deassert Time t1 10 µs 3. VOS=1/2 (output voltage of inverted output + output voltage of noninverted output). Signal Detect Assert Time t2 4. LVDS output must be terminated differentially with Rt. 5. Measured between 20% and 80% level with a maximum capacitive load of 5 pF. LVDS Output Enable off Delay Time t3 20 ns LVDS Output Enable on Delay Time t4 Time 6. With no optical input jitter. 7. At sensitivity limit of -17.0 dBm at infinite ER. Receiver Pin Description 8. Source current 9. Sink current Pin# Pin Name 10.With input channel-to-channel skew 0 ps. 1 VEE Ground 2 VCC1 Power supply voltage of preamplifier 3 VCC2 Power supply voltage of analog circuitry 4 t.b.l.o. to be left open 5 -RESET LVCMOS In High=normal operation Low=sets all Data Outputs to low This input has an internal pull-up resistor which pulls to high level when this input is left open 6 SD1 LVCMOS Out Optical parameters valid for each channel. 7 VCC3 1. Optical input data should be DC balanced within 100 ns. Maximum time interval of consecutive ’0’s and ’1’s (run length) should not exceed 50 ns. 8 VEE Ground 9 t.b.l.o. to be left open 2. Measured with a DC balanced pattern (within 144 bits) with a maximum run length of 72 bits. BER=10 –12. Extinction ratio=infinite. 10 VEE Ground 11 VEE Ground 12 VEE 13 DO01P LVDS Out Data Output #1, non-inverted 14 DO01N LVDS Out Data Output #1, inverted 15 VEE 16 VEE 17 DO02P LVDS Out Data Output #2, non-inverted 18 DO02N LVDS Out Data Output #2, inverted 19 VEE 20 VEE 21 DO03P LVDS Out Data Output #3, non-inverted 22 DO03N LVDS Out Data Output #3, inverted Parameter Symbol Min. Data Rate Per Channel(1) DR Sensitivity (Average Power)(2) PIN Typ. Max. Units 250 1600 Mbit/s –17.0 dBm Saturation (Average Power)(2) PSAT –6.0 Signal Detect Assert Level(3) PSDA Signal Detect Deassert Level(3) PSDD –26.0 Signal Detect Hysteresis(3) PSDA– PSDD 1.0 Return Loss of Receiver ARL 12 –18.0 2.5 4.0 dB Level/Logic Description Notes 3. PSDA: Average optical power when SD switches from unactive to active. PSDD: Average optical power when SD switches from active to unactive. Figure 4. Timing diagram Data Out 1, 12 t1 t2 Signal Detect 1 Signal Detect 12 Fiber Optics Signal Dectect on fiber #1. High=signal of sufficient AC power is present on fiber #1 Low=signal on fiber #1 is insufficient Power supply voltage of digital circuitry Ground Ground Ground Ground Ground V23814/15-U1306-M130 Parallel Optical Link: PAROLI Tx/Rx AC, 1.6 Gbit/s 6 Pin# Pin Name Level/Logic Description 23 VEE Ground 24 VEE Ground 25 t.b.l.o. 26 DO04P LVDS Out Data Output #4, non-inverted 27 DO04N LVDS Out Data Output #4, inverted 28 VEE Pin# Pin Name Level/Logic Description 67 -SD12 LVCMOS Out low active 68 ENSD LVCMOS In High=SD1 and SD12 function enabled Low=SD1 and SD12 are set to permanent active.Internal pullup pulls to high level when input is left open. to be left open Ground Signal Detect on fiber #12 Low=signal of sufficient AC power is present on fiber #12 High=signal on fiber #12 is insufficient 29 DO05P LVDS Out Data Output #5, non-inverted 30 DO05N LVDS Out Data Output #5, inverted 31 VEE Ground 69 t.b.l.o. to be left open 32 VEE Ground 70 VCC2 33 DO06P LVDS Out Data Output #6, non-inverted Power supply voltage of LVDS outputs 34 DO06N LVDS Out Data Output #6, inverted 71 VCC1 35 VEE Ground Power supply voltage of amplifier 36 VEE Ground 72 VEE Ground 37 DO07P LVDS Out Data Output #7, non-inverted Optical Port 38 DO07N LVDS Out Data Output #7, inverted Designed for Infineon Simplex MT Connector (SMC) 39 VEE Ground • Port outside dimensions: 15.4 mm x 6.8 mm (width x height) 40 VEE Ground 41 DO08P LVDS Out Data Output #8, non-inverted • MT compatible fiber spacing (250 µm) and alignment pin spacing (4600 µm) 42 DO08N LVDS Out Data Output #8, inverted • Alignment pins fixed in module port 43 VEE Ground • Integrated mechanical keying 44 VEE Ground • process plug (SMC dimensions) included with every module 45 VEE Ground 46 DO09P LVDS Out Data Output #9, non-inverted • cleaning of port and connector interfaces necessary prior to mating 47 DO09N LVDS Out Data Output #9, inverted Features of Infineon Simplex MT Connector (SMC) 48 t.b.l.o. to be left open (as part of optional PAROLI fiber optic cables) 49 VEE Ground 50 VEE Ground 51 DO10P LVDS Out Data Output #10, non-inverted • MT compatible fiber spacing (250 µm) and alignment pin spacing (4600 µm) 52 DO10N LVDS Out Data Output #10, inverted • Snap-in mechanism 53 VEE Ground 54 VEE Ground 55 DO11P LVDS Out Data Output #11, non-inverted 56 DO11N LVDS Out Data Output #11, inverted 57 VEE Ground 58 VEE Ground 59 DO12P LVDS Out Data Output #12, non-inverted 60 DO12N LVDS Out Data Output #12, inverted 61 VEE Ground 62 VEE Ground 63 VEE Ground 64 t.b.l.o. to be left open 65 VEE Ground 66 VCC3 Power supply voltage of digital circuitry • Uses standardized MT ferrule • Ferrule bearing spring loaded • Not strain-relieved • Integrated mechanical keying Cleaning and Soldering Process for Transmitter and Receiver Special care must be taken to remove residuals from the soldering and washing process, which can impact the mechanical function. Avoid the use of aggressive organic solvents like ketones, ethers, etc. Consult the supplier of the PAROLI modules and the supplier of the solder paste and flux for recommended cleaning solvents. The following common cleaning solvents will not affect the module: deionized water, ethanol, and isopropyl alcohol. Airdrying is recommended to a maximum temperature of 100°C. Do not use ultrasonics. During soldering, heat must be applied to the leads only, to ensure that the case temperature never exceeds 100°C. The module must be mounted with a hot-bar soldering process using a SnPb solder type, e.g.. S-Sn63Pb37E, in accordance with ISO 9435. Fiber Optics V23814/15-U1306-M130 Parallel Optical Link: PAROLI Tx/Rx AC, 1.6 Gbit/s 7 Figure 5. Numbering convention Pin 1 Pin 28 Figure 7. Recommended footprint: transmitter Dimensions in mm (inches) Top View Pin 29 (18) .709 Pin 44 Fiber 1 Fiber 12 Pin 45 Top View Pin 72 (13.5) .531 Figure 6. Recommended footprint: receiver (∅0.2) A B ∅.008 A B Dimensions in mm (inches) (18) .709 (15.4) .606 (2±0.1) .08±.004 (3.5) .138 (22.7) .894 Top View (7).276 (13.5) .531 (∅0.2) A B ∅.008 A B (15.4) .606 1 (3.5) .138 (33.89) 1.334 72 (2±0.1) .08±.004 (22.7) .894 27x Detail Y 29 72 1 B 15 x (33.89) 1.334 A B 29 44 (1.64) .065 (0.65 = 9.75) .0256=.691 (14.9) .587 Dashed lines show module outline and board space required for SMC plug. No electronic components on customer PCB within this area. (1.64) .065 (0.65 = 9.75) 15 x .0256=.691 A 44 (18.7) .736 45 Detail Y 28 (0.65 = 17.55) 27x .0256=.691 (0.65 = 17.55) .0256=.691 45 28 (7).276 Figure 8. Mounting hole, Detail Y (2.575) .1014 (14.9) .587 (18.7) .736 (2.775) .0109 Dashed lines show module outline and board space required for SMC plug. No electronic components on customer PCB within this area. (1.8±0.05) .071±.002 72x 28 (∅0.05) M A B ∅.002 M A B 29 (2.55+0.03/-0) 0.100+.001/-0 (∅0.05) M A B 4x ∅.002 M A B (0.35+0.05/-0) .014+.002/-0 72x (∅0.05) M A B ∅.002 M A B dashed lines show module outlines Fiber Optics V23814/15-U1306-M130 Parallel Optical Link: PAROLI Tx/Rx AC, 1.6 Gbit/s 8 Figure 9. Applications LVDS SMC Port PAROLI LD Link Controller Tx Rx PD Ribbon Cable Board-to-Board Passive Optical Backplane PAROLI SMC Port Tx Ribbon Cable Rx Optical Feed Through Backplane Connector I/O Board Backplane PAROLI LD Tx SMC Port SMC Port Ribbon Cable PD Rx LVDS LVDS Point-to-Point Published by Infineon Technologies AG Warnings © Infineon Technologies AG 1999 All Rights Reserved Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your Infineon Technologies offices. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologiesis an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact the Infineon Technologies offices or our Infineon Technologies Representatives worldwide - see our webpage at www.infineon.com/fiberoptics Infineon Technologies AG • Fiber Optics • Wernerwerkdamm 16 • Berlin D-13623, Germany Infineon Technologies, Inc. • Fiber Optics • 19000 Homestead Road • Cupertino, CA 95014 USA Siemens K.K. • Fiber Optics • Takanawa Park Tower • 20-14, Higashi-Gotanda, 3-chome, Shinagawa-ku • Tokyo 141, Japan