Fiber Optics Parallel Optical Link Transmitter: PAROLI® 2 Tx AC, 1.6 Gbit/s Parallel Optical Link Receiver: PAROLI® 2 Rx AC, 1.6 Gbit/s V23832-T2131-M101 V23832-R121-M101 Design Benefits • • • • • Relieve system bandwidth bottle necks Simplifies system design Enables system upgrades in field Low power consumption at increased board density Flat package for height critical application Features • • • • • • • • • • • • • • • • • • • • Infineon’s highly reliable 850 nm VCSEL technology Power supply 3.3 V Transmitter with multistandard electrical interface Receiver with LVDS electrical interface 12 electrical data channels Asynchronous, AC-coupled optical link 12 optical data channels Internal power monitoring for constant power budget Transmission data rate of up to 1600 Mbit/s per channel, total link data rate up to 19 Gbit/s PIN diode array technology Optimized for 62.5 µm multimode graded index fiber MT based optical port (MPO connector) Plug-in module with ultra low profile IEC Class 1M laser eye safety compliant GBE mask compliant modules available EMI-shielding for front panel access Standard link length compliant Unused transmitter channels can be switched off DC or AC coupling of input data Telcordia compliant File: 3104 PAROLI ® is a registered trademark of Infineon Technologies AG Data Sheet 1 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Applications Optical Port • • • • Designed for the industry standard 12 fiber MT Connector (MPO) Alignment pins fixed in module port Integrated mechanical keying Module is provided with a dust cover Features of MT Connector (MPO) (as part of optional PAROLI fiber optic cables) • • • • Uses standardized MT ferrule MT compatible fiber spacing (250 µm) and alignment pin spacing (4600 µm) Push-pull mechanism Ferrule bearing spring loaded Features of the PAROLI 2 Electrical Connector • • • • • • • • Pluggable version using BGA socket 100 pin positions (10x10) 4 mm stack height in mated conditions Plug and receptacle are provided with protective cap Standard BGA process for socket assembly Contact area plating made out of gold over nickel Module side: FCI-MEG-Array® -Plug (part no. 84512-202) PCB side: FCI-MEG-Array® -Receptacle (part no. 84513-201) Applications • • • • • Switches, routers, transport equipment Mass storage devices Access network Rack-to-rack/board-to-board interconnect Optical backplane interconnect Data Sheet 2 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Pin Configuration Pin Configuration Pin A1 Pin A10 Bottom view File: 3331 Figure 1 Pin Information Transmitter Numbering Conventions Transmitter (bottom view) J I H G F E D C B A 1 VEE DI05N DI05P DI06N DI06P DI07N DI07P DI08N DI08P VEE 2 DI04P VEE VEE VEE VEE VEE VEE VEE VEE DI09N 3 DI04N VEE Reserved Reserved t.b.l.o. t.b.l.o. Reserved Reserved VEE DI09P 4 DI01P VEE Reserved Reserved t.b.l.o. t.b.l.o. Reserved Reserved VEE DI12N 5 DI01N VEE VEE VEE t.b.l.o. t.b.l.o. VEE VEE VEE DI12P 6 DI02P VEE VEE VEE t.b.l.o. –LE VEE VEE VEE DI11N 7 DI02N VEE VEE VEE LCU LE VEE VEE VEE DI11P 8 DI03P VEE VEE VEE VIN –RESET VEE VEE VEE DI10N 9 DI03N VEE VEE VEE VCC VCC VEE VEE VEE DI10P VEE VEE VEE VCC VCC VEE VEE VEE VEE 10 VEE This edge towards MPO connector Data Sheet 3 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Pin Configuration Pin Description Transmitter Symbol Level/Logic Description VCC VIN Power supply voltage of laser driver CML: VIN = Reference supply (e.g. VCC) LVDS, LVPECL: VIN = VEE VEE Ground LCU LVCMOS Out Laser Controller Up. High = normal operation. Low = laser fault or RESETlow. DIxxN Signal In Data Input #xx, inverted DIxxP Signal In Data Input #xx, non-inverted –RESET LVCMOS In High = laser diode array is active. Low = switches laser diode array off. This input has an internal pull-down to ensure laser eye safety switch off in case of unconnected RESETinput. LE LVCMOS In Laser ENABLE. High active. High = laser array is on if LE is also active. Low = laser array is off. This input has an internal pull-up, therefore can be left open. –LE LVCMOS In Laser ENABLE. Low active. Low = laser array is on if LE is also active. This input has an internal pull-down, therefore can be left open. t.b.l.o. to be left open Reserved Reserved for future use Data Sheet 4 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Pin Configuration Pin A1 Pin A10 Bottom view File: 3332 Figure 2 Pin Information Receiver Numbering Conventions Receiver (bottom view) J I H G F E D C B A 1 VEE DO05P DO05N DO06P DO06N DO07P DO07N DO08P DO08N VEE 2 DO04N VEE VEE VEE VEE VEE VEE VEE VEE DO09P 3 DO04P VEE Reserved Reserved t.b.l.o. t.b.l.o. Reserved Reserved VEE DO09N 4 DO01N VEE Reserved Reserved OEN ENSD Reserved Reserved VEE DO12P 5 DO01P VEE VEE VEE SD01 –SD12 VEE VEE VEE DO12N 6 DO02N VEE VEE VEE Reserved REFR VEE VEE VEE DO11P 7 DO02P VEE VEE VEE VCCO VCCO VEE VEE VEE DO11N 8 DO03N VEE VEE VEE VCCO VCCO VEE VEE VEE DO10P 9 DO03P VEE VEE VEE VCC VCC VEE VEE VEE DO10N VEE VEE VEE VCC VCC VEE VEE VEE VEE 10 VEE This edge towards MPO connector Data Sheet 5 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Pin Configuration Pin Description Receiver Symbol Level/Logic Description VCC VCCO Power supply voltage of pre amplifier and analog circuitry REFR LVDS = to be left open (t.b.l.o.) VEE Ground Power supply voltage of output stages OEN LVCMOS In Output Enable High = normal operation. Low = sets all Data Outputs to low. This input has an internal pull-up which pulls to high level when this input is left open. ENSD LVCMOS In High = SD1 and –SD12 function enabled. Low = SD1 and –SD12 are set to permanent active. This input has an internal pull-up which pulls to high level when this input is left open. SD1 LVCMOS Out Signal Detect on fiber #1. High = signal of sufficient AC power is present on fiber #1. Low = signal on fiber #1 is insufficient. –SD12 LVCMOS Out low active Signal Detect on fiber #12. Low = signal of sufficient AC power is present on fiber #12. High = signal on fiber #12 is insufficient. DOxxP LVDS Out Data Output #xx, non-inverted DOxxN LVDS Out Data Output #xx, inverted t.b.l.o. to be left open Reserved Reserved for future use Data Sheet 6 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Description Description PAROLI is a parallel optical link for high-speed data transmission. A complete PAROLI link consists of a transmitter module, a 12-channel fiber optic cable, and a receiver module. The transmitter supports LVDS, CML and LVPECL differential signals. This specification describes the LVDS electrical output only. A specification for Infineon’s adjustable CML output can be provided separately. PAROLI Link Figure 3 Data Sheet Data Out 12 Converter 12 parallel channels Receiver Amplifier DC-balanced data stream PIN-Array VCSEL Array 12 Laser Driver Converter Data In Transmitter File: 3509 Example of a PAROLI Link 7 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Description Transmitter V23832-T2131-M101 The transmitter module converts parallel electrical input signals via a laser driver and a Vertical Cavity Surface Emitting Laser (VCSEL) diode array into parallel optical output signals. All input data signals are Multistandard Differential Signals (LVDS compatible; LVPECL and CML is also supported because of the wide common input range). The electrical interface (LVDS, LVPECL or CML) is selected by the supply inputs VIN. The data rate is up to 1600 Mbit/s for each channel. The transmitter module’s min. data rate of 500 Mbit/s is specified for the CID1) worst case pattern (disparity 72) or any pattern with a lower disparity. The transmitter features active feedback of optical output power and extinction ratio, which guarantees a constant power budget. Unused channels can be forced to a quiescent state by applying e.g. a constant high level to the input stage of these channels. The integrated alerter circuit (see “Laser Eye Safety Design Considerations” on Page 12) will switch off the corresponding transmitter output, which results also in a reduced power consumption. Unused transmitter input channels can also be left open. The integrated swing detection circuit will assure a quiescent output state for these channels. A logic low level at –RESET switches all laser outputs off. During power-up –RESET must be used as a power-on reset which disables the laser driver and laser control until the power supply has reached a 3.135 V level. The Laser Controller Up (LCU) output is low if a laser fault is detected or –RESET is forced to low. All non data signals have LVCMOS levels. Transmission delay of the PAROLI system is ≤ 1 ns for the transmitter, ≤ 1 ns for the receiver and approximately 5 ns per meter for the fiber optic cable. Data In −LE Laser Enable LE Electrical Input 12 12 Input Stage Laser Driver 12 Laser Diode Array Optical Output 12 Data Laser Control VIN Figure 4 1) −RESET Laser Controller Up (LCU) File: 3317 Transmitter Block Diagram Consecutive Identical Digit (CID) immunity test pattern for STM-N signals, ITU-T recommendation G.957 sec. II. Data Sheet 8 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Description Receiver V23832-R121-M101 The PAROLI receiver module converts parallel optical input signals into parallel electrical output signals. The optical signals received are converted into voltage signals by PIN diodes, trans impedance amplifiers, and gain amplifiers. There are two different modules available, one for LVDS and one for CML output. This description only refers to a module with LVDS output. A module description for Infineon’s adjustable CML output can be provided separately. The data rate is up to 1600 Mbit/s for each channel. The receiver module’s min. data rate of 500 Mbit/s is specified for the CID1) worst case pattern (disparity 72) or any pattern with a lower disparity. Additional Signal Detect outputs (SD1 active high / –SD12 active low) show whether an optical AC input signal is present at data input 1 and/or 12. The signal detect circuit can be disabled with a logic low at ENSD. The disabled signal detect circuit will permanently generate an active level at Signal Detect outputs, even if there is insufficient signal input. This could be used for test purposes. A logic low at LVDS Output Enable (OEN) sets all data outputs to logic low. SD outputs will not be effected. All non data signals have LVCMOS levels. Transmission delay of the PAROLI system is at a maximum 1 ns for the transmitter, 1 ns for the receiver and approximately 5 ns per meter for the fiber optic cable. Optical Input Electrical Output 12 Data 12 Pin Diode Array Gain Amplifier Amplifier 1) LVDS Output Stage Signal Detect Circuit ENSD Figure 5 12 12 Data Out SD1 −SD12 Output Enable (OEN) File: 3333 Receiver Block Diagram Consecutive Identical Digit (CID) immunity test pattern for STM-N signals, ITU-T recommendation G.957 sec. II. Data Sheet 9 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Description Regulatory Compliance The following table shows industry standard test methods and results obtained from the indicated test methods. (The overall system design will affect the electromagnetic interference (EMI), electrostatic discharge (ESD) and immunity). Feature Standard Comments ESD: Electrostatic Discharge to the Electrical Pins (HBM) JEDEC Human Body Model (HBM) Test Method EIA/JESD22-A114-B (MIL-STD 883D method 3015.7) Class 1C Immunity: EN 61000-4-2 Against Electrostatic IEC 61000-4-2 Discharge (ESD) to the Module Receptacle Discharges ranging from ±2 kV to ±15 kV on the front end/face-plate/ receptacle cause no damage to module (under recommended mounting conditions). Immunity: Against Radio Frequency Electromagnetic Field EN 61000-4-3 IEC 61000-4-3 With a field strength of 3 V/m, noise frequency ranges from 10 MHz to 2 GHz1). No effect on module performance between the specification limits. Emission: Electromagnetic Interference (EMI) FCC 47 CFR Part 15, Class B EN 55022 Class B CISPR 22 Noise frequency range: 30 MHz to 18 GHz; Radiated Emission does not exceed specified limits when measured inside a shielding enclosure with recommended cutout dimensions. Typically pass with > 11 dB margin to the limit (under recommended mounting conditions). 1) This test covers high frequency bands of mobile phones. EMI Recommendations EMI behavior of each PAROLI module revision is evaluated and measured - in order to ensure a good and sufficient EMI performance of all PAROLI modules. As the total EMI performance will also depend on system design and to avoid electromagnetic radiation exceeding the required limits set by the standards, please take note of the following recommendations. Data Sheet 10 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Description When Gigabit switching components are found on a PCB (e.g. multiplexer, serializerdeserializer, clock data recovery, etc.), any opening of the chassis may leak radiation; this may also occur at chassis slots other than that of the device itself. Thus every mechanical opening or aperture should be as small as feasible and its length carefully considered. On the board itself, every data connection should be an impedance matched line (e.g. micro strip, strip line or coplanar strip line). Data (D) and Data-not (Dn) should be routed symmetrically. Vias should be avoided. Where internal termination inside an IC or a PAROLI module is not present, a line terminating resistor must be provided. The decision of how best to establish a ground depends on many boundary conditions. This decision may turn out to be critical for achieving lowest EMI performance. At RF frequencies the ground plane will always carry some amount of RF noise. Thus the ground and VCC planes are often major radiators inside an enclosure. As a general rule, for small systems such as PCI cards placed inside poorly shielded enclosures, the common ground scheme has often proven to be most effective in reducing RF emissions. In a common ground scheme, the PCI card becomes more equipotential with the chassis ground. As a result, the overall radiation will decrease. In a common ground scheme, it is strongly recommended to provide a proper contact between signal ground and chassis ground at every location where possible. This concept is designed to avoid hotspots which are places of highest radiation, caused when only a few connections between chassis and signal grounds exist. Compensation currents would concentrate at these connections, causing radiation. However, as signal ground may be the main cause for parasitic radiation, connecting chassis ground and signal ground at the wrong place may result in enhanced RF emissions. For example, connecting chassis ground and signal ground at a front panel/ bezel/chassis by means of a fiber optic module may result in a large amount of radiation especially where combined with an inadequate number of grounding points between signal ground and chassis ground. Thus the fiber optic module becomes a single contact point increasing radiation emissions. Even a capacitive coupling between signal ground and chassis ground may be harmful if it is too close to an opening or an aperture. For a number of systems, enforcing a strict separation of signal ground from chassis ground may be advantageous, providing the housing does not present any slots or other discontinuities. This separate ground concept seems to be more suitable in huge systems. The return path of RF current must also be considered. Thus a split ground plane between Tx and Rx paths may result in severe EMI problems. The bezel opening for a transceiver should be sized so that all contact springs of the transceiver cage make good electrical contact with the face plate. Please consider that the PCB may behave like a dielectric waveguide. With a dielectric constant of 4, the wavelength of the harmonics inside the PCB will be half of that in free space. Thus even the smallest PCBs may have unexpected resonances. Data Sheet 11 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Laser Eye Safety Laser Eye Safety The transmitter of the AC coupled Parallel Optical Link (PAROLI) is an IEC 60825-1 Amend. 2 Class 1M laser product. It complies with FDA performance standards (21 CFR 1040.10 and 1040.11) for laser products except for deviations pursuant to Laser Notice No. 50, dated July 26, 2001. To avoid possible exposure to hazardous levels of invisible laser radiation, do not exceed maximum ratings. The PAROLI module must be operated under the specified operating conditions (supply voltage can be adjusted between 3.0 V and 3.6 V) under any circumstances to ensure laser eye safety. Class 1M Laser Product Attention: Invisible laser radiation. Do not view directly with optical instruments. Note: Any modification of the module will be considered an act of “manufacturing”, and will require, under law, recertification of the product under FDA (21 CFR 1040.10 (i)). Laser aperture and beam File: 3506 Figure 6 Laser Emission Laser Eye Safety Design Considerations To ensure laser eye safety for all input data patterns each channel is controlled internally and will be switched off if the laser eye safety limits are exceeded. A channel alerter switches the respective data channel output off if the input duty cycle permanently exceeds 57% (switching range 57 % min. - 65 % max.). The alerter will not disable the channel below an input duty cycle of 57% under all circumstances. The minimum alerter response time is 1 µs with a constant high input, i.e. in the input pattern the time interval of excessive high input (e.g. ’1’s in excess of a 57% duty cycle, consecutive or non-consecutive) must not exceed 1 µs, otherwise the respective channel will be switched off. The alerter switches the respective channel from off to on without the need of resetting the module if the input duty cycle is no longer violated. All of the channel alerters operate independently, i.e. an alert within a channel does not affect the other channels. To decrease the power consumption of the module unused channel inputs can be tied to high input level. In this way a portion of the supply current in this channel is triggered to shut down by the corresponding alerter. Data Sheet 12 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Laser Eye Safety Laser Eye Safety Measurement Conditions Laser Data Symbol Center wavelength λC Values min. typ. max. 830 850 860 Array size 12 Divergence angle/ Numerical Aperture Θ/NA IEC class 1M Accessible Emission Limit AEL Applying penalties (safety margin) ∆Popt Data Sheet 13 Condition nm Tcase 0...80°C channels °/rad Θ full / NA half angle 6.36 dBm 7 mm aperture @ 100 mm distance 4.2 dB 2.16 dBm 44/0.22 Test limit Unit 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Technical Data Technical Data Absolute Maximum Ratings Stress beyond the values stated below may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Performance between absolute maximum ratings and recommended operating conditions is not guaranteed. Parameter Symbol VCC–VEE VIN |VID| Tcase Tstg Supply Voltage Data/Control Input Levels 1) Data Input Differential Voltage 2) Operating Case Temperature 3) Storage Ambient Temperature Relative Humidity (non condensing) Limit Values min. max. –0.3 4.5 V –0.5 VCC+0.5 V 2.0 V 0 90 °C –40 100 °C 5 95 % 1 kV ESD Resistance (all pins to VEE, human body model) 4) (see table “Regulatory Compliance” on Page 10) 1) 2) 3) 4) Unit At Data and LVCMOS inputs. |VID| = |(input voltage of non-inverted input minus input voltage of inverted input)|. Measured at case temperature reference point (see Figure 15 on Page 28). To avoid electrostatic damage, handling cautions similar to those used for MOS devices must be observed. Recommended Operating Conditions1) Parameter Symbol Values Unit min. typ. max. Tcase VCC NPS VDATAI 0 45 80 °C 3.135 3.3 3.6 V 200 mV 500 VCC mV |VID| 80 1000 mV Transmitter Operating Case Temperature Power Supply Voltage Noise on Power Supply 2) Data Input Voltage Range (DC-coupled) 3), 4) Data Input Differential Voltage (DC- or AC-coupled) 4), 5) Data Sheet 14 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Technical Data Recommended Operating Conditions1) (cont’d) Parameter Symbol Values min. Data Input Skew 6) typ. tSPN Unit max. 0.5 x tR-DI, ps tF-DI Data Input Rise/Fall Time 7) LVCMOS Input High Voltage LVCMOS Input Low Voltage LVCMOS Input Rise/Fall Time 8) tR-DI, tF-DI 50 VLVCMOSIH 2.0 VLVCMOSIL VEE tR-LVCMOSI, tF-LVCMOSI 280 ps VCC V 0.8 V 20 ns 3.6 V 200 mV 120 Ω VCC V 0.8 V 20 ns 320 ps Receiver Power Supply Voltages Noise on Power Supply 2) Differential LVDS Termination Impedance VCC, VCCO 3.0 NPS Rt 80 Optical Input Rise/Fall Time9) VLVCMOSIH 2.0 VLVCMOSIL VEE tR-LVCMOSI, tF-LVCMOSI tR-OI, tF-OI Input Extinction Ratio ER 6.0 Input Center Wavelength λC 830 LVCMOS Input High Voltage LVCMOS Input Low Voltage LVCMOS Input Rise/Fall Time 8) 3.3 dB 860 nm Voltages refer to VEE = 0 V. 1) 2) 3) 4) 5) 6) 7) 8) 9) Recommended range of input parameters for specified module functional performance. Noise frequency is 1 kHz to fmax, where fmax is equal to the maximum data rate in units of MHz. E.g. for a maximum data rate of 2700 Mbit/s, fmax = 2700 MHz. Power supply noise is defined with the recommended filter in place at the supply side of the filtering circuit (see Figure 9 on Page 17). The input stage can also be AC-coupled. Input level diagram: see Figure 7 on Page 16. |VID| = |(input voltage of non-inverted input minus input voltage of inverted input)|. Skew between positive and negative inputs measured at 50% level. 20% - 80% level. Measured between 0.8 V and 2.0 V. 20% - 80% level. Non filtered values. Data Sheet 15 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Technical Data mV VCC |VID| 500 Time Figure 7 File: 3318 Input Level Diagram, DC-coupling mV 1475 |VOD| 925 Time File: 3334 Figure 8 Data Sheet Output Level Diagram, DC-coupling 16 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Technical Data Recommended Power Supply Filtering A power supply filtering is recommended for the transmitter and the receiver module. A possible filtering scheme is shown in Figure 9. The module signal and chassis ground refer to a common ground plane, which can be contacted to the PCB ground by the mounting screws (see Figure 14 “PCB Layout” on Page 25). L1 VCC VCC to PAROLI Tx or Rx Module 1 µH C1 22 µF C3 100 nF C2 100 nF Board Ground Plane Figure 9 File: 3330 Filtering Scheme Transmitter Module VCC Data In P internal P Rin/2 Rin/2 Data In N internal N VIN > 6 kΩ 1.95 V Figure 10 Data Sheet File: 3320 Transmitter - Input Stage 17 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Technical Data The electro-optical characteristics described in the following tables are valid only for use under the recommended operating conditions. Transmitter Electrical Characteristics Parameter Symbol Values min. Unit typ. max. Supply Current1) ICC 400 450 mA Power Consumption1) P 1.3 1.6 W Data Rate per Channel DR 1600 Mbit/s LVCMOS Output Voltage Low VLVCMOSOL VLVCMOSOH 2.5 ILVCMOSI –100 0.4 V LVCMOS Output Voltage High LVCMOS Input Current High/Low 500 2) V LVCMOS Output Current High 3) ILVCMOSOH LVCMOS Output Current Low 4) Data Differential Input Impedance 5) 1) 2) 3) 4) 5) ILVCMOSOL RIN 80 100 100 µA 0.5 mA 4.0 mA 120 Ω Measured at the recommended case temperature of Tcase = 45°C. For Tcase = 0°C a decrease of approximately 10% and for Tcase = 80°C an increase of approximately 15% can be expected. Specified for CID worst case pattern (disparity 72) or any pattern with a smaller disparity. The minimum data rate depends on the disparity of the used data pattern. For example, a regular clock signal (1-0 sequence) can be transmitted down to a data rate as low as 1 Mbit/s. Source current. Sink current. Data input stage. Data Sheet 18 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Technical Data Transmitter Electro-Optical Characteristics Parameter Symbol Values min. typ. Unit max. 200 ps Optical Fall Time 1) tR tF 200 ps Total Jitter 2), 3) TJ 0.284 UI Deterministic Jitter3), 4) DJ 0.1 UI Channel-to-channel skew 5) tCSK PAVG PSD 100 ps –8.0 –3.0 dBm –30.0 dBm λC 830 850 860 nm 0.35 0.65 nm –117 dB/Hz Optical Rise Time 1) Launched Average Power6) Launched Power Shutdown Center Wavelength 7) ∆λ 8) Spectral Width (rms) 9) Relative Intensity Noise RIN Extinction Ratio (dynamic) ER 6.0 Optical Modulation Amplitude 10), 11) OMA 0.19 12) –5.0 dB 0.46 13) mW to be defined 14) Eye mask compliance Electro-optical parameters valid for each channel and measured at the highest specified data rate. All optical parameters are measured with a 62.5 µm multimode fiber. 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) 12) 13) 14) 20% - 80% level, non filtered values. The Total Jitter (TJ) is composed of Random Jitter (RJ) and Deterministic Jitter (DJ) according to: TJ = RJ (14 Sigma value) + DJ. The TJ is specified at a BER of 10–12 from TP1 to TP2 according to IEEE 802.3, sec. 38.5. The RJ is measured at the 50% level of the optical signal as the mean of the rising and falling edge measurement value. UI (Unit Interval) is equal to the length of one bit. For example, 2.72 Gbit/s corresponds to 368 ps. The DJ consists of Duty Cycle Distortion and Data Dependent Jitter and is measured according to IEEE 802.3 using a K28.5 pattern. With input channel-to-channel skew 0 ps and a maximum data channel-to-channel average deviation and swing deviation of 5%. The specified output power is compliant with IEC 60825-1, Amendment 2, Class 1M Accessible Emission Limits (AEL). Wavelength is measured according to IEEE 802.3, sec. 38.6.1. Spectral width is measured according to IEEE 802.3, sec. 38.6.1. RIN is measured according to IEEE 802.3, sec. 38.6.4. Peak to peak values. OMA is defined as the difference of the optical high state (’1’) and the optical low state (’0’): OMA = Popt(’1’) – Popt(’0’). Corresponds to a minimum extinction ratio of 6 dB. Corresponds to a typical extinction ratio of 8 dB. GBE mask (IEEE 802.3, sec. 38.6.5.) adopted for data rate available. Data Sheet 19 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Technical Data VCC −RESET 3.6 V 3.135 V 2.0 V 0.8 V t3 Data data valid data invalid t1 t2 File: 3321 Figure 11 Timing Diagram Parameter Symbol Values min. Unit typ. max. –RESET on delay time t1 15 50 ms –RESET off delay time t2 100 500 ns –RESET low duration 1) t3 1) 10 µs Only when not used as power on reset. At any failure recovery, –RESET must be brought to low level for at least t3. Data Sheet 20 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Technical Data Receiver Electrical Characteristics Parameter Symbol Values min. Unit typ. max. Supply Current1) ICC 280 340 mA Power Consumption1) P 0.9 1.2 W LVDS Output Low Voltage2), 3) VLVDSOL LVDS Output High Voltage2), 3) VLVDSOH LVDS Output Differential Voltage2), 3), 4), 5) |VOD| 925 LVDS Output Offset Voltage2), 3), 6) VOS LVDS Rise/Fall Time 7) LVCMOS Output Voltage Low LVCMOS Output Voltage High mV 1475 mV 250 400 mV 1125 1275 mV 230 ps 400 mV tR-LVDS, tF-LVDS VLVCMOSOL VLVCMOSOH 2500 ILVCMOSI –100 mV 100 µA 0.5 mA LVCMOS Output Current Low 9) ILVCMOSOH ILVCMOSOL 4.0 mA Total Jitter 10), 11), 12), 13), 14) TJ 0.33 UI Deterministic Jitter 10), 13), 15) DJ 0.12 UI Channel-to-channel skew 16) tCSK 100 ps LVCMOS Input Current High/Low LVCMOS Output Current High 8) 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) 12) 13) 14) Typical value is measured at Tcase = 45°C and 3.3 V, maximum value is measured at Tcase = 80°C and 3.6 V. Output level diagram: see Figure 8 on Page 16. LVDS output must be terminated differentially with Rt. |VOD| = |(output voltage of non-inverted output minus output voltage of inverted output)|. Unused channels must be terminated by 50 Ω. VOS = 1/2 (output voltage of inverted output + output voltage of non-inverted output). Measured between 20% and 80% level with a maximum capacitive load of 3 pF. Source current. Sink current. With no optical input jitter. Measured with an optical input power of 3 dB above minimum receiver sensitivity. Unused channels can be terminated by 50 Ω or left open. UI (Unit Interval) is equal to the length of one bit. For example, 2.72 Gbit/s corresponds to 368 ps. The Total Jitter (TJ) is the sum from Random Jitter (RJ) and Deterministic Jitter (DJ) according to: TJ = RJ (14 Sigma value) + DJ. The TJ is specified at a BER of 10–12 from TP3 to TP4 according to IEEE 802.3, sec. 38.5. The RJ is measured at the 50% level of the optical signal as the mean of the rising and falling edge RJ measurement value. Data Sheet 21 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Technical Data 15) 16) The DJ consists of Duty Cycle Distortion and Data Dependent Jitter and is measured according to IEEE 802.3 using a K28.5 pattern. With input channel-to-channel skew 0 ps. Receiver Electro-Optical Characteristics Parameter Symbol Values Unit min. max. 5001) 1600 Mbit/s –16.0 dBm Data Rate Per Channel DR Sensitivity (Average Power)2) PIN Optical Modulation Amplitude 3) OMA 0.030 4) mW Saturation (Average Power)5) PSAT PSDA PSDD PSDA –PSDD –2.0 dBm ORL 12 Signal Detect Assert Level 6) Signal Detect Deassert Level 6) Signal Detect Hysteresis 6) Return Loss of Receiver 7) –17.0 –27.0 1.0 dBm dBm 4.0 dB dB Electro-optical parameters valid for each channel and measured at the highest specified data rate. All optical parameters are measured with a 62.5 µm multimode fiber. 1) 2) 3) 4) 5) 6) 7) Specified for CID worst case pattern (disparity 72) or any pattern with a smaller disparity. The minimum data rate depends on the disparity of the used data pattern. For example, a regular clock signal (1-0 sequence) can be received down to a data rate as low as 6 Mbit/s. Sensitivity is measured for BER = 10–12 with a Pseudo Random Bit sequence of length 223–1 (PRBS23) and a test pattern source with RIN of –117 dB/Hz or better. Sensitivity is specified for the worst case extinction ratio and maximum cross talk possibility. The maximum crosstalk possibility is defined as the “victim” receiver channel operating at its sensitivity limit and the neighboring channels operating at 6 dB higher incident optical power. Peak to peak value. Corresponds to a maximum sensitivity (average power) of –16.0 dBm at an extinction ratio of 6 dB. Saturation is specified with a Pseudo Random Bit sequence of length 223–1 (PRBS23) and ER ≥ 6 dB. PSDA: Average optical power when SD switches from inactive to active. PSDD: Average optical power when SD switches from active to inactive. Return loss is specified as the ration of the received optical power to the reflected optical power back into the link fiber. Data Sheet 22 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Technical Data Data Out 1, 12 t2 t1 Signal Detect 1 Signal Detect 12 File: 3325 2.0 V Output Enable OEN Data Out 0.8 V data valid data valid data Low t3 t4 File: 3326 Figure 12 Timing Diagrams Parameter Symbol Values min. Signal Detect Deassert Time Signal Detect Assert Time Output Enable off Delay Time Output Enable on Delay Time Data Sheet t1 t2 t3 t4 23 Unit typ. max. 3 10 µs 2 10 µs 14 20 µs 18 20 µs 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Technical Data Host Face-Plate Layout for Panel Accessed Modules F1 F2 F6 F3 F4 F9 F10 F11 F7 F12 F8 F5 File: 3507 Figure 13 Key Values Unit Comments mm Cutout center spacing min. typ. F1 18.42 20 F2 16.7 16.8 16.9 mm Cutout width F3 9.1 9.2 9.3 mm Cutout height F4 4.42 4.52 4.62 mm Center of cutout and center of receptacle to top of PCB F5 44.5 46 mm Face-plate placement 1 mm Radius mm Opt. reference plane to top of PCB mm Limitation for PCB length mm Length of receptacle mm Including shield, without spring contacts F6 F7 max. 4.25 F8 38 F9 16.8 F10 15.3 F11 7.6 F12 Data Sheet Including shield, without spring contacts 1.7 mm See Package Outlines Figure 15 on Page 28 24 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Technical Data Dimensions in mm Figure 14 File: 3508 PCB Layout 1. Figure 14 describes the recommended customer board layout for the PAROLI 2 modules. 2. The holes for the screwing leads and ground plates must be tied to signal ground. 3. Modules must be screwed on the 4 indicated positions (tightening torque should be typically 10 cNm). 4. Screw size for PCB or heat sink mounting = M1.6. 5. Screw length (PCB mounting) = PCB thickness + 5.2–0.5 mm. 6. Screw length (heat sink mounting) = heat sink thickness + 3.1–0.5 mm. 7. Modules can be mounted directly side by side. 8. The dashed lines in Figure 14 indicate the typical keep out area for straight MPO connectors as well as for the module MPO receptacle in case of central board placement of the module. Data Sheet 25 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Technical Data Thermal Characteristics The thermal behaviour of PAROLI modules (transmitter and receiver) depends on the operating conditions for different applications. The following table gives a guideline for system designers. T case – T ambient The thermal resistance Rth ( R th = ------------------------------------------ ; Pel = electrical power consumption) P el can be used for calculating the module case temperature under different operating conditions and is displayed for two different module options: a) Baseplate module without heat sink. b) Baseplate module with customer designed heat sink (e.g. height = 9 mm, length = 41 mm, width = 18 mm, no. of cooling fins = 9). Air Velocity1) 0 m/s 1.5 m/s 3 m/s 4 m/s Unit Rth - Option a) 23.3 10.3 8.6 7.5 K/W Rth - Option b) 20.0 5.2 4.2 4.0 K/W 1) The air velocity is applied along the shortest side of the module in parallel to the direction of the heat sinks. Link Length The link length calculations are based on the most conservative assumption of PAROLI modules working on their worst case specification limits. Multimode fibers of different types (modal bandwidth at 850 nm) are shown. The stated link length is valid under all specified operating conditions and includes 2 dB of additional connector loss. Fiber Type Diameter Core/Cladding [µm] Modal Bandwidth [MHz*km] Link Distance at 0.5 Gbit/s [m] Link Distance at 1.25 Gbit/s [m] Link Distance at 1.6 Gbit/s [m] 62.5 / 125 200 850 360 275 62.5 / 125 400 1300 640 490 Data Sheet 26 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Technical Data Channel Description Transmitter Module (front view as looking into the MPO connector receptacle of the module) Ch 12 Ch 11 Ch 10 Ch 9 Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 2 Ch 1 Host PCB below Receiver Module (front view as looking into the MPO connector receptacle of the module) Ch 12 Ch 11 Ch 10 Ch 9 Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Host PCB below The MPO connector provides a keying functionality, which requires a 180 degree twist of fiber cable, if used as a direct connection between transmitter and receiver module. (For example the transmitter channel 1 is directly connected to the receiver cannel 1). Handling Instructions Washing Process The PAROLI mating BGA connector can be handled according to standard industry wave solder, hand solder and washing processes. The PAROLI modules shall not be washed, due to possible influence on module performance. Dust Cover The optical connector is provided with a dust cover, which protects the optical interface from potential damage and contamination from dust during handling. The dust cover should always remain in the module, when no connector is used. Data Sheet 27 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Package Outlines Package Outlines PAROLI 2 Tx Temperature Reference Point on top of the module PAROLI 2 Rx Temperature Reference Point on top of the module Typical module mass approximately 10.4 grams The front collar EMI shield is electrically separated from module signal ground Dimensions in mm File: 3203 Figure 15 Data Sheet 28 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Ordering Information Ordering Information Part Number Description V23832-T2531-M101 PAROLI Transmitter, 12 x 1.25 Gbit/s, multistandard electrical interface V23832-T2131-M101 PAROLI Transmitter, 12 x 1.6 Gbit/s, multistandard electrical interface V23832-T2431-M101 PAROLI Transmitter, 12 x 2.7 Gbit/s, multistandard electrical interface V23832-T2331-M101 PAROLI Transmitter, 12 x 3.125 Gbit/s, multistandard electrical interface V23832-R521-M101 PAROLI Receiver, 12 x 1.25 Gbit/s, LVDS electrical interface V23832-R121-M101 PAROLI Receiver, 12 x 1.6 Gbit/s, LVDS electrical interface V23832-R421-M101 PAROLI Receiver, 12 x 2.7 Gbit/s, LVDS electrical interface V23832-R321-M101 PAROLI Receiver, 12 x 3.125 Gbit/s, LVDS electrical interface V23832-R511-M101 PAROLI Receiver, 12 x 1.25 Gbit/s, CML electrical interface V23832-R111-M101 PAROLI Receiver, 12 x 1.6 Gbit/s, CML electrical interface V23832-R411-M101 PAROLI Receiver, 12 x 2.7 Gbit/s, CML electrical interface V23832-R311-M101 PAROLI Receiver, 12 x 3.125 Gbit/s, CML electrical interface Data Sheet 29 2003-11-19 V23832-T2131-M101 V23832-R121-M101 Revision History: 2003-11-19 Previous Version: 2003-05-21 Page DS2 Subjects (major changes since last revision) Document completely revised Edition 2003-11-19 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany © Infineon Technologies AG 2003. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.