INTEGRATED CIRCUITS DATA SHEET UDA1341TS Economy audio CODEC for MiniDisc (MD) home stereo and portable applications Preliminary specification File under Integrated Circuits, IC22 1998 Dec 18 Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications CONTENTS 1 1.1 1.2 1.3 1.4 FEATURES General Multiple format data interface DAC digital sound processing Advanced audio configuration 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 QUICK REFERENCE DATA 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 System clock Pin compatibility Analog front end Programmable Gain Amplifier (PGA) Analog-to-Digital Converter (ADC) Digital Automatic Gain Control (AGC) AGC status detection Digital mixer Decimation filter (ADC) Overload detection (ADC) Mute (ADC) Interpolation filter (DAC) Peak detector Quick mute Noise shaper (DAC) Filter Stream Digital-to-Analog Converter (FSDAC) Multiple format input/output interface L3-interface Address mode Data transfer mode Programming the sound processing and other features STATUS control Reset System clock frequency DC-filter Data input format Output gain switch Input gain switch Polarity of ADC Polarity of DAC Double speed 7.17 7.18 7.19 7.20 7.21 7.21.1 7.21.1.1 7.21.1.2 7.21.1.3 7.21.1.4 7.21.1.5 7.21.1.6 7.21.1.7 7.21.1.8 7.21.1.9 1998 Dec 18 2 UDA1341TS 7.21.1.10 7.21.2 7.21.2.1 7.21.2.2 7.21.2.3 7.21.2.4 7.21.2.5 7.21.2.6 7.21.2.7 7.21.3 7.21.3.1 7.21.3.2 7.21.3.3 7.21.3.4 7.21.3.5 7.21.3.6 7.21.3.7 7.21.4 7.21.4.1 Power control DATA0 direct control Volume control Bass boost Treble Peak detection position De-emphasis Mute Mode DATA0 extended programming registers Mixer gain control MIC sensitivity Mixer mode AGC control AGC output level Input channel 2 amplifier gain AGC time constant DATA1 control Peak level value 8 LIMITING VALUES 9 THERMAL CHARACTERISTICS 10 DC CHARACTERISTICS 11 AC CHARACTERISTICS (ANALOG) 12 AC CHARACTERISTICS (DIGITAL) 13 APPLICATION INFORMATION 14 PACKAGE OUTLINE 15 SOLDERING 15.1 15.2 15.3 15.4 Introduction Reflow soldering Wave soldering Repairing soldered joints 16 DEFINITIONS 17 LIFE SUPPORT APPLICATIONS Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications 1 UDA1341TS FEATURES 1.1 General • Low power consumption • 3.0 V power supply • 256fs, 384fs or 512fs system clock frequencies (fsys) • Small package size (SSOP28) • Partially pin compatible with UDA1340M and UDA1344TS • Optional differential input configuration for enhanced ADC sound quality • Fully integrated analog front end including digital AGC • ADC plus integrated high-pass filter to cancel DC offset • Stereo line output (under microcontroller volume control) • ADC supports 2 V (RMS value) input signals • Digital peak level detection • Overload detector for easy record level control • High linearity, dynamic range and low distortion. • Separate power control for ADC and DAC • No analog post filter required for DAC • Easy application 2 • Functions controllable via L3-interface. The UDA1341TS is a single-chip stereo Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with signal processing features employing bitstream conversion techniques. Its fully integrated analog front end, including Programmable Gain Amplifier (PGA) and a digital Automatic Gain Control (AGC). Digital Sound Processing (DSP) featuring makes the device an excellent choice for primary home stereo MiniDisc applications, but by virtue of its low power and low voltage characteristics it is also suitable for portable applications such as MD/CD boomboxes, notebook PCs and digital video cameras. 1.2 • Multiple format data interface I2S-bus, MSB-justified and LSB-justified format compatible • Three combinational data formats with MSB data output and LSB 16, 18 or 20 bits data input • 1fs input and output format data rate. 1.3 DAC digital sound processing The UDA1341TS is similar to the UDA1340M and the UDA1344TS but adds features such as digital mixing of two input signals and one channel with a PGA and a digital AGC. • Digital dB-linear volume control (low microcontroller load) • Digital tone control, bass boost and treble • Digital de-emphasis for 32, 44.1 or 48 kHz audio sample frequencies (fs) The UDA1341TS supports the I2S-bus data format with word lengths of up to 20 bits, the MSB-justified data format with word lengths of up to 20 bits, the LSB-justified serial data format with word lengths of 16, 18 and 20 bits and three combinations of MSB data output combined with LSB 16, 18 and 20 bits data input. The UDA1341TS has DSP features in playback mode like de-emphasis, volume, bass boost, treble and soft mute, which can be controlled via the L3-interface with a microcontroller. • Soft mute. 1.4 Advanced audio configuration • DAC and ADC polarity control • Two channel stereo single-ended input configuration • Microphone input with on-board PGA 3 GENERAL DESCRIPTION ORDERING INFORMATION TYPE NUMBER UDA1341TS 1998 Dec 18 PACKAGE NAME DESCRIPTION VERSION SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1 3 Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications 4 UDA1341TS QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA(ADC) ADC analog supply voltage 2.4 3.0 3.6 V VDDA(DAC) DAC analog supply voltage 2.4 3.0 3.6 V VDDD digital supply voltage IDDA(ADC) ADC analog supply current IDDA(DAC) DAC analog supply current IDDD digital supply current Tamb operating ambient temperature 2.4 3.0 3.6 V operation mode − 12.5 − mA ADC power-down − 6.0 − mA operation mode − 7.0 − mA DAC power-down − 50 − µA operation mode − 7.0 − mA −20 − +85 °C − 1.0 − V 0 dB − −85 −80 dB −60 dB; A-weighted − −37 −33 dB 0 dB − −90 −85 dB −60 dB; A-weighted − −40 −36 dB Analog-to-digital converter Vi(rms) input voltage (RMS value) (THD + N)/S total harmonic distortion-plus-noise to signal ratio notes 1 and 2 stand-alone mode double differential mode S/N αcs signal-to-noise ratio Vi = 0 V; A-weighted stand-alone mode − 97 − dB double differential mode − 100 − dB − 100 − dB 0 dB − −85 − dB −60 dB; A-weighted − −37 − dB − 95 − dB channel separation Programmable gain amplifier (THD + N)/S total harmonic distortion-plus-noise to signal ratio 1 kHz; fs = 44.1 kHz S/N Vi = 0 V; A-weighted signal-to-noise ratio Digital-to-analog converter Vo(rms) output voltage (RMS value) supply voltage = 3 V; note 3 − 900 − mV (THD+N)/S total harmonic distortion-plus-noise to signal ratio 0 dB − −91 −86 dB −60 dB; A-weighted − −40 − dB S/N signal-to-noise ratio code = 0; A-weighted − 100 − dB αcs channel separation − 100 − dB Notes 1. The ADC inputs can be used in a 2 V (RMS value) input signal configuration when a resistor of 12 kΩ is used in series with the inputs and 1 or 2 V (RMS value) input signal operation can be selected via the Input Gain Switch (IGS). 2. The ADC input signal scales inversely proportional with the power supply voltage. 3. The DAC output voltage scales linear with the DAC analog supply voltage. 1998 Dec 18 4 Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications 5 UDA1341TS BLOCK DIAGRAM VDDA(ADC) handbook, full pagewidth VSSA(ADC) 3 VINL2 VDDD 1 VSSD 10 VADCN 7 11 5 6 8 PGA 2 ADC2 0 dB/6 dB SWITCH 4 0 dB/6 dB SWITCH ADC1 VINR1 ADC1 22 UDA1341TS VINR2 PGA ADC2 VINL1 VADCP DIGITAL AGC AGCSTAT DIGITAL MIXER 9 DECIMATION FILTER DATAO BCK WS DATAI 18 13 16 DIGITAL INTERFACE 17 L3-BUS INTERFACE 15 19 12 DSP FEATURES QMUTE 23 INTERPOLATION FILTER 20 28 21 DAC VOUTL L3CLOCK L3DATA SYSCLK TEST1 TEST2 DAC 26 24 25 VOUTR 27 VDDA(DAC) VSSA(DAC) Fig.1 Block diagram. 1998 Dec 18 L3MODE PEAK DETECTOR NOISE SHAPER Vref 14 OVERFL 5 MGR427 Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications 6 UDA1341TS PINNING SYMBOL PIN SYMBOL DESCRIPTION PIN DESCRIPTION VSSA(ADC) 1 ADC analog ground L3DATA 15 L3-bus data input and output VINL1 2 ADC1 input left BCK 16 bit clock input VDDA(ADC) 3 ADC analog supply voltage WS 17 word select input VINR1 4 ADC1 input right DATAO 18 data output VADCN 5 ADC negative reference voltage DATAI 19 data input VINL2 6 ADC2 input left TEST1 20 test control 1 (pull-down) VADCP 7 ADC positive reference voltage TEST2 21 test control 2 (pull-down) 22 AGC status 23 quick mute input VINR2 8 ADC2 input right AGCSTAT OVERFL 9 decimation filter overflow output QMUTE VDDD 10 digital supply voltage VOUTR 24 DAC output right 25 DAC analog supply voltage VSSD 11 digital ground VDDA(DAC) SYSCLK 12 system clock 256fs, 384fs or 512fs VOUTL 26 DAC output left L3MODE 13 L3-bus mode input VSSA(DAC) 27 DAC analog ground L3CLOCK 14 L3-bus clock input Vref 28 ADC and DAC reference voltage handbook, halfpage handbook, halfpage 27 VSSA(DAC) VINL1 2 VDDA(ADC) 3 27 VSSA(DAC) VINL1 2 VDDA(ADC) 3 26 VOUTL 25 VDDA(DAC) VINR1 4 28 Vref VSSA(ADC) 1 28 Vref VSSA(ADC) 1 26 VOUTL 25 VDDA(DAC) VINR1 4 VADCN 5 24 VOUTR VADCN 5 24 VOUTR VINL2 6 23 QMUTE VINL2 6 23 QMUTE VADCP 7 VADCP 7 22 AGCSTAT 22 AGCSTAT UDA1341TS UDA1341TS VINR2 8 21 TEST2 VINR2 8 21 TEST2 OVERFL 9 20 TEST1 OVERFL 9 20 TEST1 VDDD 10 19 DATAI VDDD 10 19 DATAI VSSD 11 18 DATAO VSSD 11 18 DATAO SYSCLK 12 17 WS SYSCLK 12 17 WS L3MODE 13 16 BCK L3MODE 13 16 BCK L3CLOCK 14 L3CLOCK 14 15 L3DATA 15 L3DATA MGR429 MGR428 Marked pins are compatible with UDA1340M Fig.2 Pin configuration. 1998 Dec 18 Fig.3 Compatible pins with UDA1340M. 6 Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications 7 FUNCTIONAL DESCRIPTION 7.1 7.5 7.6 Pin compatibility Analog front end The analog front end of the UDA1341TS consists of two stereo ADCs with a Programmable Gain Amplifier (PGA) in channel 2. The PGA is intended to pre-amplify a microphone signal applied to the input channel 2. 7.7 7.8 INPUT GAIN SWITCH Present 0 dB 2 V (RMS value) input signal; note 1 Present 6 dB 1 V (RMS value) input signal Absent 0 dB 1 V (RMS value) input signal Absent 6 dB 0.5 V (RMS value) input signal • ADC1 only mode (for line input); input channel 2 is off • ADC2 only mode, including PGA and digital AGC (for microphone input); input channel 1 is off MAXIMUM INPUT VOLTAGE • ADC1 + ADC2 mixer mode, including PGA and AGC • ADC1 and ADC2 double differential mode (improved ADC performance). Important: In order to prevent crosstalk between the line inputs no signal should be applied to the microphone input in the double differential mode. In all modes (except the double differential mode) a reference voltage is always present at the input of the ADC. However, in the double differential mode there is no reference voltage present at the microphone input. Note 1. If there is no need for 2 V (RMS value) input signal support, the external resistor should not be used. 7.4 In the mixer mode, the output signals of both ADCs in channel 1 and channel 2 (after the digital AGC) can be mixed with coefficients that can be set via the L3-interface. The range of the mixer coefficients is from 0 to −∞ dB in 1.5 dB steps. Programmable Gain Amplifier (PGA) The PGA can be set via the L3-interface at the gain settings: −3, 0, 3, 9, 15, 21 or 27 dB. 1998 Dec 18 Digital mixer The two stereo ADCs (including the AGC) can be used in four modes: Application modes using input gain stage RESISTOR (12 kΩ) AGC status detection The AGCSTAT signal from the digital AGC is HIGH when the gain level of the AGC is below 8 dB. This signal can be used to give the PGA a new gain setting via the L3-interface and to power e.g. a LED. Input channel 1 has a selectable 0 or 6 dB gain stage, to be controlled via the L3-interface. In this way, input signals of 1 V (RMS value) or 2 V (RMS value) e.g. from a CD source can be supported using an external resistor of 12 kΩ in series with the input channel 1. The application modes are given in Table 1. Table 1 Digital Automatic Gain Control (AGC) Input channel 2 has a digital AGC to compress the dynamic range when a microphone signal is applied to input channel 2. The digital AGC can be switched on and off via the L3-interface. In the on state the AGC compresses the dynamic range of the input signal of input channel 2. Via the L3-interface the user can set the parameters of the AGC: attack time, decay time and output level. When the AGC is set off via the L3-interface, the gain of input channel 2 can be set manually. In this case the gain of the PGA and digital AGC are combined. The range of the gain of the input channel 2 is from −3 to +60.5 dB in steps of 0.5 dB. The UDA1341TS is partially pin compatible with the UDA1340M and UDA1344TS, making an upgrade of a printed-circuit board from UDA1340M to UDA1341TS easier. The pins that are compatible with the UDA1340M are marked in Fig.3. 7.3 Analog-to-Digital Converter (ADC) The stereo ADC of the UDA1341TS consists of two 3rd-order Sigma-Delta modulators. They have a modified Ritchie-coder architecture in a differential switched capacitor implementation. The over-sampling ratio is 128. System clock The UDA1341TS accommodates slave mode only, this means that in all applications the system devices must provide the system clock. The system frequency is selectable. The options are 256fs, 384fs or 512fs. The system clock must be locked in frequency to the digital interface signals. 7.2 UDA1341TS 7 Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications 7.9 The peak level detector is implemented as a peak-hold detector, which means that the highest sound level is hold until the peak level is read out via the L3-interface. After read-out the peak level registers are reset. Decimation filter (ADC) The decimation from 128fs is performed in two stages. sin x The first stage realizes 3rd order ------------ characteristic, x decimating by 16. The second stage consists of 3 half-band filters, each decimating by a factor of 2. Table 2 7.14 CONDITIONS Quick mute A hard mute can be activated via the static pin QMUTE. When QMUTE is set HIGH, the output signal is instantly muted to zero. Setting QMUTE to LOW, the mute is instantly in-activated. Decimation filter characteristics ITEM UDA1341TS VALUE (dB) Passband ripple 0 to 0.45fs ±0.05 7.15 Stop band >0.55fs −60 Dynamic range 0 to 0.45fs 108 Overall gain input channel 1; 0 dB input −1.16 The 3rd-order noise shaper operates at 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique allows for high signal-to-noise ratios. The noise shaper output is converted into an analog signal using a filter stream digital-to-analog converter. 7.10 Noise shaper (DAC) Overload detection (ADC) 7.16 This name is convenient but a little inaccurate. In practice the output is used to indicate whenever that output data, in either the left or right channel, is bigger than −1 dB (actual figure is −1.16 dB) of the maximum possible digital swing. If this condition is detected the OVERFL output is forced HIGH for at least 512fs cycles (11.6 ms at fs = 44.1 kHz). This time-out is reset for each infringement. Filter Stream Digital-to-Analog Converter (FSDAC) On recovery from power-down or switching on of the system clock, the serial data output DATAO is held LOW until valid data is available from the decimation filter. The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. 7.12 7.17 7.11 Mute (ADC) Interpolation filter (DAC) The UDA1341TS supports the following data formats: The digital filter interpolates from 1fs to 128fs by means of a cascade of a recursive filter and a Finite Impulse Response (FIR) filter. Table 3 • MSB-justified serial format with word length up to 20 bits • LSB-justified serial format with word length of 16, 18 or 20 bits CONDITIONS VALUE (dB) Passband ripple 0 to 0.45fs ±0.03 Stop band >0.55fs −50 Dynamic range 0 to 0.45fs 108 7.13 • I2S-bus with word length up to 20 bits Interpolation filter characteristics ITEM • MSB data output with LSB 16, 18 or 20 bits input. Left and right data-channel words are time multiplexed. The formats are illustrated in Fig.4. The UDA1341TS allows for double speed data monitoring purposes. In this case the sound features bass boost, treble and de-emphasis cannot be used. However, volume control and soft-mute can still be controlled. The double speed monitoring option can be set via the L3-interface. Peak detector In the playback path a peak level detector is build in. The position of the peak detection can be set via the L3-interface to either before or after the sound features. 1998 Dec 18 Multiple format input/output interface The bit clock frequency must be 64 times word select frequency or less, so fBCK ≤ 64 × fWS. 8 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... RIGHT >=8 3 1 2 3 BCK DATA MSB B2 LSB MSB >=8 B2 LSB MSB INPUT FORMAT I2S-BUS LEFT WS 1 2 RIGHT >=8 3 1 2 LSB MSB B2 >=8 3 BCK DATA MSB B2 LSB MSB B2 MSB-JUSTIFIED FORMAT WS RIGHT LEFT 16 15 2 1 16 B15 LSB MSB 15 2 1 BCK MSB DATA B2 B2 B15 LSB 9 LSB-JUSTIFIED FORMAT 16 BITS WS RIGHT LEFT 18 Philips Semiconductors 2 Economy audio CODEC for MiniDisc (MD) home stereo and portable applications 1 ook, full pagewidth 1998 Dec 18 LEFT WS 17 16 15 2 1 18 B17 LSB MSB 17 16 15 2 1 B17 LSB 2 1 BCK DATA MSB B2 B3 B4 B2 B3 B4 LSB-JUSTIFIED FORMAT 18 BITS WS LEFT 20 19 18 RIGHT 17 16 15 1 20 B19 LSB MSB 19 18 17 16 15 BCK MSB B2 B3 B4 B5 B6 B2 B3 B4 B5 B6 B19 LSB MGG841 LSB-JUSTIFIED FORMAT 20 BITS Fig.4 Serial interface formats. UDA1341TS DATA Preliminary specification 2 Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications 7.18 UDA1341TS The address mode is required to select a device communicating via the L3-bus and to define the destination registers for the data transfer mode. L3-interface The UDA1341TS has a microcontroller input mode. In the microcontroller mode, all the digital sound processing features and the system controlling features can be controlled by the microcontroller. Data transfer can be in both directions: input to the UDA1341TS to program its sound processing and system controlling features and output from the UDA1341TS to provide the peak level value. The controllable features are: • Reset • System clock frequency 7.19 • Power control The address mode is used to select a device for subsequent data transfer and to define the destination registers. The address mode is characterized by L3MODE being LOW and a burst of 8 pulses on L3CLOCK, accompanied by 8 data bits. The fundamental timing is shown in Fig.5. • DAC gain switch • ADC input gain switch • ADC/DAC polarity control • Double speed playback • De-emphasis Address mode Data bits 7 to 2 represent a 6-bit device address, with bit 7 being the MSB and bit 2 the LSB. The address of the UDA1341TS is 000101. • Volume • Mode switch Data bits 0 to 1 indicate the type of the subsequent data transfer as shown in Table 4. • Bass boost • Treble In the event that the UDA1341TS receives a different address, it will deselect its microcontroller interface logic. • Mute • MIC sensitivity control • AGC control 7.20 • Input amplifier gain control Data transfer mode The selection activated in the address mode remains active during subsequent data transfers, until the UDA1341TS receives a new address command. • Digital mixer control • Peak detection position. Via the L3-interface the peak level value of the signal in the DAC path can be read out from the UDA1341TS to the microcontroller. The fundamental timing of data transfers is essentially the same as the timing in the address mode and is given in Fig.6. The exchange of data and control information between the microcontroller and the UDA1341TS is accomplished through a serial hardware L3-interface comprising the following pins: • L3MODE: microcontroller interface mode line Note that ‘L3DATA write’ denotes data transfer from the microcontroller to the UDA1341TS and ‘L3DATA peak read’ denotes data transfer in the opposite direction. The maximum input clock and data rate is 64fs. All transfers are byte-wise, i.e. they are based on groups of 8 bits. Data will be stored in the UDA1341TS after the eighth bit of a byte has been received. • L3CLOCK: microcontroller interface clock line. A multibyte transfer is illustrated in Fig.7. • L3DATA: microcontroller interface data line Information transfer through the microcontroller bus is organized in accordance with the so called ‘L3’ format, in which two different modes of operation can be distinguished: address mode and data transfer mode. 1998 Dec 18 10 Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications Table 4 Selection of data transfer BIT 1 BIT 0 0 UDA1341TS 0 MODE DATA0 TRANSFER direct addressing registers: volume, bass boost, treble, peak detection position, de-emphasis, mute and mode extended addressing registers: digital mixer control, AGC control, MIC sensitivity control, input gain, AGC time constant and AGC output level 0 1 DATA1 1 0 STATUS reset, system clock frequency, data input format, DC-filter, input gain switch, output gain switch, polarity control, double speed and power control peak level value read-out (information from UDA1341TS to microcontroller) 1 1 not used handbook, full pagewidth L3MODE tsu(L3)A th(L3)A tCLK(L3)L tsu(L3)A tCLK(L3)H th(L3)A L3CLOCK Tcy(CLK)(L3) tsu(L3)DA L3DATA th(L3)DA BIT 7 BIT 0 MGR431 Fig.5 Timing address mode. 1998 Dec 18 11 Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications UDA1341TS tstp(L3) handbook, full pagewidth tstp(L3) L3MODE tCLK(L3)L th(L3)D Tcy(CLK)L3 tCLK(L3)H tsu(L3)D L3CLOCK th(L3)DA L3DATA write tsu(L3)DA th(L3)DA BIT 0 BIT 7 L3DATA read PL0 PL1 PL2 PL3 PL4 PL5 MGR430 Fig.6 Timing for data transfer mode. tstp(L3) handbook, full pagewidth L3MODE L3CLOCK L3DATA address data byte #1 data byte #2 Fig.7 Multibyte transfer. 1998 Dec 18 12 address MGR432 Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications 7.21 • DATA0 Programming the sound processing and other features There are two addressing modes: direct addressing mode and extended addressing mode. The sound processing and other feature values are stored in independent registers. Direct addressing mode is using the 2 MSB bits of the data byte. Via this addressing mode the features volume, bass boost, treble, peak position, de-emphasis, mute, and mode can be controlled directly. The first selection of the registers is achieved by the choice of data type that is transferred. This is performed in the address mode using bit 0 and bit 1 (see Table 4). The second selection is performed by the 2 or 3 MSBs of the data byte (bits 7 and 6 or bits 7, 6 and 5). The other bits in the data byte (bits 5 to 0 or bits 4 to 0) represent the value that is placed in the selected registers. Extended addressing mode is provided for controlling the features digital mixer, AGC control, MIC sensitivity, input gain, AGC time constants, and AGC output level. An extended address can be set via the EA registers (3 bits). The data in the extended registers can be set by writing data to the ED registers (5 bits). For the UDA1341TS the following modes can be selected: • STATUS • DATA1 In this mode the features reset, system clock frequency, data input format, DC-filter, input gain switch, output gain switch, polarity control, double speed and power control can be controlled. Table 5 UDA1341TS In this mode the detected peak level value can be read out. Default settings SYMBOL FEATURE SETTING OR VALUE Status OGS Output gain switch 0 dB IGS Input gain switch 0 dB PAD Polarity of ADC non-inverting PDA Polarity of DAC non-inverting DS Double speed single speed PC Power control ADC and DAC on Direct control VC Volume control 0 dB BB Bass boost 0 dB TR Treble 0 dB PP Peak detection position after the tone features DE De-emphasis no de-emphasis MT Mute no mute M Mode switch flat Extended programming MA Mixer gain channel 1 −6 dB MB Mixer gain channel 2 −6 dB MS MIC sensitivity 0 dB MM Mixer mode switch double differential AG AGC control disable AGC AT AGC attack and decay time 11 ms and100 ns AL AGC output level −9 dB FS 1998 Dec 18 13 Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications 7.21.1 Table 6 UDA1341TS STATUS CONTROL Data transfer of type ‘STATUS’ BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 RST SC1 SC0 IF2 IF1 IF0 DC REGISTER SELECTED RST = reset SC = system clock frequency (2 bits) IF = data input format (3 bits) DC = DC-filter 1 OGS IGS PAD PDA DS PC1 PC0 OGS = output gain (6 dB) switch IGS = input gain (6 dB) switch PAD = polarity of ADC PDA = polarity of DAC DS = double speed PC = power control (2 bits) 7.21.1.1 Reset 7.21.1.4 A 1-bit value to initialize the L3-registers with the default settings except system clock frequency. Data input format A 3-bit value to select the data input format. Table 10 Data input format settings Table 7 Reset settings RST IF2 IF1 IF0 FUNCTION FUNCTION 0 0 0 I2S-bus 0 no reset 0 0 1 LSB-justified 16 bits 1 reset 0 1 0 LSB-justified 18 bits 0 1 1 LSB-justified 20 bits 1 0 0 MSB-justified 1 0 1 LSB-justified 16 bits input and MSB-justified output 1 1 0 LSB-justified 18 bits input and MSB-justified output 1 1 1 LSB-justified 20 bits input and MSB-justified output 7.21.1.2 System clock frequency A 2-bit value to select the used external clock frequency. Table 8 System clock settings SC1 SC0 FUNCTION 0 0 512fs 0 1 384fs 1 0 256fs 1 1 not used 7.21.1.3 DC-filter A 1-bit value to enable the digital DC-filter. Table 9 DC-filtering settings DC FUNCTION 0 no DC-filtering 1 DC-filtering 1998 Dec 18 14 Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications 7.21.1.5 Output gain switch UDA1341TS 7.21.1.9 Double speed A 1-bit value to control the DAC output gain switch. The default setting is given in Table 5. A 1-bit value to enable the double speed playback. The default setting is given in Table 5. Table 11 Gain switch of DAC settings Table 15 Double speed settings OGS GAIN OF DAC DS 0 0 dB 0 single speed playback 1 6 dB 1 double speed playback 7.21.1.6 Input gain switch FUNCTION 7.21.1.10 Power control A 1-bit value to control the ADC input gain switch. The default setting is given in Table 5. A 2-bit value to disable the ADC and/or DAC to reduce power consumption. The default setting is given in Table 5. Table 12 Gain switch of ADC settings IGS GAIN OF ADC 0 0 dB 1 6 dB 7.21.1.7 Table 16 Power control settings FUNCTION PC1 ADC Polarity of ADC A 1-bit value to control the ADC polarity. The default setting is given in Table 5. Table 13 Polarity control of ADC settings PAD POLARITY OF ADC 0 non-inverting 1 inverting 7.21.1.8 Polarity of DAC A 1-bit value to control the DAC polarity. The default setting is given in Table 5. Table 14 Polarity control of DAC settings PDA POLARITY OF DAC 0 non-inverting 1 inverting 1998 Dec 18 PC0 15 DAC 0 0 off off 0 1 off on 1 0 on off 1 1 on on Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications 7.21.2 UDA1341TS DATA0 DIRECT CONTROL Table 17 Data transfer of type ‘DATA0’ BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 VC5 VC4 VC3 VC2 VC1 VC0 0 1 BB3 BB2 BB1 BB0 TR1 TR0 REGISTER SELECTED VC = volume control (6 bits) BB = bass boost (4 bits) TR = treble (2 bits) 1 0 PP DE1 DE0 MT M1 M0 PP = peak detection position DE = de-emphasis (2 bits) MT = mute M = mode switch (2 bits) 1 1 0 0 0 EA2 EA1 EA0 EA = extended address (3 bits) 1 1 1 ED4 ED3 ED2 ED1 ED0 ED = extended data (5 bits) 7.21.2.1 Volume control 7.21.2.2 Bass boost A 6-bit value to program the left and right channel volume attenuation. The range is from 0 to −∞ dB in steps of 1 dB. The default setting is given in Table 5. A 4-bit value to program the bass boost settings. The used set depends on the mode bits. The default setting is given in Table 5. Table 18 Volume settings Table 19 Bass boost settings VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB) 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 −1 0 0 0 0 0 0 0 1 1 −2 0 0 : : : : : : : 0 1 1 1 0 1 1 −58 1 1 1 1 0 0 −59 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1998 Dec 18 BASS BOOST BB3 BB2 BB1 BB0 FLAT (dB) MIN. (dB) MAX. (dB) 0 0 0 0 1 0 2 2 1 0 0 4 4 0 1 1 0 6 6 0 1 0 0 0 8 8 0 1 0 1 0 10 10 −60 0 1 1 0 0 12 12 0 −∞ 0 1 1 1 0 14 14 1 −∞ 1 0 0 0 0 16 16 1 0 0 1 0 18 18 1 0 1 0 0 18 20 1 0 1 1 0 18 22 1 1 0 0 0 18 24 1 1 0 1 0 18 24 1 1 1 0 0 18 24 16 Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications 7.21.2.3 Treble UDA1341TS 7.21.2.6 A 2-bit value to program the treble setting. The used set depends on the mode bits. The default setting is given in Table 5. Mute A 1-bit value to enable the digital mute. The default setting is given in Table 5. Table 23 Mute settings Table 20 Treble settings MT TREBLE FUNCTION 0 no mute 1 mute TR1 TR0 FLAT (dB) MIN. (dB) MAX. (dB) 0 0 0 0 0 7.21.2.7 0 1 0 2 2 1 0 0 4 4 1 1 0 6 6 A 2-bit value to program the mode of the sound processing filters of bass boost and treble. The default setting is given in Table 5. 7.21.2.4 Table 24 Mode filter switch settings Peak detection position A 1-bit value to control the position of the peak level detector in the signal processing path. The default setting is given in Table 5. Table 21 Peak detection position settings PP FUNCTION 0 before tone features 1 after tone features 7.21.2.5 De-emphasis A 2-bit value to enable the digital de-emphasis filter. The default setting is given in Table 5. Table 22 De-emphasis settings DE1 DE0 0 0 no de-emphasis 0 1 de-emphasis: 32 kHz 1 0 de-emphasis: 44.1 kHz 1 1 de-emphasis: 48 kHz 1998 Dec 18 Mode FUNCTION 17 M1 M0 FUNCTION 0 0 flat 0 1 minimum 1 0 minimum 1 1 maximum Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications 7.21.3 UDA1341TS DATA0 EXTENDED PROGRAMMING REGISTERS Table 25 Extended control registers EA2 EA1 EA0 ED4 ED3 ED2 ED1 ED0 REGISTER SELECTED 0 0 0 MA4 MA3 MA2 MA1 MA0 MA = mixer gain channel 1 (5 bits) 0 0 1 MB4 MB3 MB2 MB1 MB0 MB = mixer gain channel 2 (5 bits) 0 1 0 MS2 MS1 MS0 MM1 MM0 MS = MIC sensitivity (3 bits) MM = mixer mode (2 bits) 1 0 0 AG 0 0 IG1 IG0 AG = AGC control IG = input amplifier gain channel 2 (2 bits) 1 0 1 IG6 IG5 IG4 IG3 IG2 IG = input amplifier gain channel 2 (5 bits) 1 1 0 AT2 AT1 AT0 AL1 AL0 AT = AGC time constant (3 bits) AL = AGC output level (2 bits) Programming via extended addressing is done by first sending a DATA0 data byte EA (3 bits) which specifies the addresses of the extended register followed by a DATA0 data byte which specifies the contents of the extended data register (5 bits). The EA extended addresses and names of the extended data registers are given in Table 25. 7.21.3.1 7.21.3.2 A 3-bit value to program eight gain settings of the microphone amplifier. These settings are valid only when AGC control is enabled and not in the double differential mode. The default setting is given in Table 5. Table 27 MIC sensitivity settings Mixer gain control MS2 MS1 MS0 Two 5-bit values to program the channel 1 (MA) and channel 2 (MB) coefficients in the mixer mode. The range is from 0 to −∞ dB in steps of 1.5 dB. The default settings are given in Table 5. Table 26 Mixer gain control channel 1 and channel 2 settings MA4 MA3 MA2 MA1 MA0 MB4 MB3 MB2 MB1 MB0 MIXER GAIN (dB) 0 0 0 0 0 0 0 0 0 0 1 −1.5 0 0 0 1 0 −3.0 : : : : : : 1 1 1 0 1 −43.5 1 1 1 1 0 −45.0 1 1 1 1 1 −∞ 1998 Dec 18 MIC sensitivity 18 MIC AMPLIFIER GAIN (dB) 0 0 0 −3 0 0 1 0 0 1 0 +3 0 1 1 +9 1 0 0 +15 1 0 1 +21 1 1 0 +27 1 1 1 not used Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications 7.21.3.3 Mixer mode UDA1341TS 7.21.3.6 Input channel 2 amplifier gain A 2-bit value to program the mode of the digital mixer. There are four modes: double differential, input channel 1 select, input channel 2 select and digital mixer mode. The default setting is given in Table 5. A 7-bit value to program the input channel 2 amplifier gain. The range is from −3 to +60.5 dB in steps of 0.5 dB. These settings are only valid when AGC control is disabled and not valid in the double differential mode. Table 28 Mixer mode switch settings Table 31 Input channel 2 amplifier gain settings MM1 MM0 FUNCTION 0 0 double differential mode 0 1 input channel 1 select (input channel 2 off) 1 0 input channel 2 select (input channel 1 off) 1 1 digital mixer mode (input 1 × MA + input 2 × MB) 7.21.3.4 IG6 IG5 IG4 IG3 IG2 IG1 IG0 AGC control A 1-bit value to enable the AGC input. The default setting is given in Table 5. Table 29 AGC control settings AG FUNCTION 0 disable AGC: manual gain setting through IG (7 bits) 1 enable AGC: gain control with manual MIC sensitivity setting 0 0 0 0 0 0 0 −3.0 0 0 0 0 0 0 1 −2.5 0 0 0 0 0 1 0 −2.0 0 0 0 0 0 1 1 −1.5 0 0 0 0 1 0 0 −1.0 0 0 0 0 1 0 1 −0.5 0 0 0 0 1 1 0 0.0 : : : : : : : : 1 1 1 1 1 0 1 59.5 1 1 1 1 1 1 0 60.0 1 1 1 1 1 1 1 60.5 7.21.3.7 7.21.3.5 AGC output level INPUT CHANNEL 2 AMPLIFIER GAIN (dB) AGC time constant A 2-bit value to program the AGC output level. The default setting is given in Table 5. A 3-bit value to program the attack and the decay parameters of the digital AGC. The default setting is given in Table 5. Table 30 AGC output level settings Table 32 AGC time constant settings AL1 AL0 OUTPUT LEVEL (dB FS) AT2 AT1 AT0 ATTACK TIME (ms) DECAY TIME (ns) 0 0 −9.0 0 0 0 11 100 0 1 −11.5 0 0 1 16 100 1 0 −15.0 0 1 0 11 200 1 1 −17.5 0 1 1 16 200 1 0 0 21 200 1 0 1 11 400 1 1 0 16 400 1 1 1 21 400 1998 Dec 18 19 Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications 7.21.4 UDA1341TS DATA1 CONTROL Table 33 Data transfer of type ‘DATA1’ BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 PL5 PL4 7.21.4.1 PL3 PL2 PL1 PL0 READ-OUT DATA peak level value (6 bits) Peak level value A 6-bit value to indicate the peak level value of the playback data. The largest value of the left and right channel data in the playback signal path is held since the last read-out of the microcontroller. Table 34 Peak level read-out data PEAK VALUE(1) (dB) PL5 PL4 PL3 PL2 PL1 PL0 0 0 0 0 0 0 −∞ 0 0 0 0 0 1 n.a. 0 0 0 0 1 0 n.a. 0 0 0 0 1 1 −90.31 0 0 0 1 0 0 n.a. 0 0 0 1 0 1 n.a. 0 0 0 1 1 0 n.a. 0 0 0 1 1 1 −84.29 : : : : : : : 0 1 0 0 1 1 note 2 0 1 0 1 0 0 note 3 : : : : : : : 1 1 1 1 0 1 −2.87 1 1 1 1 1 0 −1.48 1 1 1 1 1 1 0.00 Notes 1. Peak value (dB) = (Peak level − 63.5) × 5 × log 2. 2. For peak data >010011, the error in the peak value is 11 × log 2 < -------------------------4 3. For peak data <010100, the error is larger due to limited bit length. 1998 Dec 18 20 Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications UDA1341TS 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); VDDD = VDDA = 3 V; all voltages measured with respect to ground; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT − 5.0 V maximum crystal temperature − 150 °C Tstg storage temperature −65 +125 °C Tamb operating ambient temperature −20 +85 °C Ves electrostatic handling note 2 −2000 +2000 V note 3 −250 +250 V VDD supply voltage Txtal(max) note 1 Notes 1. All VDD and VSS connections must be made to the same power supply. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor. 3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor. 9 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS thermal resistance from junction to ambient VALUE UNIT 90 K/W in free air 10 DC CHARACTERISTICS VDDD = VDDA = 3 V; Tamb = 25 °C; RL = 5 kΩ; all voltages measured with respect to ground (pins 1, 11 and 27); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA(ADC) ADC analog supply voltage note 1 2.4 3.0 3.6 V VDDA(DAC) DAC analog supply voltage note 1 2.4 3.0 3.6 V VDDD digital supply voltage note 1 2.4 3.0 3.6 V IDDA(ADC) ADC analog supply current operation mode − 12.5 − mA ADC power-down − 6.0 − mA IDDA(DAC) IDDD DAC analog supply current digital supply current operation mode − 7.0 − mA DAC power-down − 50 − µA operation mode − 7.0 − mA DAC power-down − 4.0 − mA ADC power-down − 3.0 − mA Digital input pins VIH HIGH-level input voltage 0.8VDDD − VDDD + 0.5 V VIL LOW-level input voltage −0.5 − 0.2VDDD V |ILI| input leakage current − − 10 µA Ci input capacitance − − 10 pF 1998 Dec 18 21 Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications SYMBOL PARAMETER UDA1341TS CONDITIONS MIN. TYP. MAX. UNIT Digital output pins VOH HIGH-level output voltage IOH = −2 mA 0.85VDDD − − V VOL LOW-level output voltage IOL = 2 mA − − 0.4 V Analog-to-digital converter VADCP positive reference voltage − VDDA − V VADCN negative reference voltage 0.0 0.0 0.0 V Ro(ref) Vref reference output resistance pin 28 − 24 − kΩ Ri input resistance measured at 1 kHz stand-alone mode − 12.5 − kΩ double differential mode − 6.25 − kΩ − 20 − pF microphone mode − 12.5 − kΩ double differential mode − >1 − MΩ − 0.13 3.0 Ω (THD + N)/S < 0.1% − 0.22 − mA 3 − − kΩ note 2 − − 50 pF with respect to VSSA 0.45VDDA 0.5VDDA 0.55VDDA V Ci input capacitance Programmable gain amplifier (input channel 2) Ri input resistance Digital-to-analog converter Ro output resistance Io(max) maximum output current RL load resistance CL load capacitance Reference voltage Vref reference voltage Notes 1. All power supply pins (VDD and VSS) must be connected to the same external power supply unit. 2. When higher capacitive loads (above 50 pF) must be driven then a resistor of 100 Ω must be connected in series with the DAC output in order to prevent oscillations in the output operational amplifier. 1998 Dec 18 22 Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications UDA1341TS 11 AC CHARACTERISTICS (ANALOG) VDDD = VDDA = 3 V; fi = 1 kHz; fs = 44.1 kHz; Tamb = 25 °C; RL = 5 kΩ; all voltages measured with respect to ground (pins 1, 11 and 27); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Analog-to-digital converter Vi(rms) input voltage (RMS value) ∆Vi unbalance between channels (THD + N)/S total harmonic distortion-plus-noise to signal ratio − 1.0 − V − 0.1 − dB 0 dB − −85 −80 dB −60 dB; A-weighted − −37 −33 dB 0 dB − −90 −85 dB −60 dB; A-weighted − −40 −36 dB stand-alone mode − 97 − dB double differential mode − 100 − dB notes 1 and 2 stand-alone mode double differential mode S/N signal-to-noise ratio Vi = 0 V; A-weighted αcs channel separation − 100 − dB PSRR power supply rejection ratio fripple = 1 kHz; Vripple(p-p) = 30 mV − 30 − dB Manual gain mode (AGC disabled) Gmin minimum gain − −3 − dB Gmax maximum gain − 60.5 − dB Gstep digital gain step − 0.5 − dB −3 dB setting − 1414 − mV 0 dB setting − 1000 − mV 3 dB setting − 708 − mV 9 dB setting − 355 − mV 15 dB setting − 178 − mV 21 dB setting − 89 − mV 27 dB setting − 44 − mV −3 dB setting − −75 − dB 0 dB setting − −85 − dB 3 dB setting − −85 − dB 9 dB setting − −85 − dB 15 dB setting − −80 − dB 21 dB setting − −75 − dB 27 dB setting − −75 − dB Programmable gain amplifier Vi(rms) (THD + N)/S 1998 Dec 18 input voltage (RMS value) total harmonic distortion-plus-noise to signal ratio at full-scale at 0 dB 23 Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications SYMBOL (THD + N)/S PARAMETER total harmonic distortion-plus-noise to signal ratio UDA1341TS CONDITIONS MIN. TYP. MAX. UNIT at −60 dB; A-weighted −3 dB setting − tbf − dB 0 dB setting − −37 − dB 3 dB setting − tbf − dB 9 dB setting − tbf − dB 15 dB setting − tbf − dB 27 dB setting − tbf − dB Digital-to-analog converter Vo(rms) output voltage (RMS value) note 3 − 900 − mV ∆Vo unbalance between channels − 0.1 − dB (THD + N)/S total harmonic distortion-plus-noise to signal ratio 0 dB − −91 −86 dB −60 dB; A-weighted − −40 − dB S/N signal-to-noise ratio code = 0; A-weighted − 100 − dB αcs channel separation − 100 − dB PSRR power supply rejection ratio fripple = 1 kHz; Vripple(p-p) = 100 mV − 50 − dB Notes 1. The ADC inputs can be used in a 2 V (RMS value) input signal configuration when a resistor of 12 kΩ is used in series with the inputs and 1 or 2 V (RMS value) input signal operation can be selected via the Input Gain Switch (IGS). 2. The ADC input signal scales inversely proportional with the power supply voltage. 3. The DAC output voltage scales linear with the DAC analog supply voltage. 1998 Dec 18 24 Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications UDA1341TS 12 AC CHARACTERISTICS (DIGITAL) VDDD = VDDA = 2.7 to 3.6 V; Tamb = −20 to +85 °C; all voltages measured with respect to ground (pins 1, 11 and 27); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT System clock timing (see Fig.8) Tsys tCWL tCWH clock cycle time LOW-level pulse width HIGH-level pulse width fsys = 256fs 78 88 131 ns fsys = 384fs 52 59 87 ns fsys = 512fs 39 44 66 ns fsys < 19.2 MHz 0.30Tsys − 0.70Tsys ns fsys ≥ 19.2 MHz 0.40Tsys − 0.60Tsys ns fsys < 19.2 MHz 0.30Tsys − 0.70Tsys ns fsys ≥ 19.2 MHz 0.40Tsys − 0.60Tsys ns Serial input/output data timing (see Fig.9) Tcy bit clock cycle time 300 − − ns tBCK(H) bit clock HIGH time 100 − − ns tBCK(L) bit clock LOW time 100 − − ns tr rise time − − 20 ns tf fall time − − 20 ns ts;DATI data input set-up time 20 − − ns th;DATI data input hold time 0 − − ns td;DATO(BCK) data output delay time (from BCK falling edge) − − 80 ns td;DATO(WS) data output delay time (from WS edge) − − 80 ns th;DATO data output hold time 0 − − ns ts;WS word select set-up time 20 − − ns th;WS word select hold time 10 − − ns MSB-justified format Microcontroller L3-interface timing (see Figs 5 and 6) Tcy(CLK)(L3) L3CLOCK 500 − − ns tCLK(L3)H L3CLOCK HIGH time 250 − − ns tCLK(L3)L L3CLOCK LOW time 250 − − ns tsu(L3)A L3MODE set-up time addressing mode 190 − − ns th(L3)A L3MODE hold time addressing mode 190 − − ns tsu(L3)D L3MODE set-up time data transfer mode 190 − − ns th(L3)D L3MODE hold time data transfer mode 190 − − ns tsu(L3)DA L3DATA set-up time data transfer and addressing mode 190 − − ns th(L3)DA L3DATA hold time data transfer and addressing mode 30 − − ns tstp(L3) L3MODE halt time 190 − − ns 1998 Dec 18 25 Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications UDA1341TS tCWH handbook, full pagewidth tCWL MGL443 Tsys Fig.8 System clock timing. handbook, full pagewidth WS tr tBCK(H) th;WS tf td(DATO)(BCK) ts;WS BCK tBCK(L) td(DATO)(WS) th;DATO Tcy DATAO ts;DATI th;DATI DATAI MGG840 Fig.9 Serial interface timing. 1998 Dec 18 26 Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications UDA1341TS 13 APPLICATION INFORMATION handbook, full pagewidth L1 +3 V 8LM32A07 R21 1Ω L2 VDDD 8LM32A07 C12 100 µF (16 V) ground VDDD VDDA VDDA C2 C11 100 µF (16 V) 100 µF (16 V) 100 µF (16 V) C21 C25 C29 100 nF (63 V) 100 nF (63 V) 100 nF (63 V) VSSD VSSA(ADC) VDDA(ADC) R30 system clock SYSCLK 47 Ω DATAO BCK WS DATAI OVERFL overflow flag 1 R28 1Ω C9 3 VADCN VADCP 5 7 11 VDDD 10 12 18 28 16 C22 100 nF (63 V) 17 19 VINL1 left line input C4 C6 MIC input 2 24 VINL2 C7 47 µF (16 V) VOUTR C8 47 µF (16 V) 6 VINR2 8 23 L3MODE L3CLOCK L3DATA 22 13 14 21 15 20 25 27 VSSA(DAC) VDDA(DAC) C27 100 nF (63 V) C10 100 µF (16 V) R29 1Ω VDDA Fig.10 Application diagram. 1998 Dec 18 left output UDA1341TS 47 µF (16 V) right R23 100 Ω R22 10 kΩ VINR1 4 47 µF (16 V) left C5 VOUTL 47 µF (16 V) 47 µF (16 V) right C3 47 µF (16 V) 9 26 C1 Vref 27 MGR433 QMUTE AGCSTAT TEST2 TEST1 R26 100 Ω R27 10 kΩ right output Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications UDA1341TS 14 PACKAGE OUTLINE SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm D SOT341-1 E A X c HE y v M A Z 28 15 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 14 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.0 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.1 0.7 8 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT341-1 1998 Dec 18 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 93-09-08 95-02-04 MO-150AH 28 o Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications If wave soldering cannot be avoided, the following conditions must be observed: 15 SOLDERING 15.1 Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (order code 9398 652 90011). 15.2 During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all SSOP packages. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. 15.4 Wave soldering Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1998 Dec 18 Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. 15.3 UDA1341TS 29 Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications UDA1341TS 16 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1998 Dec 18 30 Philips Semiconductors Preliminary specification Economy audio CODEC for MiniDisc (MD) home stereo and portable applications NOTES 1998 Dec 18 31 UDA1341TS Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstraße 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1998 SCA60 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 655102/750/01/pp32 Date of release: 1998 Dec 18 Document order number: 9397 750 03982