INTEGRATED CIRCUITS DATA SHEET SAA2520 Stereo filter and codec for MPEG layer 1 audio applications Preliminary specification File under Integrated Circuits, IC01 August 1993 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 FEATURES GENERAL DESCRIPTION • Stereo filtering and codec functions in a single chip The SAA2520 performs the sub-band filtering and audio frame codec functions to provide efficient audio compression/decompression for MPEG (11172-3) Layer1 applications. It is capable of functioning as a stand-alone decoder but requires the addition of an adaptive masking threshold processor (SAA2521) in order to function as a highly efficient encoder. • MPEG coded interface • Filtered data interface • Baseband audio data interface • LT interface to microcontroller • Clock generator • Low operating voltage capability. ORDERING INFORMATION PACKAGE EXTENDED TYPE NUMBER SAA2520GP(1) PINS PIN POSITION MATERIAL CODE 44 QFP plastic SOT205AG Note 1. SOT205-1; 1996 August 26. CLK24 X22OUT X24OUT X22IN X24IN handbook, full pagewidth CLK22 38 39 40 41 42 43 V DD 28,44 8 FS256 SBDIR SBEF 1 CLOCK GENERATOR SAA2520 9 SUB-BAND SERIAL INTERFACE 7 10 12 11 2 STEREO SUB-BAND FILTER PROCESSOR CODEC 3 4 SWS SCL SDA SBCL SBWS SBMCLK MUTEDAC DEEMDAC ATTDAC 20 19 21 BASEBAND SERIAL INTERFACE 5,37 FILTERED DATA INTERFACE 18 17 FDAF V SS FDAC MICROPROCESSOR INTERFACE & CONTROL 16 15 14 FRESET FSYNC 13 SYNCDAI FDIR 36 35 LTCNT0 LTCNT1 Fig.1 Block diagram. August 1993 SBDA 2 34 33 LTCLK LTENA 32 22 PWRDWN LTDATA 29 6 URDA RESET MLB125 Philips Semiconductors Preliminary specification 34 LTENA 35 LTCNT0 36 LTCNT1 SAA2520 37 V SS 38 CLK22 39 CLK24 40 X22IN 41 X22OUT 42 X24IN handbook, full pagewidth 43 X24OUT 44 VDD Stereo filter and codec for MPEG layer 1 audio applications FS256 1 33 LTCLK MUTEDAC 2 32 LTDATA DEEMDAC 3 31 T0 ATTDAC 4 30 T1 V SS 5 URDA 6 SBDIR 7 27 DSC0 SBDA 8 26 DSC1 SBCL 9 25 DSC2 29 RESET SAA2520 28 VDD 20 21 SCL SWS SDA 22 19 FDAC MLB126 PWRDWN 18 17 FDAF 15 FSYNC 16 12 SBMCLK FRESET 23 DSC4 14 11 SBEF FDIR 24 DSC3 SYNCDAI 13 SBWS 10 Fig.2 Pin configuration. handbook, full pagewidth AUDIO AMPLIFIER digital audio interface DAC control SAA2520 MPEG interface MPEG source system micro interface MICROCONTROLLER power down reset MLB127 Fig.3 MPEG decoder system data flow diagram. August 1993 3 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 PINNING SYMBOL PIN DESCRIPTION TYPE FS256 1 (Filtered)-I2S clock; 256 × sample frequency. 12 mA 3-state output + CMOS input with pull-down I/O MUTEDAC 2 DAC control/output expander O DEEMDAC 3 DAC control/output expander O O ATTDAC 4 DAC control/output expander VSS 5 supply ground (0 V) URDA 6 unreliable drive processing data; CMOS level I2S I SBDIR 7 sub-band SBDA 8 sub-band I2S data; 4 mA, 3-state output + CMOS input with pull-down I/O SBCL 9 sub-band I2S bit clock; 4 mA, 3-state output + CMOS input with pull-down I/O SBWS 10 direction: (SWBS, SBCL, SBDA); CMOS level sub-band I2S word select; 4 mA, 3-state output + CMOS input with pull-down I2S byte error flag; CMOS level I I/O SBEF 11 sub-band SBMCLK 12 sub-band I2S clock, 6.144 MHz locked to FS256; 8 mA, 3-state output + CMOS input with pull-down O SYNCDAI 13 DAI synchronization pulse O I FDIR 14 (Filtered)-I2S FRESET 15 reset signal for SAA2521 O FSYNC 16 Filtered-I2S sync signal for SAA2521 O 17 Filtered-I2S I/O FDAF direction: (FDAC, FDAF, SDA); sub-band filter data; 4 mA, 3-state output + CMOS input with O pull-down FDAC 18 Filtered-I2S sub-band codec data; 4 mA, 3-state output + CMOS input with pull-down I/O SCL 19 I2S bit clock; 4 mA, 3-state output + CMOS input with pull-down I/O SWS 20 I2S-word select; 4 mA, 3-state output + CMOS input with pull-down I/O SDA 21 I2S baseband data filter; 4 mA, 3-state output + CMOS input with pull-down I/O PWRDWN 22 power-down mode; CMOS level DSC4 23 test pin DSC3 24 test pin DSC2 25 test pin DSC1 26 test pin DSC0 27 test pin VDD 28 positive supply voltage (+5 V) RESET 29 system reset; CMOS level with pull-down and hysteresis T1 30 test pin; do not connect T0 31 test pin; do not connect LTDATA 32 LT interface data; 4 mA, 3-state output + CMOS input with pull-down LTCLK 33 LT interface bit clock; CMOS level August 1993 4 I I I/O I Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SYMBOL PIN DESCRIPTION SAA2520 TYPE LTENA 34 LT interface enable; CMOS level I LTCNT0 35 LT interface control; CMOS level I LTCNT1 36 LT interface control; CMOS level I VSS 37 supply ground (0 V) CLK22 38 22.5792 MHz buffered output O CLK24 39 24.576 MHz buffered output O X22IN 40 22.5792 MHz crystal input I X22OUT 41 22.5792 MHz crystal output O X24IN 42 24.576 MHZ crystal input I X24OUT 43 24.576 MHz crystal output O VDD 44 positive supply voltage (+5 V) August 1993 5 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 handbook, full pagewidth from SAA2521 allocation information and scale factor indices ALLOCATION & SCALE FACTOR INFORMATION TABLE SYNC AND CODING INFORMATION base band samples SUB-BAND FILTER sub - band samples SCALING & QUANTIZATION FORMATTER MPEG OUTPUT DATA quantized samples MLB128 Fig.4 Encoding mode. handbook, full pagewidth sync/coding allocation scale factor MPEG input data DE– FORMATTER quantized samples CONTROL SCALE FACTOR ARRAY & ALLOCATION MULTIPLY DEQUANTIZATION OUTPUT CONTROL sub-band samples MLB129 Fig.5 Decoding mode. August 1993 6 SUB-BAND FILTER base band samples Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications After sync and coding information, allocation data and the scale factors are used to correctly fill the scale factor array. FUNCTIONAL DESCRIPTION Coding System This is followed by a process of multiplication to provide de-quantization and de-scaling of the samples. The decoded sub-band samples, which are represented in 24-bit two's complement notation, are processed by the sub-band filters and reconstituted into a single digital audio signal. MPEG coding achieves highly efficient digital encoding of audio signals by using an algorithm based on the characteristics of the human auditory system. The broad-band audio signal is split into 32 sub-band signals during encoding. For each of the sub-band signals the masking threshold is calculated. The samples of the sub-bands are incorporated in the signal with an accuracy that is determined by the signal to masking threshold ratio for that sub-band. RESET Reset must be active under the following conditions: 1. From system power-up until CLK24 has executed more than 24 clock cycles. During decoding, the sub-band signals are reconstructed and combined into a broadband audio signal. The integrated filter processor performs the splitting (encoding) and joining (decoding) including the corresponding formatting functions. 2. From the falling edge of PWRDWN for a period equivalent to 24 cycles of CLK24 + oscillator start-up time. This is typically >1 ms, however, this value is crystal dependent. For encoding, a SAA2521 is necessary to calculate the masking threshold and required accuracy of the sub-band samples. PWRDWN A HIGH input applied to this pin will halt all internally generated clock signals. As a result, chip activity will halt completely with outputs frozen in the state which was current at the time of PWRDWN activation. Encoding (See Fig.4) An encoding algorithm table is used during the coding process but, due to the Adaptive Allocation functions of the SAA2521, this may change with every frame. The table is therefore calculated for each frame by the SAA2521 and then transferred to the SAA2520. The bi-directional outputs: LTDATA, FDAC, FDAF, SDA, SBWS, SBCL and SBDA will be 3-stated. A frame contains 2 × 384 samples of Left and Right audio data. This results in 12 samples per sub-band (32 sub-bands). The samples of the greatest amplitude are used to determine the scale factor for a given sub-band. All samples are then scaled to represent a fraction of the greatest amplitude. Crystal Oscillators A 24.576 MHz crystal together with some external components form the 24.576 MHz oscillator (pins 42 and 43). Similarly a 22.5792 MHz oscillator (pins 40 and 41) is formed by similar peripheral components together with an appropriate crystal (see Fig.6). Once scaled, the samples are quantized to reduce the number of bits to correspond with the allocation table as calculated by the SAA2521. Synchronization and coding information data is then added to result in a fully encoded MPEG signal. The component values shown apply only to crystals from the Philips 4322 156 series which exhibit an equivalent series resistance of ≤ 40 Ω. Decoding (See Fig.5) All essential information (synchronization, system information, scale factors and encoded sub-band samples) are conveyed by incoming data. Decoding is repeated for every frame. August 1993 SAA2520 7 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 handbook, full pagewidth C2 33 pF X22IN 22.5792 MHz X1 C1 33 pF X22OUT R2 1 kΩ 24.576 MHz X2 C3 33 pF 40 R1 1 MΩ X24IN 41 42 SAA2520 R4 1 MΩ X24OUT 43 R3 1 kΩ C4 33 pF MLB130 Component values apply only to crystals from the Philips 4322 156 series. Fig.6 Crystal oscillator components. channel right left 32 bits SWS SCL 18 bits 1 13 bits SDA bit : 1 7 MSB 1 6 1 5 1 4 0 2 0 1 0 0 1 7 LSB 1 6 MSB Fig.7 Transfer of SDA data (Standard I2S default format). August 1993 8 1 5 1 4 MLA923 - 2 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications channel SAA2520 right left 32 bits SWS SCL 18 bits 14 bits SDA bit : 1 7 1 6 1 5 1 4 1 3 0 2 0 1 MSB 0 0 1 7 LSB 1 6 1 5 1 4 MLA924 - 2 MSB Fig.8 Transfer of SDA data (alternative format). channel right left 32 bits SWS SCL 1 7 bits FDAC/ FDAF bit : 2 3 MSB 2 2 2 1 2 0 0 2 0 1 2 3 0 0 LSB MSB Fig.9 Transfer of FDAF and FDAC (filtered) data. August 1993 9 2 2 2 1 2 0 MLA925 - 2 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications channel L R L R L R L SAA2520 R L R L R L R SWS FSYNC sub-band 31 0 1 31 0 1 MBC148 - 1 Fig.10 SWS related to phase of FSYNC. Baseband Interface Signals The interface between the SAA2520 and the baseband input/output circuitry consists of the following signals: SWS bi-directional word (channel) select FS SCL bi-directional bit clock 64FS SDA bi-directional baseband data FDIR output decoding mode (direction control) The SWS signal indicates the channel of the sample signal (either LEFT or RIGHT) and is equal to the sampling frequency FS. Operating at a frequency of 64 times that is used for sampling, the bit clock dictates that each SWS period contains 64 SDA data bits. Of these, a maximum of 36 are used to transfer data (samples may have a length up to 18-bits). Samples are transferred most significant bit first. Both SWS and SDA change state at the negative edge of SCL. This baseband data is transferred between the SAA2520 and the input/output using either Standard I2S (default) or the alternative format shown in Fig.8. August 1993 10 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 Interface between SAA2520 and SAA2521 consists of the following signals: FILTERED-I2S INTERFACE SWS bi-directional word select (common to I2S) SCL bi-directional bit clock (common to FDAC bi-directional codec data FDAF bi-directional filter data FSYNC output synchronization MPEG CODED INTERFACE The interface that carries the MPEG coded signal uses the following signals: The MPEG I2S interface The frequency of the SWS signal is equal to the sample frequency FS and the bit clock SCL is 64 times the sample frequency. Each period of SWS contains 64 data-bits, 48 of which are used to transfer data. The half period in which SWS is LOW is used to transfer the information of the LEFT channel while the following half period during which SWS is HIGH carries the data of the RIGHT channel. The 24-bit samples are transferred most significant bit first. This bit is transferred in the bit clock period with a 1-bit delay following the change in SWS. Both SWS and FDAF/FDAC change state at the negative edge of SCL. The operation of SAA2521 and the input/output circuitry is controlled by three signals shown in Table 1. FRESET and SYNCDAI are given whenever: FS256 frequency is changed (12.288/11.2896/8.192 MHz) − FDIR is switching − bit rate is changing − system reset is active August 1993 bi-directional word selection SBCL bi-directional bit clock SBDA bi-directional sub-band coded data SBEF input error signal SBDIR input direction of data flow URDA input unreliable encoded data signal The SBMCLK signal is the main frequency from which other clock signals are derived. In encode mode this division is performed internally. In decode mode the external source should provide SBWS and SBCL. The frequency of the signal is equal to 1/32nd of the bit rate. The frequency of the bit clock SBCL is twice that of the bit rate. Some examples of the frequencies are given in Table 2. SAA2521 AND INPUT/OUTPUT MODE CONTROL − SBWS Operation is further controlled by: The SAA2521 may be synchronized to the sub-band codec using the FSYNC signal, which defines the SWS period in which the samples of sub-band 0 (containing the lowest frequency components) are transferred (see Fig.10). FS256, SCL and SWS outputs switch between high and low impedance 64FS FS/32 Filtered data is transferred between SAA2520 filter/codec functions and the SAA2521 using the format shown in Fig.9. − FS I2S) 11 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications Table 1 SAA2520 SAA2521 input/output control. FRESET output request a general reset of SAA2521 FDIR output '1' for decoding and '0' for encoding mode (common to I2S) SYNCDAI output pulse for synchronization of digital input/output (TDA1315) Table 2 Frequency examples. BIT RATE (k BITS/s) SBWS FREQUENCY (kHz) SBCL FREQUENCY (kHz) 384 12 768 256 8 512 192 6 384 128 4 256 ENCODE MODE The following modes are supported: Stereo or 2-channel mono with allowable bit rates of 384, 256, 192 and 128 kbits/s; audio sampling frequencies of 48, 44.1 and 32 kHz. DECODE MODE The following modes are supported: Stereo and joint stereo, 2-channel mono and 1-channel mono with allowable bit rates in the range 448 to 32 k bits/s; audio sampling frequencies of 48, 44.1 and 32 kHz. August 1993 12 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 T t fH t fL FS256 t d1 t d1 SCL t sL t sH Tc t h2 SWS, SDA, FDAF, FDAC, FSYNC output t d2 t su t h1 SDA, FDAF, FDAC input MEA642 - 3 Fig.11 Filtered I2S interface timing (master mode - FS256, SCL and SWS are input). Notes to Fig.11 T FS256 cycle time (fs = 48 kHz) FS256 cycle time (fs = 44.1 kHz) FS256 cycle time (fs = 32 kHz) 81.4 ns nominal 88.6 ns nominal 122.1 ns nominal Tc SCL cycle time 4T ns nominal tfH FS256 HIGH time (fs = 48 kHz) FS256 HIGH time (fs = 44.1 kHz) FS256 HIGH time (fs = 32 kHz) ≥ 35 ns ≥ 38 ns ≥ 35 ns tfL FS256 LOW time (fs = 48 kHz) FS256 LOW time (fs = 44.1 kHz) FS256 LOW time (fs = 32 kHz) ≥ 35 ns ≥ 38 ns ≥ 75 ns tSH SCL HIGH time ≥ 2T - 20 ns tSL SCL LOW time ≥ 2T - 20 ns tS SDA, FDAF, FDAC input set-up before FS256 HIGH ≥ 20 ns tH1 SDA, FDAF, FDAC input hold after FS256 HIGH ≥ 30 ns tH2 SDA, FDAF, FDAC output hold after FS256 HIGH ≤ 0 ns tD1, 2 FS256 HIGH to SCL, SWS, SDA, FDAF, FDAC output valid ≤ 50 ns August 1993 13 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications t fL T SAA2520 t fH FS256 t sH Tc t sL SCL t h1 td SDA, FDAF, FDAC, FSYNC output t su t h2 SWS, SDA, FDAF, FDAC input MEA644 - 3 Fig.12 Filtered I2S interface timing (slave mode - FS256, SCL and SWS are input). Notes to Fig.12 tfH FS256 HIGH time ≥ 35 ns tfL FS256 LOW time ≥ 35 ns tsH SCL HIGH time ≥ T + 35 ns tsL SCL LOW time ≥ T + 35 ns tH1 SDA, FDAF, FDAC output hold after SCL HIGH ≥ 2T - 15 ns tD SCL HIGH to SDA, FDAF FDAC output valid ≤ 3T + 60 ns ts SDA, FDAF, FDAC input valid after SCL HIGH ≥ 20 ns tH2 SDA, FDAF, FDAC input hold after SCL HIGH ≥ T + 20 ns August 1993 14 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications , SAA2520 FRESET t d0 t sH t d1 SYNCDAI t d2 t d3 FDIR t d4 t d5 HIGH Z SDA HIGH Z SDA t d6 HIGH Z SWS FS256 SCL FDAF FDAC HIGH Z t d8 t d7 HIGH Z FDAF FDAC t d9 HIGH Z Fig.13 Mode switch timing. Notes to Fig.13 tDO FRESET HIGH to SYNCDAI HIGH ≥ 300 ns tSH SYNCDAI HIGH time ≥ 1280 ns tD1 SYNCDAI LOW to FRESET LOW ≥ 790 ns tD2 FDIR hold to FRESET HIGH ≤ 20 ns tD3 FRESET HIGH to FDIR valid ≤ 20 ns tD4 SDA change to high impedance after FRESET HIGH tD5 SDA remains high impedance after FRESET LOW tD6 FDAF, FDAC change to high impedance after FRESET HIGH tD7 FDAF, FDAC remain high impedance August 1993 ≥ 0 ns ≤ 170 ns ≥ 0 ns ≤ 170 ns ≤ 20 ns 15 SWS FS256 SCL MEA646 - 1 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 Notes to Fig.13 after FRESET HIGH ≥ 460 ns tD8 FS256, SWS, SCL change to high impedance before SYNCDAI HIGH ≥ 140 ns tD9 FS256, SWS, SCL remain HIGH impedance after SYNCDAI HIGH ≥ 140 ns 32 bits SBWS SBCL 1 15 bits 1 SBDA bit : 0 0 0 1 MSB 0 2 0 3 1 0 1 1 1 2 1 3 1 4 1 5 LSB 1 1 6 7 MSB 1 8 1 9 2 0 2 1 2 2 SBEF byte 0 byte 1 byte 2 MEA649 - 2 Fig.14 Transferring MPEG data to and from the SAA2520. August 1993 16 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 MPEG Coded Interface (Sub-band I2S) Encoding mode The MPEG coded data is transferred to and from the SAA2520 using the format shown in Fig.14. SBCL, SBWS and SBDA are generated by the SAA2520. However, if the SBDIR signal is logic 1, the output buffers are not enabled and these signals do not appear on the pins. This mode is available to permit a change of operating mode whilst the bus signals are driven from an external source. Each period of SBWS contains 64 data bits, 32 of which are used to convey data. The half-period during which SBWS is logic 0 is used to transfer the first 16-bits (0 to 15) of a sub-band slot. The remaining half-period during which SBWS is logic 1 carries the remaining 16-bits (16 to 31). Thus one period of SBWS corresponds with one slot of the sub-band signal. Decoding mode SBCL, SBWS and SBDA are generated by an external source. Bits 0 and 16 are transferred in the bit clock period, one bit-time after the change in SBWS. Both SBWS and SBDA change state during the negative edge of SBCL. Table 3 contains a summary of the source signals in the various modes. In decode mode a byte error flag SBEF is also transferred. This occurs approximately in the middle of the corresponding byte (byte 0 = bits 0 to 7, byte 1 = bits 8 to 15 etc). Table 3 Modes and source signals. source of: Mode FDIR SBDIR SBWS SBCL SBDA SBEF SBMCLK Encode 0 0 INT INT INT ---- INT note 1 Encode 0 1 EXT EXT EXT ---- INT note 2 Decode 1 0 INT INT INT EXT INT note 3 Decode 1 1 EXT EXT EXT EXT INT Notes 1. During encoding the SBEF signal is ‘don’t care’. 2. Incoming data is not decoded. The SAA2520 operates in the encoding mode and the data does not enter the interface. 3. Operation is undefined. The SAA2520 is in decoding mode whilst the SBWS, SBCL and SBDA output drivers are enabled. August 1993 17 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications t mL Ts SAA2520 t mH SBMCLK Tsc t cL t cH SBCL t d1 t d2 SBWS SBDA MEA645 - 2 Fig.15 Sub-band I2S interface timing (master mode - SBCL, SBWS and SBDA are output). Notes to Fig.15 T SBMCLK cycle time 120 to 205 ns (163 ns nominal) tmH SBMCLK HIGH time ≥ 35 ns tmL SBMCLK LOW time ≥ 75 ns Tc SBCL cycle time (384 kB/s) SBCL cycle time (256 kB/s) SBCL cycle time (192 kB/s) SBCL cycle time (128 kB/s) 8T ns nominal 12T ns nominal 16T ns nominal 24T ns nominal tCH SBCL HIGH time (384 kB/s) SBCL HIGH time (256 kB/s) SBCL HIGH time (192 kB/s) SBCL HIGH time (128 kB/s) ≥ 4T - 20 ns ≥ 6T - 20 ns ≥ 8T - 20 ns ≥ 12T - 20 ns tCL SBCL LOW time (384 kB/s) SBCL LOW time (256 k/Bs) SBCL LOW time (192 kB/s) SBCL LOW time (128 kB/s) ≥ 4T - 20 ns ≥ 6T - 20 ns ≥ 8T - 20 ns ≥ 12T - 20 ns tD1 SBWS, SBDA hold to SBCL LOW ≤ 20 ns tD2 SBCL LOW to SBWS, SBDA valid ≤ 20 ns August 1993 18 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 ,, ,,, , , SBWS SBCL SBDA 0 1 2 3 4 5 6 7 8 9 10 11 12 SBEF t cL Tsc t cH SBCL t su1 t h1 SBWS SBDA t h2 SBEF MEA648 - 2 t su2 Fig.16 Sub-band I2S interface timing (slave mode - SBCL, SBWS and SBDA are input). Notes to Fig.16 TC SBCL cycle time (see note 1) 6.86T to 96T ns (8T ns nominal) tCH SBCL HIGH time ≥ T + 30 ns tCL SBCL LOW time ≥ T + 30 ns tS1 SBWS, SBDA input set-up before SBCL HIGH ≥ T + 30 ns tH1 SBWS, SBDA input hold after SBCL HIGH ≥ 30 ns tS2 SBCL HIGH to SBEF valid ≤ T - 30 ns tH2 SBEF hold after SBCL HIGH Note 1: Minimum at bit rate = 448 kB/s Nominal at bit rate = 384 kB/s Maximum at bit rate = 32 kB/s ≥ 2T- 30 ns August 1993 19 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 SBDIR t d1 t d2 HIGH Z SBCL SBWS SBDA HIGH Z MEA647 - 1 Fig.17 Sub-band I2S mode switch timing. Notes to Fig.17 tD1 SBDIR HIGH to SBCL, SBWS, SBDA high impedance ≤ 50 ns tD2 SBCL, SBWS, SBDA after SBDIR LOW high impedance ≥ 240 ns August 1993 20 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 Microcontroller interface The SAA2520 has an interface connection to the serial interface of a microcontroller. The following signals are used: LTCLK input bit clock LTDATA bi-directional serial data LTCNT0 input control line 0 LTCNT1 input control line 1 LTENA input enable The SAA2520 microcontroller interface is enabled only if LTENA (pin 34) is logic 1. Information to or from the SAA2520 is conveyed in serial 8 or 16-bit units, whilst the type of information is controlled by LTCNT0 (pin 35) and LTCNT1 (pin 36). During the transfer of 8-bit units, the least significant bit is first to be transferred. When 16-bit units are transferred the most significant byte is sent first. A transfer commences when the microcontroller sets the control lines to the correct combination for the required action. LTENA is set to logic 1. The SAA2520 determines its required action and prepares to transfer data. When the microcontroller supplies the LTCLK, data is transferred to or from the SAA2520 in units of 8-bits. 16-bit transfers are conveyed as two 8-bit units during which LTENA remains high. Four information bits together with four address bits are transferred in this mode. The order in which the bits appear on the interface is: Table 4 EXTENDED SETTINGS (LTCNT1 = 0, LTCNT0 = 0) D0..D1..D2..D3..A0..A1..A2..A3 Extended Settings. BIT A3 BIT A2 BIT A1 BIT A0 0 0 0 0 CODEC external settings (see Table 5) 0 0 0 1 FILTER settings (see note 1) 0 0 1 0 not used .. .. .. .. .. 1 1 1 1 not used Table 5 DESCRIPTION Extended Settings. BIT DESIGNATION DEFAULT FUNCTION D0 MUTEDAC 1 connected to DAC mute input D1 ATTDAC 0 connected to DAC attenuation input D2 DEEMDAC 0 emphasis control for DAC circuit D3 HOLDCLKOK 0 selects CLKOK hold mode Note If not used for DAC control, the MUTEDAC, ATTDAC and DEEMDAC can be used as general purpose output expanders. August 1993 21 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications Bits D0 to D3 are copied directly to the corresponding output pins/mode flip-flop. SAA2520 This is then followed by the scale factor information. In the event that only internal settings information is sent, then a default allocation of logic 0 will be assigned to all sub-bands. If in addition no internal settings are sent then the previous settings remain valid. For HOLDCLKOK = logic 1. When CLKOK drops it will remain LOW until set by an encode/decode mode, sample frequency, external 256FS or bit rate index change. The allocation information is transferred in 4-bit units. Each of these units contains the number of bits allocated to the sub-band, MINUS 1, except in the case of a logic 0 value, which indicates that no bits are allocated to that sub-band. Note 1. When D0 = logic 1 (default) I2S mode is selected. For D0 = logic 0 the alternative mode is selected. The setting of D0 remains dormant until activated by the occurrence of FRESET. Scale factor information is transferred in units of 8-bits, containing the 6-bit scale factor which is extended to 8-bits by adding two logic 0’s at the most significant end. ALLOCATION/SCALE FACTOR INFORMATION (LTCNT1 = 0, LTCNT0 = LOGIC 1) LOGIC In the case of stereo encoding the channels are indicated by L (left) and R (right). This changes to I and II in the case of 2 channel mono encoding. For encoding, the allocation and scale factor arrays can be filled using this mode. To completely fill the allocation array 16 complete transfers of 16-bits are required. After the first transfer of allocation information a check must be made to determine when the SAA2520 is ready to receive the remaining information. This will ensure synchronization with the internal program of the SAA2520. Transfer of the allocation information is completed by sending the internal settings. Table 6 Allocation information format. msb bits B13 - channel sub-band B12 L or I 0 .. 30 (even) B15 - B14 B11 - B10 - B9 - B8 R or II 0 .. 30 (even) B7 - B6 - B5 - B4 L or I 1 .. 31 (odd) B3 - B2 - B1 - B0 R or II 1 .. 31 (odd) Table 7 - lsb Scalefactor information format. msb bits lsb channel B15 ................ B8 L or I 0 .. 31 B7 ................ B0 R or II 0 .. 31 August 1993 22 sub-band Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 INTERNAL SETTINGS (LTCNT1 = LOGIC 1, LTNCT 0 = LOGIC 0) The operation of the codec is controlled by the bits transferred in this mode. Table 8 Internal Settings (LTCNT1 = logic 1, LTNCT 0 = logic 0). msb lsb name function valid in S15 ... S12 bit rate index bit rate indication encode S11 ... S10 sample frequency 44.1, 48 or 32 kHz indication encode S9 decode 1 = decode; 0 = encode encode/decode S8 EXT 256FS 1 = external; 0 = internal 256FS encode/decode S7 2-channel mono 1 = 2-CH mono; 0 = stereo encode S6 MUTE 1 = mute; 0 = no mute encode/decode S5 not used S4 CH1 1 = CH1; 0 = CH2 decode S3 ... S2 Tr0 to Tr1 transparent bits encode S1 ... S0 EMPHASIS emphasis indication encode Table 9 Internal Settings (LTCNT1 = logic 1, LTCNT0 = logic 0). msb lsb bit rate 1 1 0 0 384 kbits/s 1 0 0 0 256 kbits/s 0 1 1 0 192 kbits/s 0 1 0 0 128 kbits/s CH1 is utilized in the decoding mode to select one of the 2-channel mono signals to be decoded (default is I - channel 1). A value of 0 results in channel 2 being decoded). The bit rate index indicates the bit rate of the encoded signal and is only effective in the encode mode. The decode bit determines the operation mode of the SAA2520. The default value is logic 1 (decoding mode). The transparent bits are copied in the sub-band signal, default is 00. EXT 256FS in the encoding mode determines whether or not the SAA2520 is master or slave of the Filtered-I2S interface (default is logic 0, master mode). The information from S15 to S10, S7 and S3 to S0 will be copied into the sub-band signal. 2CH MONO is used in the encoding mode to determine whether the sub-band signal is generated as a stereo or 2-channel mono signal. Default value is logic 0. MUTE is used in both the encoding and decoding modes to mute the information to or from the Filtered-I2S interface (the default value is logic 0). August 1993 default value 23 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 Table 10 Sample frequency indication. msb lsb sample frequency 0 0 44.1 kHz 0 1 48 kHz 1 0 32 kHz 1 1 not used default value Table 11 EMPHASIS indication. msb lsb emphasis 0 0 no emphasis 0 1 50/15 µs 1 0 reserved 1 1 CCITT J.17 default value Before sending internal settings the microcontroller should check whether or not the SAA2520 is ready-to-receive. However, this does not apply for the transfer of internal settings to end a transfer of allocation information. STATUS (LTCNT = LOGIC 1, LTNCT0 = LOGIC 1) Table 12 Status information 16-bit units. msb lsb name function valid in T15 ... T12 bit rate index bit rate indication encode/decode T11 ... T10 sample frequency 44.1, 48 or 32 kHz indication encode/decode ready-to-receive 1 = ready; 0 = not ready encode/decode MODE sub-band signal mode indication encode/decode SYNC synchronization indication decode T9 T8 not used T7 T6 T5 T4 T3 T1 ... CLKOK 1 = o.k.; 0 = not o.k. encode/decode T2 Tr0 to Tr1 transparent bits encode/decode T0 EMPHASIS emphasis indication encode/decode The bit rate index indicates the bit rate of the sub-band signal in units of 32 kbits/s. bit rate index 0000 indicates the ‘free format’ condition. bit rate 1111 is illegal and should not be found. The coding of the sample frequency indication is equal to the one in the internal settings. August 1993 24 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 Table 13 MODE identification. msb lsb mode 0 0 stereo L and R 0 1 joint stereo L and R 1 0 2 channel mono I or II as selected 1 1 1 channel mono mono; no selection Ready-to-receive indicates whether the SAA2520 is ready to receive allocation, scale factor or internal setting transfers. This should be checked in order to synchronize the transfer of such information. In 2 channel mono decode mode the selected samples are transferred to both output channels. The same occurs with all samples in 1-channel mono decode mode. In both of these instances the L and R filter output channels are identical. In decode mode the SYNC bit is logic 0 when the SAA2520 is unable to decode the sub-band frames. This will occur in the following situations: • with the loss of synchronisation • when in correct allocation information is received for two or more subsequent frames (SBEF was HIGH). • when the URDA input pin is HIGH In these situations the SAA2520 data output will be muted. The SYNC bit will return to logic 1 as soon as the decoder is resynchronized to the incoming sub-band data. CLKOK indicates whether the 256FS clock corresponds to specified sample frequency. The CLKOK bit is set to logic 1 after a change in sample frequency, operation mode or EXT256FS setting. It drops to logic 0 as soon as the 256FS clock deviates from the nominal frequency by more than approximately 0.2%. Return to logic 1 will only occur automatically when the extended setting CLKOK-hold-mode is logic 0. The transparent bits are copied from the MPEG coded signal. The EMPHASIS indication is as defined in the internal settings. It can be used to apply the correct de-emphasis. Note: the two bytes of the status are 'sampled' at different moments so the information may not result from the same sub-band frame. August 1993 25 output Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 handbook, full pagewidth LTENA LTCNT0/1 LTCLK LTDATA 0 lsb 1 2 3 4 5 6 7 msb MLB131 Fig.18 Transfer of data on SAA2520 microcontroller interface. handbook, full pagewidth LTENA 16 bits allocation / scale factor information 16 bits allocation / scale factor information LTCLKC MLB132 Fig.19 The LTENA line must return to logic 0 between information transfers. August 1993 26 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 handbook, full pagewidth LTENA LTCNT0/1 LTCLK LTDATA 8 bit : 10 9 12 11 14 13 0 2 15 4 1 6 3 MLB133 5 7 Fig.20 Order of settings and status bits on the SAA2520 microcontroller interface. handbook, full LTENA pagewidth LTENA must remain HIGH LTCNT0/1 LTCLK t D6 LTDATA OUTPUT 8 9 10 11 12 13 14 15 0 tD6 delay LTCLK HIGH to LTDATA valid output for bit 0 in 16-bit transfers Fig.21 16-bit transfers. August 1993 27 1 2 3 4 5 6 7 MLB134 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 t el handbook, full pagewidth LTENA t S1 t D1 t H1 LTCNT0 LTCNT1 t D5 t CL t CH t H4 LTCLK t S2 t H2 t D4 LTCDATA input t D2 LTCDATA output t D3 t H3 t D6 hiZ hiZ MLB135 Fig.22 Microcontroller interface timing. Notes to Fig.22 teL LTENA LOW time ≥ 190 ns tCH LTCLK HIGH time ≥ 190 ns tCL LTCLK LOW time ≥ 190 ns tD1 LTENA HIGH to LTCLK HIGH ≥ 190 ns tD2 LTENA HIGH to LTDATA output low impedance ≥ 0 ns tD3 LTENA HIGH to LTDATA output valid ≤ 380 ns tD4 LTENA LOW to LTDATA high impedance ≤ 50 ns tH4 LTENA hold after LTCLK HIGH ≥ 355 ns tD5 LTCLK HIGH to LTENA HIGH ≥ 190 ns tD6 LTCLK HIGH to LTDATA output valid for bit 0 (see Fig.21) for first bit in the second 8-bit unit ≤ 355 ns ≤ 520 ns tS1 LTCNT0/1 set-up before LTENA HIGH ≥ 190 ns tH1 LTCNT0/1 hold after LTENA HIGH ≥ 190 ns tS2 LTDATA set-up before LTCLK HIGH ≥ 190 ns tH2 LTDATA input hold after LTCLK HIGH ≥ 30 ns tH3 LTDATA output hold after LTCLK HIGH ≥ 145 ns tH4 LTENA hold after LTCLK HIGH ≥ 355 ns August 1993 28 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT −0.5 6.5 V −0.5 VDD + 0.5 V supply current from VSS − 160 mA IDD supply current in VDD − 160 mA II input current −10 10 mA IO output current −20 20 mA Ptot total power dissipation − 880 mW Tstg storage temperature range −55 150 °C Tamb operating ambient temperature range - 40 85 °C Ves1 electrostatic handling note 2 −1500 1500 V Ves2 electrostatic handling note 3 −70 70 V VDD supply voltage VI input voltage ISS note 1 Notes 1. Input voltage should not exceed 6.5 V unless otherwise specified 2. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor 3. Equivalent to discharging a 200 pF capacitor through a 0 Ω series resistor. DC CHARACTERISTICS Tamb = −40 to 85 °C; VDD = 3.8 to 5.5 V unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDD supply voltage range IDD operating current IDD operating current 3.8 5.0 5.5 V VDD = 5 V (note 1) − 82 110 mA VDD = 3.8 V (note 1) − 58 80 mA Inputs URDA, SBDIR, SBEF, LTCLK, LTCNT0, LTNCT1, X22IN, X24IN VIH HIGH level input voltage 0.7VDD − − V VIL LOW level input voltage − − 0.3VDD V −II input current Vi = 0 V; Tamb = 25 °C − − 10 µA +II input current Vi = 5.5 V; Tamb = 25 °C − − 10 µA Inputs PWRDWN, LTENA VIH HIGH level input voltage 0.7VDD − − V VIL LOW level input voltage − − 0.3VDD V +II input current 40 − 250 µA August 1993 Vi = VDD; Tamb = 25 °C 29 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SYMBOL PARAMETER SAA2520 CONDITIONS MIN. TYP. MAX. UNIT Input RESET Vtlh positive-going threshold − − 0.8VDD V Vthl negative-going threshold 0.2VDD − − V Vhys hystersis (Vtlh - Vthl) − 1.5 − V +II input current Vi = VDD; Tamb = 25 °C 40 − 250 µA Outputs MUTEDAC, DEEMDAC, ATTDAC, SYNCDAI, FDIR, FRESET, FSYNC, CLK22 VOH HIGH level output voltage +Io = 2 mA VDD−0.5 − − V VOL LOW level output voltage −Io = 2 mA − − 0.4 V Outputs CLK24 VOH HIGH level output voltage +Io = 8 mA VDD−0.5 − − V VOL LOW level output voltage −Io = 8 mA − − 0.4 V Inputs/outputs SBDA, SBCL, SBWS, FDAF, FDAC, SCL, SWS, SDA, LTDATA VOH HIGH level output voltage +Io = 2 mA VDD−0.5 − − V VOL LOW level output voltage −Io = 2 mA − − 0.4 V − V Outputs SBDA, SBCL, SBWS, FDAF, FDAC, SCL, SWS, SDA, LTDATA in 3-state VIH HIGH level input voltage VIL LOW level input voltage II input current 0.7VDD Vi = VDD; Tamb = 25 °C − − − 0.3VDD V 40 − 250 µA Input/output SBMCLK VOH HIGH level output voltage +Io = 8 mA VDD−0.5 − − V VOL LOW level output voltage −Io = 8 mA − − 0.4 V Output SBMCLK in 3-state VIH HIGH level input voltage 0.7VDD − − V VIL LOW level input voltage − − 0.3VDD V II input current Vi = VDD; Tamb = 25 °C 40 − 250 µA Input/output FS256 VOH HIGH level output voltage +Io = 12 mA VDD−0.5 − − V VOL LOW level output voltage −Io = 12 mA − − 0.4 V Output FS256 in 3-state VIH HIGH level input voltage 0.7VDD − − V VIL LOW level input voltage − − 0.3VDD V II input current 40 − 250 µA Vi = VDD; Tamb = 25 °C Note 1. For load impedances representative of the application. August 1993 30 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 AC CHARACTERISTICS Tamb = −40 to 85 °C; VDD = 3.8 to 5.5 V unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Inputs CI input capacitance − − 10 pF X24IN and X22IN f crystal frequency at X22OUT, CLK22 note 1 21 22.5792 24 MHz f crystal frequency at X24OUT, CLK24 note 1 23 24.576 26 MHz gm mutual conductance 100 kHz 1.5 − − mA/V Av small signal gain Av = gm.Ro 3.5 − − V/V Cfb feedback capacitance − − 5 pF CO output capacitance − − 10 pF output capacitance − − 10 pF Outputs CO Inputs URDA, RESET, LTDATA, LTCLK, LTENA, LTCNT0, LTCNT1 tSU setup time to X24IN 15 − − ns tHD hold time to X24IN 60 − − ns Outputs LTDATA, MUTEDAC, DEEMDAC, ATTDAC, SYNCDAI, FDIR, FRESET td propagation delay from X24IN − − 80 ns Inputs FDAF, FDAC, SDA, SCL, SWS tSU setup time to FS256 15 − − ns tHD hold time to FS256 25 − − ns − − 50 ns Outputs FDAF, FDAC, SDA, SCL, SWS, FSYNC td propagation delay from FS256 Inputs SBDA, SBCL, SBWS, URDA, SBDIR, SBEF tSU setup time to SBMCLK 15 − − ns tHD hold time to SBMCLK 25 − − ns − − 50 ns Outputs SBDA, SBCL, SBWS td propagation delay from SBMCLK FS256 T FS256 cycle time fs = 48 kHz − 81.4 − ns T FS256 cycle time fs = 44.1 kHz − 88.6 − ns T FS256 cycle time fs = 32 kHz − 122.1 − ns TC SCL cycle time − 4T − ns August 1993 31 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SYMBOL PARAMETER SAA2520 CONDITIONS MIN. TYP. MAX. UNIT FS256 master mode (FS256,SCL and SWS are output) tfH FS256 HIGH time fs = 48 kHz 35 − − ns tfH FS256 HIGH time fs = 44.1 kHz 38 − − ns tfH FS256 HIGH time fs = 32 kHz 75 − − ns tfL FS256 LOW time fs = 48 kHz 35 − − ns tfL FS256 LOW time fs = 44.1 kHz 38 − − ns tfL FS256 LOW time fs = 32 kHz 75 − − ns tsH SCL HIGH time 2T-20 − − ns tsL SCL LOW time 2T-20 − − ns ts SDA, FDAF, FDAC input setup time before FS256 HIGH 20 − − ns tH1 SDA, FDAF, FDAC input hold time after FS256 HIGH 30 − − ns tH2 SDA, FDAF, FDAC output hold time after FS256 HIGH 0 − − ns tD1,2 FS256 HIGH-to SCL, SWS, SDA, FDAF, FDAC output valid − − 50 ns FS256 slave mode (FS256, SCL and SWS are input) tfH FS256 HIGH time 35 − − ns tfL FS256 LOW time 35 − − ns tsH SCL HIGH time T+35 − − ns tsL SCL LOW time T+35 − − ns tH1 SDA, FDAF, FDAC output hold time after SCL HIGH 2T-15 − − ns tD SCL HIGH-to SDA, FDAF, FDAC output valid − − 3T+60 ns tS SDA, FDAF, FDAC input valid after SCL HIGH 20 − − ns tH2 SDA, FDAF, FDAC input hold time after SCL HIGH T+20 − − ns T SBMCLK cycle time 120 163 205 ns tmH SBMCLK HIGH time 35 − − ns tmL SBMCLK LOW time 75 − − ns SBMCLK August 1993 32 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SYMBOL PARAMETER SAA2520 CONDITIONS MIN. TYP. MAX. UNIT SBMCLK master mode (SBCL, SBWS and SBDA are output) TC SBCL cycle time 384 kB/s − 8T − ns TC SBCL cycle time 256 kB/s − 12T − ns TC SBCL cycle time 192 kB/s − 16T − ns TC SBCL cycle time 128 kB/s − 24T − ns tcH SBCL HIGH time 384 kB/s 4T − 20 − − ns tcH SBCL HIGH time 256 kB/s 6T − 20 − − ns tcH SBCL HIGH time 192 kB/s 8T − 20 − − ns tcH SBCL HIGH time 128 kB/s 12T − 20 − − ns tcL SBCL LOW time 384 kB/s 4T − 20 − − ns tcL SBCL LOW time 256 kB/s 6T − 20 − − ns tcL SBCL LOW time 192 kB/s 8T − 20 − − ns tcL SBCL LOW time 128 kB/s 12T − 20 − − ns tD1 SBWS, SBDA hold to SBCL LOW 20 − − ns tD2 SBWS, SBDA valid after SBCL 0 − − 20 ns 6.86T 8T 96T ns SBMCLK slave mode (SBCL, SBWS and SBDA are input) TC SBCL cycle time note 2 tcH SBCL HIGH time T + 30 − − ns tcL SBCL LOW time T + 30 − − ns tS1 SBWS, SBDA setup time before SBCL HIGH T + 30 − − ns tH1 SBWS, SBDA hold time after SBCL HIGH 30 − − ns tS2 delay before SBEF valid after SBCL HIGH − − T − 30 ns tH2 SBEF hold time after SBCL HIGH 2T − 30 − − ns Notes 1. % deviation from nominal frequency must be the same for X24, X22, and FS256 inputs to within 0.2% 2. Minimum value for bit rate = 448 kB/s Typical value for bit rate = 384 kB/s Maximum value for bit rate = 32 kB/s August 1993 33 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm SOT205-1 c y X 33 A 23 34 22 ZE e E HE A A2 (A 3) A1 wM θ bp Lp pin 1 index 44 L 12 detail X 1 11 ZD e v M A wM bp D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 2.60 0.25 0.05 2.3 2.1 0.25 0.50 0.35 0.25 0.14 14.1 13.9 14.1 13.9 1 19.2 18.2 19.2 18.2 2.35 2.0 1.2 0.3 0.15 0.1 Z D (1) Z E (1) 2.4 1.8 2.4 1.8 θ o 7 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC SOT205-1 133E01A August 1993 JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 97-08-01 34 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications If wave soldering cannot be avoided, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9397 750 00192). Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. August 1993 SAA2520 35 Philips Semiconductors Preliminary specification Stereo filter and codec for MPEG layer 1 audio applications SAA2520 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. August 1993 36