INTEGRATED CIRCUITS DATA SHEET UDA1335H Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) Preliminary specification File under Integrated Circuits, IC01 1998 Aug 28 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) UDA1335H FEATURES Document references General • “USB Specification” • USB stereo audio record and playback system with 20 bits analog-to-digital conversion (with 5 to 55 kHz sample frequency range) and adaptive 20 bits digital-to-analog conversion (with 5 to 55 kHz sample frequency range) with integrated filtering • “USB Device Class Definition for Audio Devices” • “Device Class Definition for Human Interface Devices (HID)” • “USB HID Usage Table” • “USB Common Class Specification”. • USB-compliant audio/HID device • Supports 12 Mbits/s ‘full speed’ serial data transmission GENERAL DESCRIPTION • Fully automatic ‘Plug-and-Play’ operation The UDA1335H is a stereo CMOS codec incorporating bitstream converters designed for implementation in USB-compliant audio peripherals and multimedia audio applications. The UDA1335H is an adaptive asynchronous sink USB audio device with a continuous sampling frequency range from 5 to 55 kHz. It contains a USB interface, an embedded microcontroller, an Analog-to-Digital Interface (ADIF) and an Asynchronous Digital-to-Analog Converter (ADAC). • Supports multiple audio data formats (8, 16 and 24 bits) • 5.0 and 3.3 V power supply • Low power consumption • Efficient power management • On-chip master clock oscillators, only an external crystal is required • High linearity • Wide dynamic range The USB interface is the interface between the USB, the ADIF, the ADAC and the microcontroller. The USB interface consists of an analog front-end and a USB processor. The analog front-end transforms the differential USB data into a digital data stream. The USB processor buffers the incoming and outgoing data from the analog front-end and handles all low-level USB protocols. The USB processor selects the relevant data from the universal serial bus, performs an extensive error detection and separates control information (input and output) and audio information (input and output). The control information is made accessible to the microcontroller. The audio information received from the PC becomes available at the digital I/O output or is fed directly to the ADAC. The audio information to be transmitted to the PC is delivered by the ADIF or by the digital I2S-bus interface. • Superior signal-to-noise ratio • Low total harmonic distortion • Supports headphone and line output • Partly programmable USB descriptors and configuration via the I2C-bus. Sound processing (for digital-to analog conversion) • Separate digital volume control for left and right channel • Soft mute • Digital bass and treble tone control • External Digital Sound Processor (DSP) option possible via standard I2S-bus or Japanese digital I/O format • Selectable clipping prevention The microcontroller handles the high-level USB protocols, translates the incoming control requests and manages the user interface via general purpose pins and an I2C-bus. • Selectable Dynamic Bass Boost (DBB) • On-chip digital de-emphasis. 1998 Aug 28 2 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) The firmware for the microcontroller must be located in an external (E)PROM. UDA1335H Via the digital I/O-bus, an external DSP can be used for adding extra sound processing features for the audio received from the PC. The ADAC enables the wide and continuous range of input sampling frequencies. By means of a Sample Frequency Generator (SFG), the ADAC is able to reconstruct the average sample frequency from the incoming audio samples. The ADAC also performs the sound processing. The ADAC consists of a FIFO, a unique audio feature processing DSP, the SFG, digital upsampling filters, a variable hold register, a Noise Shaper (NS) and a Filter Stream DAC (FSDAC) with integrated filter and line output drivers. The audio information is applied to the ADAC via the USB processor or via the digital I/O input. The UDA1335H supports the digital I/O and the I2S-bus interface, with standard I2S-bus data input format and the LSB justified serial data input format with word lengths of 16, 18 and 20 bits. The wide dynamic range of the bitstream conversion technique used in the UDA1335H guarantees a high audio sound quality. APPLICATIONS • USB monitors The ADIF consists of an Programmable Gain Amplifier (PGA), an Analog-to-Digital Converter (ADC) and a Decimator Filter (DF). An Analog Phase Lock Loop (APLL) or oscillator is used for clocking the ADIF. The clock frequency for the ADIF can be controlled via the microcontroller. Several clock frequencies are possible for sampling the analog input signal at different sampling rates. • USB speakers • USB headsets • USB telephone/answering machines • USB links in consumer audio devices. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME UDA1335H 1998 Aug 28 QFP64 DESCRIPTION plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 × 20 × 2.8 mm 3 VERSION SOT319-2 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) UDA1335H QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDE supply voltage periphery 4.75 5.0 5.25 V VDDI supply voltage core 3.0 3.3 3.6 V IDD(tot) total supply current − 60 tbf mA IDD(tot)(ps) total supply current in power-saving note 1 mode − 360 − µA − −90 −80 dB − 0.0032 0.01 % Dynamic performance DAC (THD + N)/S total harmonic distortion plus noise-to-signal ratio fs = 44.1 kHz; RL = 5 kΩ fi = 1 kHz (0 dB) fi = 1 kHz (−60 dB) − −30 −20 dB − 3.2 10 % 95 − dBA 0.66 − V S/N signal-to-noise ratio at bipolar zero A-weighted at code 0000H 90 Vo(FS)(rms) full-scale output voltage (RMS value) VDD = 3.3 V − Dynamic performance PGA and ADC (THD + N)/S S/N total harmonic distortion plus noise-to-signal ratio signal-to-noise ratio fs = 44.1 kHz; PGA gain = 0 dB fi = 1 kHz; (0 dB); Vi = 1.0 V (RMS) − −85 −80 dB − 0.0056 0.01 % fi = 1 kHz (−60 dB) − −30 −20 dB − 3.2 10.0 % 90 95 − dBA Vi = 0.0 V General characteristics fi(s) audio input sample frequency 5 − 55 kHz Tamb operating ambient temperature 0 25 70 °C Note 1. Exclusive the IDDE current which depends on the components connected to the I/O pins. 1998 Aug 28 4 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) UDA1335H BLOCK DIAGRAM handbook, full pagewidth VSSX 24 XTAL1b 25 XTAL2b VDDX 26 VDDA3 52 XTAL2a 53 CLK D+ D− P0.7 to P0.0 P2.0 to P2.7 27 8 6 7, 5, 3, 64, 62, 60, 58, 56 14, 16, 18, 20, 22, 23, 29, 30 OSC 48 MHz ANALOG FRONT-END TIMING 28 XTAL1a 54 VSSA3 55 GP2/DO 63 GP3/WSO 1 GP4/BCKO 2 GP1/DI 13 GP0/BCKI 17 GP5/WSI 15 PSEN 31 DA 57 WS 59 BCK 61 OSC ADC ANALOG PLL USB-PROCESSOR 48 ALE 50 VDDI 11 VSSI VSSE 12 VDDE 32 33 VDDO VSSO 38 VDDA1 39 VSSA1 42 VDDA2 VSSA2 44 DIGITAL I/O MUX 19 SCL MICROCONTROLLER 21 SDA TEST CONTROL BLOCK 35 TC 36 RTCB 34 VOUTL 37 VOUTR FIFO SAMPLE FREQUENCY GENERATOR I2S-BUS INTERFACE AUDIO FEATURE PROCESSING DSP DECIMATOR FILTER EA 9 10 4 UPSAMPLE FILTERS SHTCB VARIABLE HOLD REGISTER VINL 43 VINR 47 VRN 49 VRP 51 PGA LEFT Σ∆ ADC PGA RIGHT Σ∆ ADC 3rd-ORDER NOISE SHAPER UDA1335H LEFT DAC − + + REFERENCE VOLTAGE 45, 46 41 40 n.c. Vref(AD) Vref(DA) Fig.1 Block diagram. 1998 Aug 28 5 RIGHT DAC − MBK838 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) UDA1335H PINNING PIN QFP64 I/O GP3/WSO 1 I/O general purpose pin 3 or word select output GP4/BCKO 2 I/O general purpose pin 4 or bit clock output P0.5 3 I/O port 0.5 of the microcontroller SYMBOL DESCRIPTION SHTCB 4 I P0.6 5 I/O port 0.6 of the microcontroller shift clock of the test control block (active HIGH) D− 6 I/O negative data line of the differential data bus, conforms to the USB standard P0.7 7 I/O port 0.7 of the microcontroller D+ 8 I/O positive data line of the differential data bus, conforms to the USB standard VDDI 9 − digital supply voltage for core VSSI 10 − digital ground for core VSSE 11 − digital ground for I/O pads VDDE 12 − digital supply voltage for I/O pads GP1/DI 13 I/O general purpose pin 1 or data input P2.0 14 I/O port 2.0 of the microcontroller GP5/WSI 15 I/O general purpose pin 5 or word select input P2.1 16 I/O port 2.1 of the microcontroller GP0/BCKI 17 I/O general purpose pin 0 or bit clock input P2.2 18 I/O port 2.2 of the microcontroller SCL 19 I/O serial clock line I2C-bus P2.3 20 I/O port 2.3 of the microcontroller SDA 21 I/O serial data line I2C-bus P2.4 22 I/O port 2.4 of the microcontroller P2.5 23 I/O port 2.5 of the microcontroller VSSX 24 − crystal oscillator ground (48 MHz) XTAL1b 25 I crystal input (analog; 48 MHz) XTAL2b 26 O crystal output (analog; 48 MHz) CLK 27 O 48 MHz clock output signal VDDX 28 − supply crystal oscillator (48 MHz) P2.6 29 I/O port 2.6 of the microcontroller P2.7 30 I/O port 2.7 of the microcontroller PSEN 31 I/O program store enable (active LOW) VDDO 32 − VSSO 33 − operational amplifier ground VOUTL 34 O voltage output left channel TC 35 I test control input (active HIGH) RTCB 36 I asynchronous reset input of the test control block (active HIGH) VOUTR 37 O voltage output right channel VDDA1 38 − analog supply voltage 1 VSSA1 39 − analog ground 1 1998 Aug 28 supply voltage for operational amplifier 6 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) UDA1335H PIN QFP64 I/O Vref(DA) 40 O reference voltage output DAC Vref(AD) 41 O reference voltage output ADC VDDA2 42 − analog supply voltage 2 VINL 43 I input signal left channel PGA VSSA2 44 − analog ground 2 n.c. 45 − not connected n.c. 46 − not connected VINR 47 I input signal right channel PGA EA 48 − external access (active LOW) VRN 49 I negative reference input voltage ADC ALE 50 − address latch enable (active HIGH) SYMBOL DESCRIPTION VRP 51 I positive reference input voltage ADC VDDA3 52 − supply voltage for crystal oscillator and analog PLL XTAL2a 53 O crystal output (analog; ADC) XTAL1a 54 I crystal input (analog; ADC) VSSA3 55 − crystal oscillator and analog PLL ground P0.0 56 I/O DA 57 I P0.1 58 I/O WS 59 I P0.2 60 I/O BCK 61 I P0.3 62 I/O port 0.3 of the microcontroller GP2/DO 63 I/O general purpose pin 2 or data output P0.4 64 I/O port 0.4 of the microcontroller 1998 Aug 28 port 0.0 of the microcontroller data Input (digital) port 0.1 of the microcontroller word select input (digital) port 0.2 of the microcontroller bit clock input (digital) 7 Philips Semiconductors Preliminary specification 52 VDDA3 53 XTAL2a 54 XTAL1a 55 VSSA3 56 P0.0 UDA1335H 57 DA 58 P0.1 59 WS 60 P0.2 61 BCK 62 P0.3 64 P0.4 handbook, full pagewidth 63 GP2/DO Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) GP3/WSO 1 51 VRP GP4/BCKO 2 50 ALE P0.5 3 49 VRN SHTCB 4 48 EA P0.6 5 47 VINR D− 6 46 n.c. P0.7 7 45 n.c. D+ 8 44 VSSA2 VDDI 9 43 VINL UDA1335H VSSI 10 42 VDDA2 VSSE 11 41 Vref(AD) VDDE 12 40 Vref(DA) GP1/DI 13 39 VSSA1 P2.0 14 38 VDDA1 GP5/WSI 15 37 VOUTR 36 RTCB P2.1 16 35 TC GP0/BCKI 17 Fig.2 Pin configuration. 1998 Aug 28 8 VDDO 32 PSEN 31 P2.7 30 P2.6 29 VDDX 28 CLK 27 XTAL2b 26 XTAL1b 25 VSSX 24 P2.5 23 33 VSSO P2.4 22 SCL 19 SDA 21 34 VOUTL P2.3 20 P2.2 18 MBK841 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) The MMU is the digital back-end of the USB processor. It handles the temporary data storage of all USB packets that are received or sent over the bus. Three types of packets are defined on the USB. These are: FUNCTIONAL DESCRIPTION The Universal Serial Bus (USB) Data and power is transferred via the USB over a 4-wire cable. The signalling occurs over two wires and point-to-point segments. The signals on each segment are differentially driven into a cable of 90 Ω intrinsic impedance. The differential receiver features input sensitivity of at least 200 mV and sufficient common mode rejection. • Token packets • Data packets • Handshake packets. The token packet contains information about the destination of the data packet. The audio data is transferred via an isochronous data sink endpoint or source endpoint and, consequently, no handshaking mechanism is used. The MMU also generates a 1 kHz clock that is locked to the USB Start Of Frame (SOF) token. The analog front-end The analog front-end is an on-chip generic USB transceiver. It is designed to allow voltage levels up to VDD from standard or programmable logic to interface with the physical layer of the USB. It is capable of receiving and transmitting serial data at full speed (12 Mbits/s). The Audio Sample Redistribution (ASR) The ASR reads the audio samples from the MMU and distributes these samples equidistant over a 1 ms frame period. The distributed audio samples are translated by the digital I/O module to standard I2S-bus format or Japanese digital I/O format. The ASR generates the bit clock and the word select signal of the digital I/O. The digital I/O formats the received audio samples to one of the four specified serial digital audio formats (I2S-bus, 16, 18 or 20 bits LSB-justified). The USB processor The USB processor forms the interface between the analog front-end, the ADIF, the ADAC and the microcontroller. The USB processor consists of: • The Philips Serial Interface Engine (PSIE) • The Memory Management Unit (MMU) • The Audio Sample Redistribution (ASR) module. The microcontroller The Philips Serial Interface Engine and Memory Management Unit (PSIE/MMU) The microcontroller receives the control information selected from the USB by the USB processor. It handles the high-level USB protocols and the user interfaces. The PSIE/MMU translates the electrical USB signals into bytes and signals. Depending upon the USB device address and the USB endpoint address, the USB data is directed to the correct endpoint buffer on the PSIE/MMU interface. The data transfer could be of bulk, isochronous, control or interrupt type. The USB device address is configured during the enumeration process. The major task of the software process, that is mapped upon the microcontroller, is to control the different modules of the UDA1335H in such a way that it behaves as a USB device. Therefore the microcontroller: The UDA1335H has four endpoints. These are: • Interprets the USB requests and maps them upon the UDA1335H application • Control endpoint 0 • Status interrupt endpoint • Controls the internal operation of the UDA1335H, the digital I/O pins and the GP I/O pins • Isochronous data sink endpoint • Isochronous data source endpoint. • Communicates with the external world (external controller, EEPROM) using the I2C-bus facility and the GP I/O pins. The amount of bytes/packet on the control endpoint is limited by the PSIE/MMU hardware to 8 bytes/packet. The microcontroller does not handle the audio stream. The UDA1335H will be delivered with USB compliant firmware. The firmware must be located in an external (E)PROM. The PSIE is the digital front-end of the USB processor. This module recovers the 12 MHz USB clock, detects the USB sync word and handles all low-level USB protocols and error checking. 1998 Aug 28 UDA1335H 9 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) UDA1335H The Analog-to-Digital Interface (ADIF) The Decimation Filter (DF) The ADIF is used for sampling an analog input signal from a microphone or line input and sending the audio samples to the USB interface. The ADIF consists of a stereo Programmable Gain Amplifier (PGA), a stereo Analog-to-Digital Converter (ADC) and Decimation Filters (DFs). The sample frequency of the ADC is determined by the ADC clock (see Section “The timing of the analog-to-digital interface”). The user can also select a digital serial input instead of an analog input. In this event the sample frequency is determined by the continuous WS clock with a range between 5 to 55 kHz. Digital serial input is possible with four formats (I2S-bus, 16, 18 or 20 bits LSB-justified). The decimator filter converts the audio data from 128fs down to 1fs with a word width of 8, 16 or 24 bits. This data will be transmitted over the USB as mono or stereo in 1, 2 or 3 bytes/sample. The decimator filters are clocked by the ADC clock. The Programmable Gain Amplifier circuit (PGA) Using the analog PLL the user can select 3 clock frequencies via the microcontroller. The timing of the analog-to-digital interface The clock source of the ADIF is the analog PLL or the ADC oscillator. The preferred clock source can be selected during start-up of the device (configuration map). The ADC clock used for the ADC and decimation filters is obtained by dividing the clock signal coming from the analog PLL or from the ADC oscillator by a factor Q. This circuit can be used for a microphone or line input. The input audio signals can be amplified by 7 different gains. The preferred gain is selected during start-up of the device (configuration map). By connecting the appropriate crystal the user can choose any clock signal between 8.192 and 14.08 MHz via the ADC oscillator. The gain settings are given in Table 1. Table 1 Table 2 The selectable gains of the PGA SETTING GAIN UNIT 000 −3 dB 001 0 dB 010 3 dB 011 9 dB 100 15 dB 101 21 dB 11X 27 dB FCODE APLL CLOCK FREQUENCY (MHz) 00 11.2896 01 8.1920 10 12.2880 11 11.2896 The dividing factor Q can be selected via the microcontroller. With this dividing factor Q the user can select a range of ADC clock signals allowing several different sample frequencies (see Table 3). The Analog-to-Digital Converter (ADC) The stereo ADC of the UDA1335H consists of two 3rd-order Sigma-Delta modulators. They have a modified Ritchie-coder architecture in a differential switched capacitor implementation. The oversampling ratio is 128. Both ADCs can be switched off in power saving mode (left and right separate). The ADC clock is generated by the analog PLL or the ADC oscillator. 1998 Aug 28 The analog PLL clock output frequencies 10 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) Table 3 UDA1335H ADC clock frequencies and sample frequencies based upon using the APLL as a clock source (analog input topology 1), see note 1. APLL CLOCK FREQUENCY (MHz) DIVIDE FACTOR Q ADC CLOCK FREQUENCY (MHz) SAMPLE FREQUENCY (kHz) 1 2 4 8 1 2 4 8 1 2 4 8 4.096 2.048 1.024 0.512 (not supported) 5.6448 2.8224 1.4112 0.7056 6.144 3.072 1.536 0.768 32 16 8 4 (not supported) 44.1 22.05 11.025 5.5125 48 24 12 6 8.1920 11.2896 12.2880 Note 1. By using the APLL as a clock source 12 sample frequencies will be reported to the USB host. Table 4 ADC clock frequencies and sample frequencies based upon using the OSCAD as a clock source (analog input topology 4), see note 1 OSCAD CLOCK FREQUENCY (MHz) DIVIDE FACTOR Q ADC CLOCK FREQUENCY (MHz) SAMPLE FREQUENCY (kHz) fosc(2) Q(3) fosc/(2Q) fosc/(256Q)(4) Notes 1. By using the OSCAD as a clock source, the sample frequency and the Q dividing factor must be filled in the configuration map. Only this one sample frequency will be reported to the USB host. 2. The oscillator frequency (and therefore the crystal) of OSCAD must be between 8.192 and 14.08 MHz. 3. The Q factor can be 1, 2, 4 or 8. 4. Sample frequencies below 5 kHz and above 55 kHz are not supported. 1998 Aug 28 11 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) UDA1335H Table 5 The Asynchronous Digital-to-Analog Converter (ADAC) The ADAC receives USB audio information from the USB processor or from the digital I/O-bus. The ADAC is able to reconstruct the sample clock from the rate at which the audio samples arrive and handles the audio sound processing. After the processing, the audio signal is upsampled, noise-shaped and converted to analog output voltages capable of driving a line output. The ADAC consists of: Frequency domains for audio processing by the DSP DOMAIN SAMPLE FREQUENCY (kHz) 1 5 to 12 2 12 to 25 3 25 to 40 4 40 to 55 The upsampling filters and variable hold function • A Sample Frequency Generator (SFG) • An audio feature processing DSP After the audio feature processing DSP two upsampling filters and a variable hold function increase the oversampling rate to 128fs. • Two digital upsampling filters and a variable hold register The noise shaper • FIFO registers • A digital Noise Shaper (NS) A 3rd-order noise shaper converts the oversampled data to a noise-shaped bitstream for the FSDAC. The in-band quantization noise is shifted to frequencies well above the audio band. • A Filter Stream DAC (FSDAC) with integrated filter and line output drivers. The Sample Frequency Generator (SFG) The Filter Stream DAC (FSDAC) The SFG controls the timing signals for the asynchronous digital-to-analog conversion. By means of a digital PLL, the SFG automatically recovers the applied sampling frequency and generates the accurate timing signals for the audio feature processing DSP and the upsampling filters. The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post filter is not needed because of the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. First-In First-Out (FIFO) registers The FIFO registers are used to store the audio samples temporarily coming from the USB processor or from the digital I/O input. The use of a FIFO (in conjunction with the SFG) is necessary to remove all jitter present on the incoming audio signal. USB Audio Playback Recording Peripheral (APRP) descriptors In a typical USB environment the PC has to know which kind of devices are connected. For this purpose each device contains a number of USB descriptors. These descriptors describe, from different points of view (USB configuration, USB interface and USB endpoint), the capabilities of a device. Each of them can be requested by the host. The collection of descriptors is denoted as a descriptor map. This descriptor map will be reported to the USB host during enumeration and on request. The audio feature processing DSP A DSP processes the sound features. The control and mapping of the sound features is explained in Section “Controlling the USB APRP”. Depending on the sampling rate (fs) the DSP knows four frequency domains in which the treble and bass are regulated. The domain is chosen automatically. The USB descriptors and their most important fields, in relationship to the characteristics of the UDA1335H are explained briefly below. 1998 Aug 28 12 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) UDA1335H AUDIO FUNCTION TOPOLOGIES Four audio function Input topologies and two audio function output topologies are supported by the UDA1335H. Each configuration map can select only one Input and one output topology. The descriptors and the supported requests depend on the selected topologies in the active configuration map. Figures 3 and 4 illustrate the different audio Input and output topologies. INPUT TERMINAL handbook, full pagewidth FEATURE UNIT OUTPUT TERMINAL FU IT OT MBK530 Fig.3 One audio output function topology (with or without bass boost) is supported. handbook, full pagewidth Analog Input Terminal IT OT Output Terminal a. Analog topology 1 (using APLL clock source). Input Terminal 1 Input Terminal 2 IT SELECTOR UNIT SU OT Output Terminal OT Output Terminal OT Output Terminal IT b. Analog topology 2. Digital Input Terminal IT c. Digital topology 3. Analog Input Terminal IT MGL437 d. Analog topology 4 (using OSCAD clock source). Fig.4 Four input function topologies are supported. 1998 Aug 28 13 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) UDA1335H THE STANDARD AUDIO STREAMING INTERFACE DESCRIPTOR GENERAL DESCRIPTORS FOR THE ISOCHRONOUS DATA SINK ENDPOINT The UDA1335H supports one configuration containing a control interface, two audio interfaces and a HID interface. The descriptor map that describes this configuration is partly fixed and partly programmable. In this section the descriptors are given for interface 1 which is used for receiving isochronous audio data from the host. The programmable part can be retrieved from one of four configuration maps located in the firmware or from an I2C-bus EEPROM. At start-up time one of four internal configuration maps can be selected depending on the logical combination of GP3 and GP4. It is possible to overwrite this configuration map with a configuration map loaded from an I2C-bus EEPROM. Although in this specific UDA1335H application no endpoint control properties can be used on the isochronous adaptive sink endpoint, the descriptors are still necessary to inform the host about the definition of this endpoint: isochronous, adaptive, sink, continuous sampling frequency (at input side of this endpoint) with a lower boundary of 5 kHz and an upper boundary of 55 kHz. AUDIO DEVICE CLASS SPECIFIC DESCRIPTORS The audio class specific descriptors can be requested with the ‘Get Descriptor: configuration request’, which returns all the descriptors, except the device descriptor. The audio device class is partly specified with standard descriptors and partly with specific audio device class descriptors. The standard descriptors specify the number and the type of the interface or endpoint. The UDA1335H supports 7 different audio modes: For each alternate setting with audio, a maximum bandwidth is claimed as indicated in the standard isochronous audio data endpoint descriptor wMaxPacketSize field. To allow a small overshoot in the number of audio samples per packet, the top sample frequency of 55 kHz is taken in the calculation of the bandwidth for each alternate setting. For each alternate setting, with its own isochronous audio data endpoint descriptor, wMaxPacketSize field is then defined as described in Table 6. • 8-bit PCM mono or stereo audio data • 16-bit PCM mono or stereo audio data • 24-bit PCM mono or stereo audio data • Zero bandwidth mode. Each mode is defined as an alternate setting of the audio interface, selectable with the standard audio streaming interface descriptor bAlternateSetting field. Table 6 The seven alternate settings are described in more detail by the specific audio device class descriptors. Audio bandwidth at each audio mode ALTERNATE SETTING The UDA1335H supports the input terminal, output terminal and the feature unit descriptors. AUDIO MODE wMaxPacketSize (HEX) 1 8-bit PCM, mono 3800 2 8-bit PCM, stereo 7000 3 16-bit PCM, mono 7000 4 16-bit PCM, stereo E000 The supported sound features are: 5 24-bit PCM, mono A800 • Volume control 6 24-bit PCM, stereo 5001 The input and output terminals are not controllable via the USB. The feature unit provides the basic manipulation of the incoming logical channels. • Mute control THE STANDARD AUDIO STREAMING INTERFACE DESCRIPTOR • Treble control FOR THE ISOCHRONOUS DATA SOURCE ENDPOINT • Bass control Interface 2 is used for sending isochronous audio data to the host. It has the same alternate settings as interface 1. • Bass Boost control. The maximum number of audio data samples within a USB packet arriving on the isochronous sink endpoint is restricted by the buffer capacity of this isochronous endpoint. The maximum buffer capacity is 336 bytes/ms. The input terminals can be defined by means of wTerminalType. 1998 Aug 28 14 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) UDA1335H HUMAN INTERFACE DEVICE SPECIFIC DESCRIPTORS Controlling the USB APRP The inputs defined on the UDA1335H are transmitted via the USB to the host according to the HID class. The host responds with the appropriate settings via the audio device class for the audio related parts or via the HID class for the HID related inputs and outputs of the UDA1335H. The sound features as defined in the “USB Device Class Definition for Audio Devices” are mapped on the UDA1335H specific feature registers by the microcontroller. These specific sound features are: • Volume control (separate for left and right stereo channels, no master channel) A HID descriptor is necessary to inform the host about the conception of the user interface. The host communicates via the HID device driver using either the control pipe or the interrupt pipe. The UDA1335H is using USB endpoint 0 (control pipe) to respond to the HID specific ‘Get/Set Report request’ to receive or transmit data from or to the UDA1335H. The UDA1335H uses the status interrupt endpoint as interrupt pipe for polling asynchronous data. • Mute control (only master channel) • Treble control (only master channel) • Bass control (only master channel) • Dynamic bass boost control (only master channel). These specific features can be activated via the host (audio device class requests) or via the GP I/O pins (HID plus audio device class requests). The user is able to download the necessary configuration data for different applications (definition of the function of the GP pins, with or without digital I/O functionality etc.) via the configuration map. The mapping and control of the standard USB audio features and UDA1335H specific features is described below. The UDA1335H is a high-speed device. The maximum transaction size is 64 bytes per USB frame and the polling rate is defined at a maximum of every 1 ms. The host requests the configuration descriptor which includes the standard interface descriptor, the HID endpoint descriptor and the HID descriptor. The HID device driver of the host then requests the report descriptor. Volume control Volume control is possible via the host or via predefined GP I/O pins. The setting of 0 dB is always referenced to the maximum available volume setting. Table 7 gives the mapping of wVolume value (as defined in the “USB Device Class Definition for Audio Devices”) upon the actual volume setting of the USB APRP. When using the UDA1335H, the range is 0 dB down to −60 dB (in steps of 1 dB) and −∞ dB. Independant control of ‘left’/’right’ volume is possible. Report descriptors are composed of pieces of information about the device. Each piece of information is called an item. All items have a 1-byte prefix that contains the item tag, type and size. In the UDA1335H only the short item basic type is used. The hosts HID device driver will parse the report descriptor and the defined items. By examining all of these items, the HID class driver is able to determine the size and composition of data reports from the device. It should be noted that wVolumeLSB B7 to B0 are not used. Values above 0 dB are returned as 0 dB. The volume value at start-up of the device is defined in the selected configuration map. The main items of the UDA1335H are input reports. Input reports are sent via the interrupt pipe (UDA1335H USB endpoint 3). Input reports can be requested by the host via the control endpoint (USB endpoint 0). Balance control is possible via the separate volume control option of both channels. Therefore the characteristics of the balance control are equal to the volume control characteristics. The UDA1335H supports a maximum of two push-buttons (six with I2C-bus expanders), which represent a certain feature of the UDA1335H. If pressed by the user the pushbutton will go to its ‘ON’ state, if not pressed the push-button will go back to its ‘OFF’ state. For more information about the input functions of the UDA1335H see the application documentation of the device. 1998 Aug 28 15 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) Table 7 UDA1335H Volume control characteristics wVOLUME (MSB) B15 B14 B13 B12 B11 B10 B9 B8 VOLUME USB SIDE (dB) VOLUME USB APRP (dB) 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 −1 −1 1 1 1 1 1 1 1 0 −2 −2 1 1 1 1 1 1 0 1 −3 −3 1 1 1 1 1 1 0 0 −4 −4 1 1 1 1 1 0 1 1 −5 −5 1 1 1 1 1 0 1 0 −6 −6 1 1 1 1 1 0 0 1 −7 −7 1 1 1 1 1 0 0 0 −8 −8 1 1 1 1 0 1 1 1 −9 −9 1 1 1 1 0 1 1 0 −10 −10 ... ... ... ... ... ... ... ... ... ... 1 1 0 0 0 1 0 1 −59 −59 1 1 0 0 0 1 0 0 −60 −60 1 1 0 0 0 0 1 1 −61 −∞ 1 1 0 0 0 0 1 0 −62 −∞ ... ... ... ... ... ... ... ... ... ... 1 0 0 0 0 0 0 0 −∞ −∞ 1998 Aug 28 16 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) The mute, on the master channel is synchronized to the sample clock, so that operation always takes place on complete samples. Mute control Mute is one of the sound features as defined in the “USB Device Class Definition for Audio Devices”. The mute control request data bMute controls the position of the mute switch. The position can be either on or off. When bMute is true the feature unit is muted. When bMute is false the feature unit is not muted. A mute can be given via the host or by pressing a predefined GP pin. Treble control When the mute is active for the master channel, the value of the sample is decreased smoothly to zero following a raised cosine curve. There are 32 coefficients used to step down the value of the data, each one being used 32 times before stepping to the next. This amounts to a mute transition of 23 ms at fs = 44.1 kHz. When the mute is released, the samples are returned to the full level again following a raised cosine curve with the same coefficients being used in reversed order. Table 8 UDA1335H The treble control is available for the master channel of the UDA1335H. The treble range is from 0 to 6 dB in steps of 2 dB. It should be noted that the negative treble values as defined in the “USB Device Class Definition for Audio Devices” are not supported by the UDA1335H; values below 0 dB are returned as 0 dB. The corner frequency is 1500 Hz. Table 8 gives the mapping of the bTreble value upon the actual treble setting of the USB APRP. Treble control characteristics bTREBLE B7 B6 B5 B4 B3 B2 B1 B0 TREBLE USB HOST (dB) 0 0 0 0 0 0 0 0 0.00 0 0 0 0 0 0 0 1 0.25 0 0 0 0 0 0 1 0 0.50 0 0 0 0 0 0 1 1 0.75 0 0 0 0 0 1 0 0 1.00 0 0 0 0 0 1 0 1 1.25 0 0 0 0 0 1 1 0 1.50 0 0 0 0 0 1 1 1 1.75 0 0 0 0 1 0 0 0 2.00 0 0 0 0 1 0 0 1 2.25 0 0 0 0 1 0 1 0 2.50 0 0 0 0 1 0 1 1 2.75 0 0 0 0 1 1 0 0 3.00 0 0 0 0 1 1 0 1 3.25 TREBLE USB APRP (dB) 0 2 4 ... 0 0 0 1 0 1 0 1 5.25 0 0 0 1 1 1 0 1 7.25 6 ... 6 ... 0 0 1 0 0 1 0 1 9.25 0 1 1 1 1 1 1 1 31.75 6 ... 1998 Aug 28 17 6 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) UDA1335H Bass control The bass control is available for the master channel of the UDA1335H. The bass range is from 0 to approximately 24 dB in steps of 2 dB. It should be noted that the negative bass values as defined in the “USB Device Class Definition for Audio Devices” are not supported by the UDA1335H; values below 0 dB are returned as 0 dB. The corner frequency is 75 Hz. Table 9 gives the mapping of the bBass value upon the actual bass setting of the USB APRP. Table 9 Bass control characteristics bBASS B7 B6 B5 B4 B3 B2 B1 B0 BASS USB HOST (dB) 0 0 0 0 0 0 0 0 0.00 0 0 0 0 0 0 0 1 0.25 0 0 0 0 0 0 1 0 0.50 0 0 0 0 0 0 1 1 0.75 0 0 0 0 0 1 0 0 1.00 0 0 0 0 0 1 0 1 1.25 0 0 0 0 0 1 1 0 1.50 0 0 0 0 0 1 1 1 1.75 0 0 0 0 1 0 0 0 2.00 0 0 0 0 1 0 0 1 2.25 0 0 0 0 1 0 1 0 2.50 0 0 0 0 1 0 1 1 2.75 0 0 0 0 1 1 0 0 3.00 0 0 0 0 1 1 0 1 3.25 BASS USB APRP (dB) 0 1.7 3.6 ... 0 0 0 1 0 1 0 1 5.25 5.4 ... 0 0 0 1 1 1 0 1 7.25 0 0 1 0 0 1 0 1 9.25 7.4 ... 9.4 ... 0 0 1 0 1 1 0 1 11.25 11.3 ... 0 0 1 1 0 1 0 1 13.25 0 0 1 1 1 1 0 1 15.25 13.3 ... 15.2 ... 0 1 0 0 0 1 0 1 17.25 17.3 ... 0 1 0 0 1 1 0 1 19.25 19.2 ... 0 0 1 1 1 0 1 1 21.25 ... 1998 Aug 28 18 21.2 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) UDA1335H bBASS B7 B6 B5 B4 B3 B2 B1 B0 BASS USB HOST (dB) BASS USB APRP (dB) 0 1 0 1 0 1 0 1 23.25 23.2 ... 0 1 1 0 0 1 0 1 25.25 0 1 1 0 1 1 0 1 27.25 23.2 ... 23.2 ... 0 1 1 1 0 1 0 1 29.25 23.2 ... 0 1 1 1 1 1 0 1 31.25 0 1 1 1 1 1 1 1 31.75 23.2 ... 23.2 Dynamic bass boost control Start-up and configuration of the UDA1335H Bass boost is one of the sound features as defined in the “USB Device Class Definition for Audio Devices”. The bass boost control request data bBassBoost controls the position of the bass boost switch. The position can be either on or off. When bBassBoost is true the bass boost is activated. When bBassBoost is false the bass boost is off. START-UP OF THE UDA1335H After power-on, an internal power-on reset signal becomes HIGH after a certain RC time (R = 5000 Ω, C = Cref). During 20 ms after power-on reset the UDA1335H has to initiate the internal settings. After the power-on reset the UDA1335H becomes master of the I2C-bus. The UDA1335H tries to read the eventually connected I2C-bus EEPROM and if an dedicated EEPROM is detected, the internal descriptors are overwritten and the selected port configuration is applied. If no EEPROM is detected, the UDA1335H tries to read the logic levels of GP3 and GP4. A choice can be made from four configuration maps via these two GP pins. When clipping prevention is active, the bass is reduced to avoid clipping with high volume settings. Bass boost is selectable via the configuration map. Clipping prevention When clipping prevention is ON and the sum of bass plus volume gives clipping, the bass is reduced. When clipping prevention is ON and the sum of treble plus volume gives clipping, the treble is reduced. Clipping prevention and clipping level are selectable via the configuration map. For more information about clipping prevention and the clipping level see the application documentation. CONFIGURATION SELECTION OF THE UDA1335H VIA A DIODE MATRIX The UDA1335H uses a configuration map to hold a number of specific configurable data on hardware, product, component and USB configuration level. At start-up, without EEPROM, the UDA1335H will scan the logic levels of GP3 and GP4. With these two GP pins it is possible to select one of the four possible configuration maps which are held in the external (E)PROM. This selection can be achieved via a diode matrix (see Fig.5). De-emphasis De-emphasis is one of the properties which is not supported by the USB. De-emphasis for 44.1 kHz can be predefined in the configuration map selected at start-up of the UDA1335H. 1998 Aug 28 19 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) UDA1335H firmware of the microcontroller. The layout of the configuration map is fixed, the values (except bytes 0 and 1) are user definable. If the user wants to change e.g. the manufacturer name this can be achieved via the EEPROM code. After selecting an internal configuration map the user cannot change the chosen settings for the GP pins, internal configuration, descriptors etc. The UDA1335H supports a maximum of two push-buttons (six with I2C-bus expanders), which represent a certain feature of the UDA1335H. The communication between the UDA1335H and the external I2C-bus device is based on the standard I2C-bus protocol given in the Philips specification “The I2C-bus and how to use it (including specifications)”, which can be ordered using the code 9398 393 40011. The I2C-bus has two lines; a clock line SCL and a serial data line SDA (see Fig.6). The UDA1335H supports a maximum of three outputs for e.g. user LEDs. For more information about the four configuration maps located in the (E)PROM and the input and output functions of the UDA1335H see the application documentation. CONFIGURATION OPTIONS OF THE UDA1335H VIA AN I2C-BUS EEPROM At start-up, the UDA1335H will address I2C-bus slave address 0 × A0H and will check the first two byte locations of the I2C-bus device with 0 × 55H and 0 × AAH. If a match occurs, the UDA1335H assumes that this I2C-bus device is an EEPROM which is dedicated to the UDA1335H. It will then read the configuration map stored in this EEPROM instead of one of four configuration maps located in the 3.3 V handbook, full pagewidth 3.3 V 3.3 V 22 kΩ 3.3 V 22 kΩ 22 kΩ GP3 GP4 TR3 KEY 1 SW1 1.5 kΩ KEY 2 SW2 22 kΩ TR1 TR2 5 Vbus D1 D2 22 kΩ USB-B connector 1 1 2 22 kΩ 2 GP5 22 kΩ 1 2 Vbus 22 Ω 3 D− D+ 22 Ω 4 MGL480 6 10 nF 22 pF 22 pF 10 nF Fig.5 Diode matrix selection. 1998 Aug 28 20 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... t LOW t BUF tr tf t HD;STA t SP Philips Semiconductors Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) 1998 Aug 28 SDA 21 SCL S t HD;DAT t SU;DAT t HIGH t SU;STA MBC611 P Preliminary specification Fig.6 Definition of timing of the I2C-bus. t SU;STO Sr UDA1335H handbook, full pagewidth t HD;STA P Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) UDA1335H Table 10 Control options for the UDA1335H via the EEPROM configuration map; note 1 BYTE (HEX) AFFECTS COMMENTS BIT VALUE 0 recognition pattern do not change it 55H 1 recognition pattern do not change it AAH 2 clocks control register selection ADC clock source 7 0 = ADC clock from APLL 1 = ADC clock from OSCAD divide factor 6 and 5 00 = ADC clock divided-by-1 01 = ADC clock divided-by-2 10 = ADC clock divided-by-4 11 = ADC clock divided-by-8 clock ADAC 4 0 clock 48 MHz internal 3 0 clock recovered PSIE/MMU 2 0 ADC clock 1 0 power on OSCAD 0 0 3 reset generator and APLL control register 00H 4 power control register analog modules 00H 5 ASR control register robust word clock serial I2S-bus 7 output format 6 and 5 1 00 = I2S-bus 01 = 16-bit LSB 10 = 18-bit LSB 11 = 20-bit LSB phase inversion (right output) 4 0 = mono phase inversal off 1 = mono phase inversal on bits per sample modi 3 and 2 00 = reserved 01 = 8-bit audio 10 = 16-bit audio 11 = 24-bit audio mono or stereo operation 1 ASR register start-up mode 0 0 = mono 1 = stereo 1998 Aug 28 22 1 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) BYTE (HEX) 6 AFFECTS PGA control register input terminal 1 (all analog input topologies) COMMENTS UDA1335H BIT VALUE reserved 7 X PGA internal setting (do not change it) 6 0 PGA gain selection right channel 5 to 3 000 = −3 dB 001 = 0 dB 010 = 3 dB 011 = 9 dB 100 = 15 dB 101 = 21 dB 110 = 27 dB 111 = 27 dB PGA gain selection left channel 2 to 0 000 = −3 dB 001 = 0 dB 010 = 3 dB 011 = 9 dB 100 = 15 dB 101 = 21 dB 110 = 27 dB 111 = 27 dB 7 PGA control register input terminal 2 (only for analog input topology 2) reserved 7 X PGA internal setting (do not change it) 6 0 PGA gain selection right channel 5 to 3 000 = −3 dB 001 = 0 dB 010 = 3 dB 011 = 9 dB 100 = 15 dB 101 = 21 dB 110 = 27 dB 111 = 27 dB PGA gain selection left channel 2 to 0 000 = −3 dB 001 = 0 dB 010 = 3 dB 011 = 9 dB 100 = 15 dB 101 = 21 dB 110 = 27 dB 111 = 27 dB 1998 Aug 28 23 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) BYTE (HEX) 8 AFFECTS ADIF control register COMMENTS reserved UDA1335H BIT 7 number of bits per audio sample to be transmitted to the host 6 and 5 VALUE X 00 = reserved 01 = 8 bits audio samples 10 = 16 bits audio samples 11 = 24 bits audio samples mono/stereo selection 4 0 = mono 1 = stereo selection audio input channel 3 0 = digital serial audio input 1 = analog input selection high-pass filter of the decimation module I2S-bus input serial input format 2 0 = high-pass filter off 1 = high-pass filter on 1 and 0 00 = I2S-bus 01 = 16-bit LSB 10 = 18-bit LSB 11 = 20-bit LSB 9 ADAC feature setting register selection ADAC mode register audio feature mode de-emphasis 7 0 6 and 5 11 4 0 = de-emphasis off 1 = de-emphasis on 0 = L → L, R → R channel manipulation 3 synchronous/asynchronous 2 0 mute control 1 1 reset ADAC 0 0 1 = L → R, R → L A ADAC lock mode register selection ADAC mode register 7 1 digital PLL lock speed 6 and 5 00 digital PLL lock mode 4 1 digital PLL mode 3 and 2 00 serial I2S-bus input format 1 and 0 00 = I2S-bus 01 = 16-bit LSB 10 = 18-bit LSB 11 = 20-bit LSB 1998 Aug 28 24 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) BYTE (HEX) B AFFECTS I/O selection register COMMENTS UDA1335H BIT VALUE clipping 7 0 = clipping prevention OFF expander 6 0 = no I2C-bus expander used 1 = clipping prevention ON 1 = I2C-bus expander used selector output (GP2) 5 0 = selector state normal 1 = selector state inverted mute/standby expander 4 mute/standby USB APRP 3 0 = mute 1 = standby 0 = mute 1 = standby C output pin 3 2 polarity output pins output pin 2 1 0 = inverted logic output pin 1 0 1 = normal logic output pin function 1 D output pin function 2 E output pin function 3 F I2S-bus and topology selection register output I2S-bus functions are available if declared in ADC: 0 = mute LED; 1 = DBB LED 7 0 = no I2S-bus used 1 = I2S-bus used 4-pin or 6-pin I2S-bus 6 only if I2S-bus is used: 0 = 4-pin I2S-bus 1 = 6-pin I2S-bus HID usage 5 0 = HID not included reserved 4 X topology selection 3 low nibble: 1 = input topology 1 2 = input topology 2 3 = input topology 3 4 = input topology 4 all other values = input topology 1 1 = HID included 2 1 0 10 rise time power amplifier, steps of 20 ms 11 time between mute and play, steps of 1 s 12 time between mute and standby, steps of 5 s 13 selector preferred state (only applicable in input topology 2) 0 = terminal Input 1 or terminal input 2 14 DBB value steps of 1 dB with maximum 255 dB 0 = no DBB active 15 start-up volume value in dB volume = −register value 1998 Aug 28 25 1 to FF = DBB active Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) BYTE (HEX) AFFECTS 16 17 COMMENTS UDA1335H BIT VALUE maximum distortion in dB sample frequency LSB 18 mid 19 MSB 1A/1B pointer to device descriptor 0030 1C/1D pointer to configuration descriptor 0045 1E/1F pointer to HID descriptor 01F0 20/21 pointer to HID report descriptor 0210 22 number of string pointers (N + 1) maximum for N is 31 23/24 pointer to string 0 025E 25/26 pointer to string 1 0260 27/28 pointer to string 2 0290 29/2A pointer to string 3 02D0 : : 23 + 2N/ 24 + 2N pointer to string N 30 → device descriptor 45 → configuration descriptor including ADC 1F0 → and HID descriptors 210 → wDescriptorLength 212 → HID report descriptor 25E → string 0 language string 260 → string 1 manufacturer string 290 → string 2 product string 2D0 → string 3 serial number(2) 32 Notes 1. An extensive description of the USB control options is available in the “USB Device Class Definition for Audio Devices”. 2. The serial number is only supported in the external configuration map and not in the four internal configuration maps. The general purpose I/O pins (GP0 to GP5) and I2C-bus expander option The UDA1335H has 6 General Purpose (GP) I/O pins; these are pins GP0 to GP5. These can be used either for digital I/O functions or for general purposes. There are basically three port configurations: • No digital I/O communication • 4-pin digital I/O communication • 6-pin digital I/O communication. 1998 Aug 28 26 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) UDA1335H These port configurations can be chosen via the configuration map at start-up of the UDA1335H. The user can also make use of an I2C-bus expander. The usage of an I2C-bus expander (yes/no) can be indicated via the configuration map. Some of the supported HID functions are located in the I2C-bus expander. If this expander is not used, the HID functions normally located in the expander must be declared as “unassigned” in the HID report descriptor. The bit which indicates if an external expander is used must then be put on zero. Table 11 Definition of the general purpose pins and I2C-bus expander pins; notes 1 to 6 PINS NO I2S-BUS USAGE 4-PIN I2S-BUS USAGE 6-PIN I2S-BUS USAGE General purpose I/O GP5 connect/disconnect connect/disconnect WS input GP4 HID input 2 BCK output BCK output GP3 HID input 1 WS output WS output GP2 selector output DATA output DATA output GP1 mute or standby output DATA input DATA input GP0 interrupt input interrupt input BCK input I2C-bus expander; note 7 P0 HID input 3 HID input 3 connect/disconnect P1 HID input 4 HID input 4 HID input 4 P2 HID input 5 HID input 5 HID input 5 P3 HID input 6 HID input 6 HID input 6 P4 output pin 1 output pin 1 output pin 1 P5 output pin 2 output pin 2 output pin 2 P6 output pin 3 selector output selector output P7 mute or standby output mute or standby output mute or standby output Notes 1. Connect/disconnect: This pin can be used to avoid malfunction during initialisation phase of the UDA1335H. While initialization takes place, the USB can be kept disconnected while the software of the microcontroller reads in the configuration map. When the UDA1335H is ready, the USB becomes connected and enumeration can start. Using the 6-pin I2S-bus, the connect/disconnect will be moved to the I2C-bus expander. 2. HID input 1 to 6 and interrupt input: A change on the expander can be signalled to the UDA1335H via the interrupt input. After detecting this signal the UDA1335H will decode the buttons. When no expander is used, the interrupt pin must be connected to the ground. The HID input pins and the interrupt input pin on the UDA1335H are scanned each 20 ms. If the interrupt in pin indicates a change on the expander, the expander input pins are scanned once. Using the 6-pin I2S-bus, the interrupt pin is not available and the inputs on the expander are scanned every 20 ms. All input pins must have a pull-up resistor. 3. Selector output: This pin can be used for switching the audio selector as illustrated in Fig.4. If the configuration map does not request this output pin, the output is always LOW. 4. Mute output: This output is activated if the isochronous signal is not available during a certain time. The output levels and the time are programmable in the configuration map. 5. Standby output: This output is activated if the UDA1335H is muted during a certain time. The output levels and the time are programmable in the configuration map. 6. Output pins 1 to 3: All the output pins are set via the I2C-bus. The function is according the configuration map. 7. For the I2C-bus expander, the PCF8574P remote 8-bit I/O expander for I2C-bus can be used. 1998 Aug 28 27 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) UDA1335H Filter characteristics The overall filter characteristic of the UDA1335H in flat mode is given in the Fig.7. The overall filter characteristic of the UDA1335H includes the filter characteristics of the DSP in flat mode plus the filter characteristic of the FSDAC (fs = 44.1 kHz) handbook, full pagewidth MGM110 −0 −20 volume (dB) −40 −60 −80 −100 −120 −140 −160 0 10 20 30 40 50 60 70 80 90 f (kHz) Fig.7 Overall filter characteristics of the UDA1335H. 1998 Aug 28 28 100 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) UDA1335H DSP extension port An external DSP can be used for adding extra sound processing features via the digital I/O-bus. The UDA1335H supports the standard I2S-bus data protocol and the LSB-justified serial data input format with word lengths of 16, 18 and 20 bits. Using the 4-pin digital I/O-bus the UDA1335H device acts as a master, controlling the BCK and WS signals. The period of the WS signal is determined by the number of samples in the 1 ms frame of the USB. This implies that the WS signal does not have a constant time period, but is jittery. Using the 6-pin digital I/O-pins GP2, GP3 and GP4 are output pins (master) and GP0, GP1 and GP5 are input pins (slave). The characteristic timing of the I2S-bus input interface is illustrated in Figs 8 and 9. LEFT handbook, full pagewidth WS RIGHT tr tBCK(H) tf ts;WS th;WS tBCK(L) BCK Tcy ts;DAT th;DAT DATA LSB MSB MGK003 Fig.8 Timing of digital I/O input signals. 1998 Aug 28 29 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2 RIGHT >=8 3 1 2 >=8 3 BCK DATA MSB B2 LSB MSB B2 LSB MSB INPUT FORMAT I2S-BUS WS RIGHT LEFT 16 15 1 16 B15 LSB MSB 2 15 2 1 BCK MSB DATA B2 B2 B15 LSB LSB-JUSTIFIED FORMAT 16 BITS 30 WS RIGHT LEFT 18 17 16 15 2 1 18 B17 LSB MSB 17 16 15 2 1 B17 LSB 2 1 Philips Semiconductors 1 Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) book, full pagewidth 1998 Aug 28 LEFT WS BCK DATA MSB B2 B3 B4 B2 B3 B4 LSB-JUSTIFIED FORMAT 18 BITS WS LEFT 20 19 18 RIGHT 17 16 15 2 1 20 B19 LSB MSB 19 18 17 16 15 BCK MSB B2 B3 B4 B5 B6 B2 B3 B4 B5 B6 B19 LSB MGK002 Fig.9 Input formats. UDA1335H LSB-JUSTIFIED FORMAT 20 BITS Preliminary specification DATA Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) UDA1335H LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT All digital I/Os VI/O DC input/output voltage range IO output current VDDE = 5.0 V −0.5 − VDDE V − − 4 mA Temperature values Tj junction temperature 0 − 125 °C Tstg storage temperature −55 − +150 °C Tamb operating ambient temperature 0 25 70 °C note 1 −3000 − +3000 V note 2 −300 − +300 V Electrostatic handling Ves electrostatic handling Notes 1. Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor. 2. Equivalent to discharging a 200 pF capacitor through a 2.5 µH series conductor. THERMAL CHARACTERISTICS SYMBOL Rthj-a PARAMETER CONDITIONS thermal resistance from junction to ambient in free air VALUE UNIT 48 K/W RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDDE supply voltage periphery (I/O) 4.75 5.0 5.25 V VDD supply voltage (core) 3.0 3.3 3.6 V VI DC input voltage range 1998 Aug 28 for D+ and D− 0.0 − VDD V for VINL and VINR − 0.5VDD − V for digital I/Os 0.0 − VDDE V 31 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) UDA1335H DC CHARACTERISTICS VDDE = 5.0 V; VDD = 3.3 V; Tamb = 25 °C; fosc = 48 MHz; fs = 44.1 kHz; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDE digital supply voltage periphery 4.75 5.0 5.25 V VDDI digital supply voltage core 3.0 3.3 3.6 V VDDA1 analog supply voltage 1 3.0 3.3 3.6 V VDDA2 analog supply voltage 2 3.0 3.3 3.6 V VDDA3 analog supply voltage 3 3.0 3.3 3.6 V VDDO operational amplifier supply voltage 3.0 3.3 3.6 V VDDX crystal oscillator supply voltage IDDE digital supply current periphery IDDI 3.0 3.3 3.6 V − 3.7 − mA digital supply current core − 39.0 − mA IDDA1 analog supply current 1 − 3.6 − mA IDDA2 analog supply current 2 − 8.0 − mA IDDA3 analog supply current 3 − 0.9 9.0(2) mA IDDO operational amplifier supply current − 3.0 − mA IDDX crystal oscillator supply current − 1.2 13.0(3) mA Ptot total power dissipation − 200 − mW Pps total power dissipation in power saving mode − 1.2 − mW −0.5 − VDDI V − 3.6 V − − 0.3 V note 1 note 4 Inputs/outputs D+ and D− VI static DC input voltage VO(H) static DC output voltage HIGH RL = 15 kΩ 2.8 connected to GND VO(L) static DC output voltage LOW RL = 15 kΩ connected to VDD ILO high impedance data line output leakage current − − 10 µA VI(diff) differential input sensitivity 0.2 − − V VCM(diff) differential common mode range 0.8 − 2.5 V VSE(R)(th) single-ended receiver threshold voltage 0.8 − 2.0 V CIN transceiver input capacitance − − 20 pF 1998 Aug 28 pin to GND 32 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) SYMBOL PARAMETER UDA1335H CONDITIONS MIN. TYP. MAX. UNIT Digital input pins VIL LOW-level input voltage − 0.3VDDE V VIH HIGH-level input voltage 0.7VDDE − − VDDE V ILI input leakage current − − 1 µA CI input capacitance − − 5 pF Vref(AD) reference voltage PGA and ADC − 0.5VDDA2 − V Vref(ADC)(pos) positive reference voltage of the ADC − VDDA2 − V Vref(ADC)(neg) negative reference voltage of the ADC − 0.0 − V VI(PGA) DC input voltage VINL and VINR of the PGA − 0.5VDDA2 − V RI(PGA) DC input resistance at VINL and VINR of the PGA − 12.5 − kΩ PGA and ADC Filter stream DAC Vref(DA) reference voltage DAC − 0.5VDDA1 − V VO(CM) common mode output voltage − 0.5VDDA1 − V RO(VOUT) output resistance at VOUTL and VOUTR − 11 − Ω RO(L) output load resistance 2.0 − − kΩ CO(L) output load capacitance − − 50 pF Notes 1. This value depends strongly on the application. The specified value is the typical value obtained using the application diagram as illustrated in Fig.10. 2. At start-up of the OSCAD oscillator. 3. At start-up of the OSC48 oscillator. 4. Exclusive the IDDE current which depends on the components connected to the I/O pins. 1998 Aug 28 33 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) UDA1335H AC CHARACTERISTICS VDDE = 5.0 V; VDDI = 3.3 V; Tamb = 25 °C; fosc = 48 MHz; fs = 44.1 kHz; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Driver characteristics D+ and D- (full-speed mode) fo(s) audio sample output frequency 5 − 55 kHz tr rise time CL = 50 pF 4 − 20 ns tf fall time CL = 50 pF 4 − 20 ns trf(m) rise/fall time matching (tr/tf) 90 − 110 % Vcr output signal crossover voltage 1.3 − 2.0 V Ro(drive) driver output resistance 28 − 43 Ω steady-state drive Data source timings D+ and D- (full-speed mode) fi(s) audio sample input frequency 5 − 55 kHz ffs(D) full speed data rate 11.97 12.00 12.03 Mbits/s tfr(D) frame interval 0.9995 1.0000 1.0005 ms tJ1(diff) source differential jitter to next transition −3.5 +0.0 +3.5 ns tJ2(diff) source differential jitter for paired transitions −4.0 +0.0 +4.0 ns tW(EOP) source end of packet width 160 − 175 ns tEOP(diff) differential to end of packet transition skew −2.0 − +5.0 ns tJR1 receiver data jitter tolerance to next transition −18.5 0.0 +18.5 ns tJR2 receiver data jitter tolerance for paired transitions −9.0 0.0 +9.0 ns tEOPR1 end of packet width at receiver must reject as end of packet 40 − − ns tEOPR2 end of packet width at receiver must accept as end of packet 82 − − ns Serial input/output data timing fs system clock frequency − 12 − MHz fi(WS) word selection input frequency 5 − 55 kHz tr rise time − − 20 ns tf fall time − − 20 ns tBCK(H) bit clock HIGH time 55 − − ns tBCK(L) bit clock LOW time 55 − − ns ts;DAT data set-up time 10 − − ns th;DAT data hold time 20 − − ns ts;WS word selection set-up time 20 − − ns th;WS word selection hold time 10 − − ns 1998 Aug 28 34 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) SYMBOL PARAMETER UDA1335H CONDITIONS MIN. TYP. MAX. UNIT SDA and SCL lines (standard mode I2C-bus) fSCL SCL clock frequency 0 − 100 kHz tBUF bus free time between a STOP and START condition 4.7 − − µs tHD;STA hold time (repeated) START condition 4.0 − − µs tLOW LOW period of the SCL clock 4.7 − − µs tHIGH HIGH period of the SCL clock 4.0 − − µs tSU;STA set-up time for a repeated START condition 4.7 − − µs tSU;STO set-up time for STOP condition 4.0 − − µs tHD;DAT data hold time 5.0 − 0.9 µs tSU;DAT data set-up time 250 − − ns tr rise time of both SDA and SCL signals − − 1000 ns tf fall time of both SDA and SCL signals − − 300 ns CL(bus) capacitive load for each bus line − − 400 pF Oscillator 1 (system clock) fosc oscillator frequency − 48 − MHz δ duty factor − 50 − % gm transconductance 12.8 22.1 30.2 mS Ro output resistance 0.6 1.1 2.3 kΩ Ci(XTAL1a) parasitic input capacitance XTAL1a 4.5 4.8 5.2 pF Ci(XTAL2a) parasitic input capacitance XTAL2a 4.1 4.6 5.0 pF Istart start-up current 3.7 7.6 13.0 mA Oscillator 2 (for ADC clock) fosc oscillator frequency 8.192 − 14.08 MHz δ duty cycle − 50 − % gm transconductance 8.1 13.6 18.1 mA/V Ro output resistance 1.3 2.0 4.0 kΩ Ci(XTAL1b) parasitic input capacitance XTAL1b 5.0 5.4 5.7 pF Ci(XTAL2b) parasitic input capacitance XTAL2b 4.1 4.6 5.0 pF Istart start-up current 2.4 5.0 8.4 mA 1998 Aug 28 35 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) SYMBOL PARAMETER UDA1335H CONDITIONS MIN. TYP. MAX. UNIT Analog PLL (for ADC clock) fclk(PLL) PLL clock frequency 8.1920 11.2896 12.2880 δ duty factor − 50 − % MHz tstrt(PO) start-up time after power-on − − 10 ms Power-on reset tsu(PO) power-on set-up-time note 1 5Cref(2) − − ms full-scale input voltage (RMS value) PGA gain = −3 dB − 1414(5) − mV PGA gain = 0 dB − 1000 − mV PGA gain = 3 dB − 708 − mV PGA gain = 9 dB − 355 − mV PGA gain = 15 dB − 178 − mV PGA gain = 21 dB − 89 − mV PGA gain = 27 dB − 44 − mV − − 20 pF PGA and ADC Vi(FS)(rms) Ci(PGA) input capacitance of the PGA (THD + N)/S total harmonic distortion plus noise-to-signal ratio fs = 44.1 kHz at input signal of 1 kHz; PGA gain = 0 dB; note 3 Vi (0 dB) (1.0 V RMS) − Vi (−60 dB) −85 −80 dB − 0.0056 0.01 % − −30 −20 dB − 3.2 10.0 % S/N signal to noise ratio Vi = 0.0 V 90 95 − dBA αct crosstalk between channels PGA gain = 0 dB − 100 − dB fs sample frequency (128fs) 0.640 − 7.04 MHz OL(FS) full-scale digital output level − −2.0 − dB 1998 Aug 28 PGA gain = 0 dB; Vi = 1 V (RMS) 36 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) SYMBOL PARAMETER UDA1335H CONDITIONS MIN. TYP. MAX. UNIT Filter stream DAC 16 − − bits − 0.66 − V supply voltage ripple rejection at fripple = 1 kHz; VDDA and VDDO Vripple(p-p) = 0.1 V − 60 − dB RES resolution Vo(FS)(rms) full-scale output voltage (RMS value) SVRR VDD = 3.3 V ∆Vo channel unbalance maximum volume − 0.03 − dB αct crosstalk between channels RL = 5 kΩ − 95 − dB (THD + N)/S total harmonic distortion plus noise-to-signal ratio fs = 44.1 kHz; RL = 5 kΩ; note 4 at input signal of 1 kHz (0 dB) − −90 −80 dB − 0.0032 0.01 % at input signal of 1 kHz (−60 dB) − −30 −20 dB − 3.2 10 % A-weighting at code 0000H 90 95 − dB S/N signal-to-noise ratio at bipolar zero Notes 1. Strongly depends on the external decoupling capacitor connected to Vref(DA). 2. Cref in µF. 3. Measured with the APLL as ADC clock source. 4. Measured with I2S-bus input as digital source. 5. Although a level of 1.414 V (RMS) would be required to optimal drive the ADC in this gain setting, this level can not be used. Due to the 3.3 V supply voltage input, signals of 1.17 V (RMS) and higher will result in clipping. APPLICATION INFORMATION The UDA1335H can only be used in combination with an external (E)PROM. This (E)PROM can be connected to the port pins (P0 and P2) of the UDA1335H and must contain the firmware for the microcontroller. The UDA1335H will be delivered with standard USB compliant firmware. The I2C-bus EEPROM is optional and can be used to configure client specific configurations and descriptors. More information about the firmware, descriptors and configurations can be obtained from several application notes. 1998 Aug 28 37 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) UDA1335H +VA handbook, full pagewidth +VA R35 1Ω C34 47 µF (16 V) C38 GP0/BCKI BCKI GP5/WSI WSI GP1/DI DI BCK BCK digital input recording WS WS DA DA 47 µF (16 V) C21 100 nF (63 V) 100 nF (63 V) VSSA1 VDDA1 VSSA2 39 digital input playback R27 1Ω C32 38 44 VDDA2 42 17 15 13 61 59 57 +VC L1 X4 1 2 3 4 R48 1.5 kΩ VUSB 1 2 3 4 8 R7 7 6 5 R16 C16 10 nF (50 V) C15 D− 22 Ω C18 22 pF (63 V) 10 nF (50 V) C8 analog input recording D+ 22 Ω C17 22 pF (63 V) VINR 6 UDA1335H 8 47 47 µF (16 V) C22 VINL 43 47 µF (16 V) C44 L5 10 nF (63 V) 1.5 µH 1 XTAL2b 26 C38 12 pF (63 V) X1 48 MHz C37 XTAL1b 25 4.7 pF (50 V) XTAL2a ADC XTAL XTAL1a C5 18 pF (50 V) VA(ext) VD(ext) L8 +VA BLM32A07 L7 +VC BLM32A07 L6 BLM32A07 +VD C47 100 µF (16 V) C46 100 µF (16 V) 53 54 C6 18 pF (50 V) C45 100 µF (16 V) 10 9 VSSI C25 100 nF (63 V) C24 100 nF (63 V) GND MBK839 11 VDDI 38 VDDE C26 L2 BLM32A07 R17 1Ω +VC Fig.10 Application diagram (continued in Fig.11). 1998 Aug 28 12 VSSE 100 nF (63 V) C27 100 nF (63 V) L3 BLM32A07 R25 1Ω +VD Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) +VA handbook, full pagewidth +VA R10 1Ω C7 55 R8 1Ω C11 47 µF (16 V) C19 100 nF (63 V) VSSA3 UDA1335H 100 nF (63 V) VDDA3 VRN 52 49 VRP 51 56 58 60 62 64 3 5 7 50 P0.0 D7 P0.1 D6 P0.2 D5 P0.3 D4 P0.4 D3 P0.5 D2 P0.6 D1 D0 P0.7 LE ALE OE 18 19 17 16 14 15 13 12 D1 74HCT373D 8 7 9 6 4 5 3 2 20 11 1 10 14 16 18 20 22 23 31 48 41 A4 Q2 A5 Q1 A6 Q0 A7 VCC A8 C24 GND 100 nF (50 V) A10 A11 OE P2.3 CE P2.4 PGM P2.5 VPP PSEN A0 C36 100 nF (63 V) 1 A1 2 A2 3 8 D4 PCF85116-3 4 7 6 5 VDD PTC 1 63 36 35 4 33 32 VSSO VDDO C33 VSSX C28 100 nF (63 V) 100 nF (63 V) C39 C18 47 µF (16 V) R43 1Ω +VA 100 nF (63 V) SDA R38 10 kΩ 15 6 16 5 17 4 18 3 19 2 Vref(AD) C31 47 µF (16 V) C29 100 nF (63 V) C41 47 µF (16 V) C35 VOUTR C48 VOUTL GP4/BCKO GP3/WSO GP2/DO BCKO WSO DO analog output playback digital output playback RTCB TC SHTCB L13 BLM32A07 R26 1Ω MBK840 39 O1 O2 O3 O4 O5 O6 O7 21 23 2 28 26 22 20 27 1 (I2C-bus) SCL Vref(DA) O0 25 R39 10 kΩ Fig.11 Application diagram (continued from Fig.10). 1998 Aug 28 7 1 SDA VDDX +VC 13 +VD 28 24 8 SCL 47 µF (16 V) 2 12 4.7 kΩ R20 1Ω 11 9 +VD R28 EA 10 D2 A9 24 EEPM27128 +VD P2.2 47 µF (16 V) 34 A3 Q3 A13 C28 100 nF (63 V) 37 A2 Q4 P2.1 VSS 40 A1 Q5 A12 UDA1335H 21 A0 Q6 P2.0 +VD 19 Q7 14 VCC C25 GND +VD 100 nF (50 V) Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) UDA1335H PACKAGE OUTLINE QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT319-2 c y X 51 A 33 52 32 ZE e E HE A A2 (A 3) A1 θ wM pin 1 index Lp bp L 20 64 detail X 19 1 ZD w M bp e v M A D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 3.20 0.25 0.05 2.90 2.65 0.25 0.50 0.35 0.25 0.14 20.1 19.9 14.1 13.9 1 24.2 23.6 18.2 17.6 1.95 1.0 0.6 0.2 0.2 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ o 7 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 95-02-04 97-08-01 SOT319-2 1998 Aug 28 EUROPEAN PROJECTION 40 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (order code 9398 652 90011). Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm. 1998 Aug 28 UDA1335H 41 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) UDA1335H DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1998 Aug 28 42 Philips Semiconductors Preliminary specification Universal Serial Bus (USB) Audio Playback Recording Peripheral (APRP) NOTES 1998 Aug 28 43 UDA1335H Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1998 SCA60 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545102/750/01/pp44 Date of release: 1998 Aug 28 Document order number: 9397 750 03922