INTEGRATED CIRCUITS DATA SHEET SAA7367 Bitstream conversion ADC for digital audio systems Product specification Supersedes data of 1996 Jun 17 File under Integrated Circuits, IC01 1998 Nov 17 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SAA7367 FEATURES • Total Harmonic Distortion plus Noise (THD + N) = −88 dB (0.004%); DR = 93 dB; S/N = 97 dB • Simple interfacing to analog inputs • Small, non-critical PCB layout • Low pin-out SO24 package (pin-compatible to SAA7366) • 4 flexible serial interface modes GENERAL DESCRIPTION • 4.5 to 5.5 V operation The SAA7367 is a CMOS low-cost stereo Analog-to-Digital Converter (ADC) using the Philips bitstream conversion technique. • Standby mode • Detection of digital signal ≥−1 dB amplitude • Up to 18 significant bits serial output • Selectable high-pass filter. APPLICATIONS The device is designed for the digital acquisition of analog audio signals for digital audio systems such as: • Compact Disc-Recordable (CD-R) • Audio digital signal processing systems for hi-fi and musical instrument applications • Digital Audio Tape (DAT). QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDDD digital supply voltage 4.5 5.0 5.5 V IDDD digital supply current − 17 − mA VDDA analog supply voltage 4.5 5.0 5.5 V IDDA analog supply current − 13 − mA fBCK clock input frequency 4.60 12.288 12.8 MHz fs sample rate 18 48 50 kHz THD + N total harmonic distortion plus noise at 0 dB input − −88 −80 dB DR dynamic range at −60 dB S/N signal-to-noise ratio 90 93 − dB − 97 − dB ORDERING INFORMATION TYPE NUMBER SAA7367 1998 Nov 17 PACKAGE NAME SO24 DESCRIPTION plastic small outline package; 24 leads; body width 7.5 mm 2 VERSION SOT137-1 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SAA7367 BLOCK DIAGRAM VSSA handbook, full pagewidth VrefR 13 15 operational amplifier BIR BOR VDACP Iref VDACN TESTB STDB 12 2 operational amplifier REFERENCE VOLTAGE GENERATOR 16 17 CLOCK GENERATION AND CONTROL 4 5 19 14 SIGMADELTA MODULATOR REFERENCE CURRENT GENERATOR 6 VDDD VSSD DECIMATION FILTER TIMING GENERATOR STAGE 2 STAGE 1 3 HALF-BAND COMB FILTERS FILTER SIGMADELTA MODULATOR 18 CKIN SAA7367 HIGH-PASS FILTER BOL BIL 20 3 21 operational amplifier REFERENCE VOLTAGE GENERATOR 22 VrefL Fig.1 Block diagram. 1998 Nov 17 SERIAL OUTPUT INTERFACE operational amplifier 23 VDDA 7 3 11 10 HPEN TEST1 24 SLAVE 8 9 OVLD SDO SWS SCK 1 SFOR MGE645 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SAA7367 PINNING SYMBOL SFOR PIN 1 DESCRIPTION TTL level input; in normal mode this input selects the serial interface output format; output format is selected as follows: SFOR = HIGH selects Format 1 SFOR = LOW selects Format 2 (similar to I2S) STDB 2 schmitt-trigger input; in normal mode, this input is used to select standby mode: STDB = HIGH selects normal operation STDB = LOW selects standby mode (low power consumption) OVLD 3 TTL level output; in normal mode this output indicates whether the internal digital signal is within 1 dB of maximum; if so, the output will go HIGH for 131072 clock cycles (approximately 11 ms); in standby mode this output is forced LOW CKIN 4 CMOS level input; system clock input; nominally clocked at 256fs VDDD 5 digital supply voltage (4.5 to 5.5 V) VSSD 6 digital ground SDO 7 TTL level output (3-state); in normal mode this pin outputs data from the serial interface; in standby mode, this output is high impedance SWS 8 TTL level input/output; serial interface word select signal; in master mode (SLAVE = LOW), this pin outputs the serial interface word select signal; in slave mode (SLAVE = HIGH), this pin is the word select input to the serial interface; in standby mode (STDB = LOW) this pin is always an input (high impedance); for polarity: see Table 1 SCK 9 TTL level input/output; in master mode (SLAVE = LOW) the pin outputs the serial interface bit clock; in slave mode (SLAVE = HIGH) this pin is the input for the external bit clock; data on SDO is clocked out on the HIGH-to-LOW transition of SCK; the data is valid on the LOW-to-HIGH transition TEST1 10 Test 1; TTL level input with internal pull-down; in slave mode (slave = HIGH), this pin is used to select extra serial interface formats (see Table 2) HPEN 11 TTL level input; this input is used to enable the internal high-pass filter when HIGH; in scan-test mode (TESTB = LOW and TEST1 = LOW) this pin functions as ‘scan chain c’ input TESTB 12 Test B; CMOS level input with internal pull-up; in normal applications, this input should be left HIGH VSSA 13 analog ground; this pin is internally connected to VSS via the on-chip substrate contacts Iref 14 current reference generator output; 33 kΩ in parallel with 22 nF is connected from this pin to VSSA VrefR 15 right channel analog reference output voltage (1⁄2VDDA) BIR 16 buffer operational amplifier inverting input for right channel BOR 17 buffer operational amplifier output for right channel VDACN 18 negative 1-bit DAC reference voltage input, connected to 0 V VDACP 19 positive 1-bit DAC reference voltage input, connected to +5 V BOL 20 buffer operational amplifier output for left channel BIL 21 buffer operational amplifier inverting input for left channel VrefL 22 left channel analog reference output voltage (1⁄2VDDA) VDDA 23 analog supply voltage (4.5 to 5.5 V) 1998 Nov 17 4 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SYMBOL SLAVE SAA7367 PIN 24 DESCRIPTION TTL level input; used to select the serial interface operating mode: SLAVE = HIGH selects slave mode SLAVE = LOW selects master mode Table 1 SWS polarity CONDITIONS POLARITY SLAVE AND TEST1 SLAVE = LOW or TEST1 = LOW SLAVE = HIGH and TEST1 = HIGH Table 2 SWS SFOR LOW LOW left data LOW HIGH right data LOW LOW right data LOW HIGH left data Selection of serial interface formats via TEST1 CONDITIONS SELECTED FORMAT SFOR TEST1 HIGH LOW LOW format 1 HIGH format 3 LOW format 2 HIGH format 4 FUNCTIONAL DESCRIPTION General handbook, halfpage SFOR 1 24 SLAVE STDB 2 23 VDDA OVLD 3 22 VrefL CKIN 4 21 BIL VDDD 5 20 BOL VSSD 6 SDO 7 18 VDACN SWS 8 17 BOR SCK 9 16 BIR SAA7367 The SAA7367 is a bitstream conversion CMOS ADC for digital audio systems. The conversion is achieved using a third-order Sigma-Delta Modulator (SDM), running at 128 times the output sample frequency (fs). The high oversampling ratio greatly simplifies the design of the analog input anti-alias filter. In most events, the internal buffer operational amplifier, configured as a low-pass filter, will suffice. The 1-bit code from the SDM is filtered and down-sampled (decimated) to 1fs by Finite Impulse Response (FIR) filters. An optional I2R high-pass filter is provided to remove DC, if required. The device has been designed with ease of use, low board area and low application costs in mind. 19 VDACP TEST1 10 15 VrefR HPEN 11 14 Iref Clock frequency TESTB 12 13 VSSA The external clock input on pin CKIN runs at 256fs, which can range from 18 to 50 kHz. MGE644 Fig.2 Pin configuration. 1998 Nov 17 5 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SAA7367 Input signals in the range 0 to 1 dB may or may not be clipped, depending on the values of DC dither and small random offsets in the analog circuitry. Input buffer Two input buffers are provided, one for each channel, for signal amplitude matching, signal buffering and anti-alias filter purposes. These are configured for inverting use. Access is provided by pins BIL, BIR (inverting inputs) and BOL, BOR (outputs), for left and right channels respectively. By the choice of feedback component values, the application signal amplitude can be matched to the requirements of the ADC. When using the recommended application circuitry, clipping will initially be observed on negative peaks, due to the use of negative DC dither. The maximum level of overload that can be safely tolerated is application circuit dependent. In the case of the recommended circuit, the following applies: the inverting operational amplifier inputs BIL and BIR are protected from excessive voltages (currents) by diodes to VDDA and VSSA. These have absolute maximum ratings of Id = ±20 mA, with a safe practical limit of ±2 mA. Typically, the operational amplifiers are configured as low-pass filters with a gain of 1 and a pole at approximately 5fs. Remark: the complete ADC is non-inverting. Hence, a positive DC input (referenced to Vref) will yield a positive digital output. Given the input resistor of 10 kΩ, ±2 mA diode current and the operation of the operational amplifier, a maximum signal (applied to the input resistor) of ±30 V can be handled safely. This level represents an overload of 26 dB. Input level During overload, the in-band portion of the waveform will be correctly converted. The out-of-band portion will be limited as previously detailed. The overall system gain is proportional VDDA, or more accurately the potential difference between the DAC reference voltages (VVDACP) and (VVDACN). For convenience, the ADC input signal amplitude is defined as that amplitude seen on BOL or BOR, the operational amplifier outputs (i.e. the input to the SDM). Also, the 0 dB input level is defined as that which gives a −1 dB (actually −1.12 dB) digital output, relative to full-scale swing. This reduced gain provides headroom to accommodate small random DC offsets, without causing the digital output to clip. Sigma-Delta Modulator (SDM) The SAA7367 uses two third-order SDMs with a quantization noise floor of approximately −104 dB. The scaling of the feedback has been optimized for stable operation, even during overload. Thus, with a maximum signal swing of 0 V to VDDA on the input, the digital output remains well-behaved, i.e. it does not burst into random oscillation. During overload, the output is simply a clipped version of the input. The gain of this stage is −4.64 dB. Hence: ( V VDACP – V VDACN ) V I ( 0 dB ) = -----------------------------------------------------5 V (RMS) Decimation filter Decimation from 128fs is performed in two stages. The first stage, a comb filter, uses 64 symmetrical coefficients to implement a 3rd sin x⁄x characteristic. This filter decimates from 128 to 8fs. The second stage, an FIR filter, consists of three half-band filters, each decimating by a factor of 2. The overall characteristics are given in Table 3. The user of the IC should ensure that, when all sources of signal amplitude variation are taken into account, the maximum input signal should conform to the 0 dB level. In the event that the maximum signal level cannot be pre-determined, e.g. live microphone input, the average signal level should be set at −10 to −20 dB down. The exact value will depend on the application and the balance between headroom and operating Signal-to-Noise Ratio (SNR). Behaviour during overload As previously defined, the maximum input level for normal operation is 0 dB. If the input level exceeds this value, clipping may occur. Within the system, excessive amplitudes are detected after the high-pass filter. Infringements are limited to the maximum permitted positive or negative values 217 − 1 or −217 respectively. 1998 Nov 17 6 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems Table 3 SAA7367 Overall filter characteristics ITEM Pass band ripple Stop band CONDITION Standby mode The STDB pin activates a power saving mode when the device function is not required. This pin can also be used as a chip enable. VALUE (dB) 0 to 0.45fs ±0.1 0.45 to 0.47fs −0.5 >0.55fs −60 Dynamic range 0 to 0.42fs 110 Gain DC 3.52 On a HIGH-to-LOW transition of the STDB pin, the internal control circuitry starts a timed power-down sequence. This takes approximately 32 system clock cycles to complete. Transitions on STDB that are shorter than 32 clock cycles may have an indeterminate effect. However, the device will always recover correctly. High-pass filter An optional I2R high-pass filter is provided to remove unwanted DC components. The operation is selected when HPEN is HIGH and deselected when LOW. The filter has the characteristics given in Table 4. During standby, the following occurs: Table 4 • The analog circuitry is disabled • The internal logic clock is disabled • The serial interface pins are forced to high impedance • The OVLD output is forced LOW High-pass filter characteristics ITEM CONDITION Pass band ripple none Pass band gain 0 Droop at 0.00042fs • The nominal external analog node voltages are maintained by a low-power circuit. This feature ensures a fast recovery from standby mode. VALUE (dB) Note: since the serial interface pins are high impedance during standby, these pins could be wire-ORed with other serial interface ICs. 0.146 Attenuation at DC at 0.00000036fs >40 Dynamic range 0 to 0.45fs >110 On a LOW-to-HIGH transition, the device reverts back to normal operation. This process takes approximately 256 system clock cycles. Before SDO is enabled, the output data is forced LOW. SDO remains LOW until good data is available from the decimation filter (see Section “Serial interface”). Serial interface The serial interface provides 2 formats in master mode and 4 in slave mode (see Figs 3 and 4). Format 2 is similar to Philips I2S. In all modes, the interface provides up to 18 significant bits of output data per channel. During standby mode (STDB = LOW), all interface pins are in their high impedance state. On recovery from standby, the serial data output SDO is held LOW until valid data is available from the decimation filter. This time depends on whether the high-pass filter is selected: The STDB pin has a Schmitt-trigger input. A simple power-on-reset function can be effected using an external capacitor to VSS and resistor to VDD. TEST1 This pin is used to select the serial interface format in slave mode. HPEN = 0; T = 1024/fs, T = 21.3 ms when fs = 48 kHz HPEN = 1; T = 12288/fs, T = 256.0 ms when fs = 48 kHz Overload detection The OVLD output is used to indicate when the output data, in either the left or right channel, is greater than −1 dB (actual figure −1.023 dB) of the maximum possible digital swing. When this condition is detected, the OVLD output is forced HIGH for at least 512fs cycles (10.6 ms at fs = 48 kHz). This time-out is reset for each infringement. 1998 Nov 17 7 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SAA7367 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VDDA analog supply voltage (note 1) −0.5 +6.5 V VI DC input voltage −0.5 +6.5 V IIK DC input clamp diode current − ±20 mA VO DC output voltage −0.5 VDD + 0.5 V IO DC output source or sink current − ±20 mA IDD(tot) total DC supply current − ±0.5 A ISStot total DC supply current − ±0.5 A Tamb operating ambient temperature −40 +85 °C Tstg storage temperature −65 +150 °C Note 1. VSSD and VSSA must be connected to a common potential. QUALITY SPECIFICATION In accordance with “SNW-FQ-611-E”. The number of the quality specification can be found in the “Quality Reference Handbook”. CHARACTERISTICS VDDD = 4.5 to 5.5 V; VDDA = 4.5 to 5.5 V; fs = 18 to 50 kHz; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDD digital supply voltage IDDD digital supply current fs = 48 kHz 4.5 5 5.5 V − 17 − mA VDDA analog supply voltage 4.5 5 5.5 V IDDA analog supply current − 13 − mA Ptot total power dissipation − 150 − mW Istb standby supply current − 160 − µA Pstb standby power consumption − 800 − µW fs = 48 kHz Digital part: inputs SFOR, SLAVE AND HPEN VIL LOW level input voltage −0.5 − +0.8 V VIH HIGH level input voltage 2.0 − VDD + 0.5 V ILI input leakage current −10 − +10 µA Ci input capacitance − − 10 pF 1998 Nov 17 8 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SYMBOL PARAMETER SAA7367 CONDITIONS MIN. TYP. MAX. UNIT CKIN VIL LOW level input voltage −0.5 − 0.3VDD V VIH HIGH level input voltage 0.7VDD − VDD + 0.5 V ILI input leakage current −10 − +10 µA Ci input capacitance − − 10 pF VIL LOW level input voltage −0.5 − +0.8 V VIH HIGH level input voltage 2.0 − VDD + 0.5 V Ri internal resistance to VSS − 50 − kΩ Ci input capacitance − − 10 pF VIH HIGH level input voltage 0.7VDD − VDD + 0.5 V Ri internal resistance to VDD − 50 − kΩ − 0.4VDD V TEST1 TESTB STDB (SCHMITT TRIGGER) VIL LOW level input voltage −0.5 VIH HIGH level input voltage 0.6VDD − VDD + 0.5 V Vhys hysteresis voltage 200 − − mV ILI input leakage current −10 − +10 µA Ci input capacitance − − 10 pF − +0.8 V VDD + 0.5 V Digital part: inputs/outputs SWS AND SCK VIL LOW level input voltage −0.5 VIH HIGH level input voltage 2.0 ILl 3-state leakage current −10 − +10 µA Ci input capacitance − − 10 pF VOL LOW level output voltage IO = −400 µA − − 0.4 V VOH HIGH level output voltage IO = 20 µA 2.4 − − V CL output load capacitance note 1 − − 50 pF Digital part: outputs OVLD VOL LOW level output voltage IO = −400 µA − − 0.4 V VOH HIGH level output voltage IO = 20 µA 2.4 − − V CL output load capacitance note 1 − − 50 pF VOL LOW level output voltage IO = −400 µA − − 0.4 V VOH HIGH level output voltage IO = 20 µA ILI 3-state leakage current CL output load capacitance SDO 1998 Nov 17 note 1 9 2.4 − − V −10 − +10 µA − − 50 pF Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SYMBOL PARAMETER SAA7367 CONDITIONS MIN. TYP. MAX. UNIT Digital part: timings CKIN tr input rise time − − 10 ns tf input fall time − − 10 ns fi input frequency msr mark-to-space ratio 4.60 − 12.8 MHz fs > 32 kHz 40 − 60 % fs ≤ 32 kHz 30 − 70 % Serial Interface master and slave modes (see Figs 5 and 6) SCK tr rise time CL = 50 pF; note 1 − − 50 ns tf fall time CL = 50 pF; note 1 − − 50 ns tL LOW time T = 1⁄64fs 0.4T − 0.6T ns tH HIGH time T= 1⁄ 64fs 0.4T − 0.6T ns fclk clock frequency master mode 64fs 64fs 64fs MHz slave mode − − 64fs MHz burst clock idle time slave mode; T = 1/fs 0 − 0.5T ns tr rise time CL = 50 pF; note 1 − − 50 ns tf fall time CL = 50 pF; note 1 − − 50 ns tL LOW time T = 1/fs 0.05T 0.5T 0.95T ns tH HIGH time T = 1/fs 0.05T 0.5T 0.95T ns fS frequency 1fs 1fs 1fs MHz td delay from SCK master mode −50 − +50 ns slave mode 50 − slave mode 150 − − ns tidle SWS tsu set-up time to SCK ns SDO th data output hold time 100 − − ns tsu data output set-up time 50 − − ns tr data output rise time CL = 50 pF; note 1 − − 50 ns tf data output fall time CL = 50 pF; note 1 − − 50 ns 1998 Nov 17 10 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SYMBOL PARAMETER SAA7367 CONDITIONS MIN. TYP. MAX. UNIT 0.475VDDA 0.5VDDA 0.525VDDA V normal mode − 1.3 − kΩ standby mode − 100 − kΩ − 0.5VDDA − V − 76 − µA input voltage − VSS − V input voltage − VDDA − V − <10 − mV 10 − kΩ Analog part at: VDD = VDDA = 5 V; Tamb = 25 °C VrefL AND VrefR VO output voltage RDC DC impedance CURRENT REFERENCE: Iref VO out put voltage IO output current R = 33 kΩ VDACN VI VDACP VI BUFFER OPERATIONAL AMPLIFIERS: BIL, BOL, BIR AND BOR VI(off) input offset voltage RL load resistance; (drive capability) ZO output impedance THD + N total harmonic distortion plus noise decoupled to Vref − − 100 − Ω f = 0 to 20 kHz − −87 − dB OVERALL PERFORMANCE (ANALOG IN, DIGITAL OUT) tgd group delay time T = 1/fs − 25T − s αsb stop band attenuation f > 0.546 fs 60 − − dB DR dynamic range 0 to 20 kHz 90 93 − dB THD + N total harmonic distortion plus noise 0 to 20 kHz − −88 −80 dB S/N signal-to-noise ratio A-weighted − 97 − dB αcs channel separation − 92 − dB G gain −1.4 −1 −0.8 dB note 2 Notes 1. Load capacitance is valid for master mode only. 2. See also Section “Input level” of Chapter “Functional description”; valid for left or right channel. 1998 Nov 17 11 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SAA7367 1 STEREO WORD handbook, full pagewidth LEFT DATA FORMAT 2 FORMAT 1 RIGHT DATA RIGHT DATA LEFT DATA 14 CLOCKS 18 CLOCKS 18 CLOCKS 14 CLOCKS SCK SDO MSB LSB MSB LSB MSB MGE647 Fig.3 Serial interface master mode format. 1998 Nov 17 12 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SAA7367 1 STEREO WORD handbook, full pagewidth FORMAT 2 LEFT DATA RIGHT DATA FORMAT 4 LEFT DATA RIGHT DATA idle N CLOCKS N CLOCKS SCK MSB SDO LSB MSB LSB MSB 1 STEREO WORD FORMAT 1 RIGHT DATA LEFT DATA FORMAT 3 RIGHT DATA LEFT DATA idle N CLOCKS N CLOCKS SCK SDO MSB LSB MSB LSB MSB MGE648 Fig.4 Serial interface slave mode format. 1998 Nov 17 13 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems handbook, full pagewidth tf tr SAA7367 tL tH 2.0 V SCK 0.8 V td 2.0 V SWS 0.8 V tr tsu th tf 2.0 V SDO MSB FORMAT 2 MSB FORMAT 1 VALID 0.8 V MGE649 Fig.5 Serial interface master mode timing. handbook, full pagewidth tf tr tL tH 2.0 V SCK 0.8 V tsu td 2.0 V SWS 0.8 V tr tsu th tf 2.0 V SDO MSB FORMAT 1 VALID MSB FORMAT 2 0.8 V MGE650 Fig.6 Serial interface slave mode timing. 1998 Nov 17 14 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 100 kΩ 47 µF 47 nF +5 V +5 V 10 kΩ (1) 47 nF 270 Ω 270 Ω 47 µF 68 pF 24 VrefL VDDA 23 47 nF BIL 22 21 47 µF 33 kΩ 330 kΩ 10 kΩ SLAVE 47 nF Rdither 620 kΩ VDDD or VSSD (1) 10 kΩ Rdither 4.7 Ω 47 µF 47 µF (1) 10 kΩ (1) VDACP BOL 20 19 22 nF 68 pF VDACN 18 Philips Semiconductors 100 kΩ Bitstream conversion ADC for digital audio systems right channel input left channel input 47 µF APPLICATION INFORMATION 1998 Nov 17 handbook, full pagewidth BOR BIR VrefR Iref VSSA 15 17 16 15 14 13 8 9 10 11 12 SAA7367 1 2 SFOR 3 STDB 4 OVLD 5 CKIN 6 VDDD 7 VSSD SDO SWS SCK TEST1 HPEN TESTB VDDD or VSSD from microcontroller power-down control 47 nF (1) VDDD or VSSD MGE646 to microcontroller overload detection 47 µF system clock input 4.7 Ω to serial interface receiver circuit +5 V Product specification Fig.7 Application circuit. SAA7367 (1) These capacitors should preferably be surface-mounted components located as close as possible to the device pins. Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SAA7367 PACKAGE OUTLINE SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c HE y v M A Z 13 24 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.10 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.61 0.60 0.30 0.29 0.050 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT137-1 075E05 MS-013AD 1998 Nov 17 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-24 97-05-22 16 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SAA7367 • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. SOLDERING Introduction to soldering surface mount packages • For packages with leads on two sides and a pitch (e): This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: 1998 Nov 17 17 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SAA7367 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE HLQFP, HSQFP, HSOP, SMS not suitable(2) suitable PLCC(3), suitable suitable SO recommended(3)(4) LQFP, QFP, TQFP not SQFP not suitable SSOP, TSSOP, VSO not suitable suitable recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1998 Nov 17 18 Philips Semiconductors Product specification Bitstream conversion ADC for digital audio systems SAA7367 NOTES 1998 Nov 17 19 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545102/00/02/pp20 Date of release: 1998 Nov 17 Document order number: 9397 750 04775