INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT132 Quad 2-input NAND Schmitt trigger Product specification File under Integrated Circuits, IC06 September 1993 Philips Semiconductors Product specification Quad 2-input NAND Schmitt trigger 74HC/HCT132 FEATURES • Output capability: standard • ICC category: SSI GENERAL DESCRIPTION The 74HC/HCT132 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT132 contain four 2-input NAND gates which accept standard input signals. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. The gate switches at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT− is defined as the hysteresis voltage VH. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay nA, nB to nY CI input capacitance CPD power dissipation capacitance per gate CL = 15 pF; VCC = 5 V 11 notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. September 1993 2 HCT 17 ns 3.5 3.5 pF 24 20 pF Philips Semiconductors Product specification Quad 2-input NAND Schmitt trigger 74HC/HCT132 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 4, 9, 12 1A to 4A data inputs 2, 5, 10, 13 1B to 4B data inputs 3, 6, 8, 11 1Y to 4Y data outputs 7 GND ground (0 V) 14 VCC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. FUNCTION TABLE INPUTS OUTPUT nA nB nY L L H L H H H L H H H L Notes 1. H = HIGH voltage level L = LOW voltage level Fig.5 Fig.4 Functional diagram. Logic diagram (one Schmitt trigger). APPLICATIONS • Wave and pulse shapers • Astable multivibrators • Monostable multivibrators September 1993 3 Philips Semiconductors Product specification Quad 2-input NAND Schmitt trigger 74HC/HCT132 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Transfer characteristics are given below. Output capability: standard ICC category: SSI Transfer characteristics for 74HC Voltages are referenced to GND (ground = 0 V) Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. typ. VT+ VT− VH positive-going threshold −40 to +85 max. min. max. WAVEFORMS UNIT V CC (V) −40 to +125 min. max. 0.7 1.18 1.5 0.7 1.5 0.7 1.5 1.7 2.38 3.15 1.7 3.15 1.7 3.15 V 4.5 2.1 3.14 4.2 2.1 4.2 2.1 4.2 6.0 negative-going threshold 0.3 0.63 1.0 0.3 1.0 0.3 1.0 0.9 1.67 2.2 0.9 2.2 0.9 2.2 4.5 1.2 2.26 3.0 1.2 3.0 1.2 3.0 6.0 0.2 0.55 1.0 0.2 1.0 0.2 1.0 0.4 0.71 1.4 0.4 1.4 0.4 1.4 4.5 0.6 0.88 1.6 0.6 1.6 0.6 1.6 6.0 hysteresis (VT+ − VT−) V 2.0 V 2.0 2.0 Figs 6 and 7 Figs 6 and 7 Figs 6 and 7 AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. typ. tPHL/ tPLH tTHL/ tTLH propagation delay nA, nB to nY output transition time September 1993 max. −40 TO +85 −40 TO +125 min. max. min. UNIT VCC (V) WAVEFORMS 2.0 Fig.13 max. 36 125 155 190 13 25 31 38 ns 4.5 10 21 26 32 6.0 19 75 95 110 7 15 19 22 4.5 6 13 16 19 6.0 4 ns 2.0 Fig.13 Philips Semiconductors Product specification Quad 2-input NAND Schmitt trigger 74HC/HCT132 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Transfer characteristics are given below. Output capability: standard ICC category: SSI Notes to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT nA, nB 0.3 Transfer characteristics for 74HCT Voltages are referenced to GND (ground = 0 V) Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER VT+ VT− VH +25 positive-going threshold −40 to +85 min. typ. max. min. max. min. max. 1.2 1.41 1.9 1.2 1.9 1.2 1.9 1.4 1.59 2.1 1.4 2.1 1.4 2.1 negative-going threshold 0.5 0.85 1.2 0.5 1.2 0.5 1.2 0.6 0.99 1.4 0.6 1.4 0.6 1.4 0.4 0.56 − 0.4 − 0.4 − 0.4 0.60 − 0.4 − 0.4 − hysteresis (VT+ − VT−) WAVEFORMS UNIT V CC (V) −40 to +125 V 4.5 Figs 6 and 7 5.5 V 4.5 Figs 6 and 7 5.5 V 4.5 Figs 6 and 7 5.5 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. typ. −40 to +85 max. min. max. −40 to +125 min. UNIT VCC (V) WAVEFORMS max. tPHL/ tPLH propagation delay nA, nB to nY 20 33 41 50 ns 4.5 Fig.13 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.13 September 1993 5 Philips Semiconductors Product specification Quad 2-input NAND Schmitt trigger 74HC/HCT132 TRANSFER CHARACTERISTIC WAVEFORMS Fig.7 Waveforms showing the definition of VT+, VT− and VH; where VT+ and VT− are between limits of 20% and 70%. Fig.9 Typical HC transfer characteristics; VCC = 4.5 V. Fig.6 Transfer characteristic. Fig.8 Typical HC transfer characteristics; VCC = 2 V. Fig.10 Typical HC transfer characteristics; VCC = 6 V. September 1993 Fig.11 Typical HCT transfer characteristics; VCC = 4.5 V. 6 Philips Semiconductors Product specification Quad 2-input NAND Schmitt trigger 74HC/HCT132 Fig.12 Typical HCT transfer characteristics; VCC = 5.5 V. AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.13 Waveforms showing the input (nA, nB) to output (nY) propagation delays and the output transition times. September 1993 7 Philips Semiconductors Product specification Quad 2-input NAND Schmitt trigger 74HC/HCT132 Application information The slow input rise and fall times cause additional power dissipation, this can be calculated using the following formula: Pad = fi × (tr × ICCa + tf × ICCa) × VCC. Where: Pad fi tr tf ICCa = additional power dissipation (µW) = input frequency (MHz) = input rise time (ns); 10% − 90% = input fall time (ns); 10% − 90% = average additional supply current (µA) Average ICCa differs with positive or negative input transitions, as shown in Figs 14 and 15. Fig.14 Average ICC for HC Schmitt trigger devices; linear change of Vi between 0.1 VCC to 0.9 VCC. Fig.15 Average ICC for HCT Schmitt trigger devices; linear change of Vi between 0.1 VCC to 0.9 VCC. HC/HCT132 used in a relaxation oscillator circuit, see Fig.16. HC: HCT: 1 1 f = --- ≈ ----------------T 0.8RC 1 1 f = --- ≈ ---------------------T 0.67 RC Fig.16 Relaxation oscillator using HC/HCT132. Note to Application information All values given are typical unless otherwise specified. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. September 1993 8