INTEGRATED CIRCUITS DATA SHEET TDA9829T Downconverter for DVB Product specification File under Integrated Circuits, IC02 1998 Nov 09 Philips Semiconductors Product specification Downconverter for DVB TDA9829T FEATURES GENERAL DESCRIPTION • 5 V supply voltage The TDA9829T is an integrated circuit for DVB-IF processing. • Gain controlled IF-amplifier • Mixer for DVB-IF downconversion • VCO for Quadrature Amplitude Modulation (QAM) carrier recovery • External VCO control • Internal and external AGC • DVB output level adjust via AGC adjust • High level DVB operational output amplifier • Mute switch for DVB output • Tuner AGC with adjustable takeover point (TOP) • AFC detector without extra reference circuit • Stabilizer circuit for ripple rejection and to achieve constant output signals. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VP supply voltage IP supply current 81 96 111 mA V3-4(rms) input sensitivity (RMS value) −1 dB DVB signal at output − 100 150 µV ∆ϕSSB VCO phase noise f = 100 kHz; free-running 103 107 − dBc/Hz αmute mute attenuation note 2 − 36 − dB I12(sink) sink current maximum tuner gain reduction; see Fig.3 1.5 2 2.6 mA CRstps(US) control steepness ∆I14/∆fIF for USA fIF = 43.75 MHz; notes 3 and 4; see Fig.4 0.7 0.98 1.3 µA/kHz V11(p-p) output voltage (peak-to-peak value) CL < 15 pF; RL > 5 kΩ; with internal AGC 1.8 2.1 2.4 V B−1dB −1 dB bandwidth CL < 15 pF; RL > 5 kΩ 11 12 − MHz αH suppression of in-band harmonics Vo = 2.0 V (p-p) 30 35 − dB PSRR power supply ripple rejection at pin 11 26 36 − dB note 1 4.5 see Fig.5 5.0 5.5 V Notes 1. Performance may be decreased at VP = 4.5 V. 2. This parameter is not tested during production and is only given as application information for designing the television receiver. 3. To match the AFC output signal to different tuning systems a current source output is provided. The test circuit is given in Fig.4. The AFC-steepness can be changed by the resistors at pin 14. 4. Depending on the ratio ∆C/C0 of the LC resonant circuit of VCO (Q0 > 50; C0 = Cint + Cext; see Table 2). 1998 Nov 09 2 Philips Semiconductors Product specification Downconverter for DVB TDA9829T ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA9829T SO20 DESCRIPTION VERSION plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 BLOCK DIAGRAM DVB AGC adjust handbook, full pagewidth tuner AGC TADJ TAGC CAGC AGCADJ VAGC AFC VCO2 VCO1 VVCO 5 12 18 9 14 16 15 10 TUNER AGC ViIF1 DVB DVB external VCO control 2 × fPC CAGC TOP DVB-IF input DVB AGC external 8 AFC DETECTOR DVB AGC VCO TWD 3 11 DVB MIXER 4 ViIF2 IF filter INTERNAL VOLTAGE STABILIZER LOGIC TDA9829T 19 17 1 VP GND VSID +5 V 20 6 n.c. AGCSWI MUTESWI Fig.1 Block diagram. 1998 Nov 09 2, 7, 13 3 MHB219 VoDVB 2 V (p-p) Philips Semiconductors Product specification Downconverter for DVB TDA9829T PINNING SYMBOL PIN DESCRIPTION VSID 1 SIF down input n.c. 2 not connected ViIF1 3 IF differential input signal voltage 1 ViIF2 4 IF differential input signal voltage 2 TADJ 5 tuner AGC takeover adjust (TOP) AGCSWI 6 AGC switch input n.c. 7 not connected VAGC 8 AGC voltage input AGCADJ 9 AGC adjust input VVCO 10 VCO control voltage VoDVB 11 DVB output TAGC 12 tuner AGC output n.c. 13 not connected AFC 14 AFC output VCO1 15 VCO1 reference circuit VCO2 16 VCO2 reference circuit GND 17 ground CAGC 18 AGC capacitor VP 19 supply voltage (+5 V) MUTESWI 20 mute switch input 1998 Nov 09 handbook, halfpage VSID 1 20 MUTESWI 19 VP n.c. 2 ViIF1 3 18 CAGC ViIF2 4 17 GND 16 VCO2 TADJ 5 TDA9829T 15 VCO1 AGCSWI 6 14 AFC n.c. 7 VAGC 8 13 n.c. 12 TAGC AGCADJ 9 VVCO 10 11 VoDVB MHB220 Fig.2 Pin configuration. 4 Philips Semiconductors Product specification Downconverter for DVB TDA9829T A peak detector is used for the DVB AGC. The peak value of (digital) the QAM signal is detected and controlled to a constant value by the variable gain IF amplifier. The detector bandwidth is adapted to the symbol frequency (3 to 11 MHz). The external AGC time constant is given by the IF AGC capacitor at pin 18. FUNCTIONAL DESCRIPTION Vision IF amplifier The vision IF amplifier consists of three AC-coupled differential amplifier stages. Each differential stage comprises a feedback network controlled by emitter degeneration to control the IF gain. The AGC capacitor voltage is transferred to an internal IF control signal, and is fed to the tuner AGC to generate the tuner AGC output current (open-collector output). The tuner AGC takeover point can be adjusted. This allows the tuner and the SWIF filter to be matched to achieve the optimum IF input level. VCO, Travelling Wave Divider (TWD) and AFC The VCO operates with a resonance circuit (with L and C in parallel) at double the IF frequency plus symbol frequency. The VCO is controlled by integrated variable capacitors. The control voltage required to tune the VCO from its free-running frequency to its actual frequency is fed to the capacitors. This control voltage is amplified and converted into a current which represents the AFC output signal. At centre frequency the AFC output current is equal to zero. The DVB output signal (VoDVB) can be adjusted in a range of ±3 dB by a control voltage (∆Vadj) at pin 9. The internal AGC can be switched off at pin 6 and the IF gain can be controlled by an external voltage at pin 8. The tuner AGC is active in both instances. DVB output amplifier The oscillator signal is divided-by-two with a TWD which generates a differential output signal for downconverting the IF signal. The output amplifier for the DVB signal has a high bandwidth and delivers a 2 V (p-p) signal. The amplifier can be switched to a mute state forced by the signal at pin 20. DVB mixer The gain controlled DVB-IF signal is downconverted to the symbol frequency by use of a four quadrant multiplier. The conversion signal is provided by the VCO and TWD. Internal voltage stabilizer A band gap circuit internally generates a voltage of approximately 1.25 V, independent of supply voltage and temperature. A voltage regulator circuit, connected to this voltage, produces a constant voltage of 3.6 V which is used as an internal reference voltage. DVB AGC and tuner AGC The AGC detector charges/discharges the AGC capacitor to the required voltage for setting the IF and tuner gain in order to keep the DVB signal at a constant level. LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT maximum chip temperature of 125 °C 0 5.5 V voltage at pins 1 to 10, 13, 14 and 18 to 20 0 VP V VP supply voltage (pin 19) Vn tsc(max) maximum short-circuit time − 10 s V12 tuner AGC output voltage 0 13.2 V Tstg storage temperature −25 +150 °C Tamb operating ambient temperature −20 +70 °C Ves electrostatic handling voltage −300 +300 V 1998 Nov 09 machine model class B 5 Philips Semiconductors Product specification Downconverter for DVB TDA9829T THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS VALUE UNIT 85 K/W in free air CHARACTERISTICS VP = 5 V; Tamb = 25 °C; see Table 1 for input frequencies; input level ViIF(3−4) = 10 mV (RMS value); measurements taken in Fig.8; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply (pin 19) VP supply voltage IP supply current note 1 4.5 5.0 5.5 V 81 96 111 mA IF amplifier (measured at fIF = 43.75 MHz; pins 3 and 4) ∆V(3-4)(rms) input sensitivity (RMS value) −1 dB DVB signal at output − 100 150 µV Vi(3-4)(rms) maximum input signal level (RMS value) 1 dB DVB signal at output 140 200 − mV ∆GIF total gain control IF amplifier 59 64 − dB tilt for ∆f ±3 MHz fs = 6.9 MHz; 40 dB gain − 0.5 1 dB Ri(3-4)(diff) input resistance (differential) note 2 − 2.2 − kΩ Ci(3-4)(diff) input capacitance (differential) note 2 − 1.7 − pF DVB mixer and VCO (pins 10, 15 and 16); see notes 4 and 5 and Table 1 fVCO(max) maximum oscillator frequency 2(fIF + fs) 125 130 − MHz fVCO(US) VCO frequency for USA 2(fIF + fs) − 97.5 − MHz fVCO(EU) VCO frequency for Europe 2(fIF + fs) − 86.0 − MHz Vref(rms) oscillator voltage swing between pins 15 and 16 (RMS value) − 60 − mV ∆ϕSSB VCO phase noise f = 100 kHz; free-running 103 107 − dBc/Hz VVCO VCO control range (pin 10) see Figs 6 and 7 0 − VP V Ri(VCO) VCO control input resistance (pin 10) 50 63 76 kΩ CRstps(VCO) control steepness ∆fs/∆V10 DVB (USA) − 0.29 − MHz/V DVB (Europe) − 0.40 − MHz/V see Figs 6 and 7 DVB output amplifier (pins 11 and 20) Vo(DVB)(p-p) DVB output signal (QAM) (peak-to-peak value) 1.8 2.1 2.4 V Ibias(int) DC internal bias current for emitter-follower (pin 11) 1.9 2.3 2.7 mA Isink(max) maximum AC and DC output sink current (pin 11) 1.5 − − mA Isource(max) maximum AC and DC output source current (pin 11) 2.0 − − mA 1998 Nov 09 6 Philips Semiconductors Product specification Downconverter for DVB SYMBOL TDA9829T PARAMETER CONDITIONS MIN. TYP. MAX. UNIT αmute mute attenuation note 2 − 36 − dB Vi(mute) mute switch input voltage (pin 20) DVB mute; note 3 1.3 − VP V DVB no mute 0 − 0.8 V LOW-level input current (pin 20) V20 = 0 V 180 230 280 µA response to an increasing amplitude step in the IF input signal note 6 − 0.25 − ms/dB response to a decreasing amplitude step in the IF input signal note 6 − 0.25 − ms/dB IIL DVB AGC detector (pins 8, 9 and 18) tresp Ich charging current (pin 18) − 200 − µA Idch discharging current (pin 18) − 200 − µA ∆Vi(AGC) AGC adjust input voltage range (pin 9) 1 2.5 4.5 V ∆Ri(AGC) AGC adjust input resistance (pin 9) 8 10 12 kΩ ∆AGCstps AGC adjust steepness 2 V < V9 < 3 V − −5 − dB/V VAGC(ext) external AGC voltage for DVB (pin 8) see Fig.3 1 − 4.5 V Ri(AGC)(ext) external AGC input resistance (pin 8) 40 − − kΩ Tuner AGC (pin 12) Vi(min)(rms) IF input signal voltage for minimum starting point of tuner takeover (RMS value) input at pins 3 and 4; RTOP = 22 kΩ; ITAGC = 0.4 mA − 2 5 mV Vi(max)(rms) IF input signal voltage for maximum starting point of tuner takeover (RMS value) input at pins 3 and 4; RTOP = 0 Ω; ITAGC = 0.4 mA 50 100 − mV Vo permissible output voltage from external source; note 2 − − 13.2 V Vsat saturation voltage ITAGC = 1.5 mA − − 0.2 V ∆V TOP ,12 -----------------------∆T variation of takeover point by temperature ITAGC = 0.4 mA − 0.03 0.07 dB/K Isink sink current see Fig.3 no tuner gain reduction; VTAGC = 13.2 V − − 5 µA maximum tuner gain reduction 1.5 2 2.6 mA 1998 Nov 09 7 Philips Semiconductors Product specification Downconverter for DVB SYMBOL ∆GIF PARAMETER IF slip by automatic gain control TDA9829T CONDITIONS MIN. TYP. MAX. UNIT tuner gain current from 20 to 80% − 6 8 dB AFC circuit (pin 14); see notes 7 and 8 and Fig.4 CRstps(US) control steepness ∆I14/∆fIF for USA fIF = 43.75 MHz 0.7 0.98 1.3 µA/kHz CRstps(EU) control steepness ∆I14/∆fIF for Europe fIF = 36.15 MHz 0.45 0.70 0.95 µA/kHz CL < 15 pF; RL > 5 kΩ; with internal AGC 1.8 2.1 2.4 V − 2.5 − V DVB output signal (IF input to DVB output) Vo(p-p) output voltage (pin 11) (peak-to-peak value) VO(DC) DC output voltage B−1dB −1 dB bandwidth 11 12 − MHz B−3dB −3 dB bandwidth − 17 − MHz αC(DVB) fundamental input signal and IF harmonics 35 40 − dB αH suppression of in-band harmonics Vo = 2.0 V (p-p) 30 35 − dB PSRR power supply ripple rejection at pin 11 see Fig.5 26 36 − dB CL < 15 pF; RL > 5 kΩ Notes 1. Performance may be decreased at VP = 4.5 V. 2. This parameter is not tested during production and is only given as application information for designing the television receiver. 3. Mute state also can be achieved by leaving pin 20 open-circuit. 4. Resonance circuit of VCO: Q0 > 50; Cext, Cint and L see Table 2. 5. Temperature coefficient of external LC-circuit is equal to zero. 6. Response speed valid for an IF input level range of 200 µV up to 70 mV. 7. To match the AFC output signal to different tuning systems a current source output is provided. The test circuit is given in Fig.4. The AFC steepness can be changed by the resistors at pin 14. 8. Depending on the ratio ∆C/C0 of the LC resonant circuit of VCO (Q0 > 50; C0 = Cint + Cext; see Table 2). Table 1 Input frequencies, symbol frequencies and VCO frequencies SYMBOL DESCRIPTION DVB (Europe) DVB (USA) UNIT 6.9 5.0 MHz fs Symbol frequency fIF IF frequency 36.15 43.75 MHz fVCO VCO frequency 86.0 97.5 MHz 1998 Nov 09 8 Philips Semiconductors Product specification Downconverter for DVB TDA9829T MHB221 70 gain (dB) 60 handbook, full pagewidth 0.06 Ituner (mA) IF input (mV RMS) 50 0.6 40 0 30 (1) 6 (2) (3) (4) 20 1 10 0 60 2 −10 1 1.5 (1) Ituner; RTOP = 22 kΩ. (2) Gain. 2 2.5 3 3.5 4 V18 (V) (3) Ituner; RTOP = 11 kΩ. (4) Ituner; RTOP = 0 Ω. Fig.3 Typical IF and tuner AGC characteristic. handbook, full pagewidth VP VP = 5 V 22 kΩ TDA9829T 14 V14 (V) I14 (µA) 4.5 −200 3.5 −100 2.5 0 1.5 100 0.5 200 I14 22 kΩ MHB222 (source current) (sink current) 35.75 43.45 36.15 43.75 36.55 44.05 Fig.4 Measurement conditions and typical AFC characteristic. 1998 Nov 09 9 fIF (MHz) 4.5 Philips Semiconductors Product specification Downconverter for DVB TDA9829T MHB223 handbook, full pagewidth VP = 5 V VP = 5 V 100 mV (fripple = 70 Hz) TDA9829T t Fig.5 Ripple rejection condition. MHA661 100 handbook, full pagewidth fVCO (MHz) 99 98 97.5 97 96 95 0 1 2 3 L1 = 115 nH and C1 = 15 pF. Fig.6 VCO control characteristic for DVB (USA). 1998 Nov 09 10 4 V10 (V) 5 Philips Semiconductors Product specification Downconverter for DVB TDA9829T MHA662 89 handbook, full pagewidth fVCO (MHz) 88 87 86 85 84 83 0 1 2 3 L1 = 248 nH and C1 = 5.6 pF. Fig.7 VCO control characteristic for DVB (Europe). 1998 Nov 09 11 4 V10 (V) 5 Philips Semiconductors Product specification Downconverter for DVB TDA9829T TEST CIRCUIT tuner DVB AGC output AFC VP = 5 V handbook, full pagewidth VP = 5 V 22 kΩ (a) (b) 22 kΩ 2 V (p-p) CAGC 2.2 µF 18 DVB output 75 Ω (1) 17 15 16 220 Ω n.c. C1 10 nF 19 BC546 68 Ω L1 mute switch 20 10 µF 100 nF (a) no mute (b) mute 14 13 12 11 7 8 9 10 TDA9829T 1 2 3 4 5 1 51 Ω n.c. 22 kΩ n.c. DVB-IF input 6 (a) (b) 3 2 AGC switch TOP 4 DVB AGC external (a) AGC internal (b) AGC external VCO control DVB AGC adjust MHB224 (1) See Table 2. Fig.8 Test circuit. Table 2 Test circuit values PARAMETER Europe USA IF frequency 36.15 MHz 43.75 MHz VCO frequency 86.0 MHz 97.5 MHz Oscillator circuit alfpage 15 (1) alfpage (2) (3) 16 15 (1) 1998 Nov 09 MHB225 (1) C(VCO) = 8.2 pF. (2) C1 = 15 pF. (3) L1 = 115 nH. (1) C(VCO) = 8.2 pF. (2) C1 = 5.6 pF. (3) L1 = 248 nH. Philips ceramic capacitor (3) 16 MHB225 Toko coil (2) 5KM 369SNS - 2010Z 5KM 369SNS - 1647Z 2222 632 39478 2222 632 33129 12 Philips Semiconductors Product specification Downconverter for DVB TDA9829T INTERNAL PIN CONFIGURATIONS + handbook, halfpage handbook, halfpage 5 kΩ 3 3.6 V + 5 kΩ 1.1 kΩ 3.6 V + 1.1 kΩ 1 1.1 kΩ 2.65 V 4 2.65 V MHB226 MHB227 Fig.9 Pin 1; VSID. Fig.10 Pin 3; ViIF1 and pin 4; ViIF2. handbook, halfpage handbook, halfpage 30 kΩ 20 kΩ 26 kΩ + + 9 kΩ 5 6 3.6 V 3.6 V 1.9 V MHB229 MHB228 Fig.11 Pin 5; TADJ. 1998 Nov 09 Fig.12 Pin 6; AGCSWI. 13 Philips Semiconductors Product specification Downconverter for DVB handbook, halfpage TDA9829T + + handbook, halfpage 50 kΩ 12 kΩ 8 1.6 kΩ 9 10.1 kΩ 3.6 V 17.2 kΩ MHB231 MHB230 Fig.13 Pin 8; VAGC. Fig.14 Pin 9; AGCADJ. + handbook, halfpage + + handbook, halfpage + 10 µA 5.1 kΩ 50 kΩ 50 kΩ 10 11 VCO 12.5 kΩ 5.1 kΩ 2.7 V 2.7 mA 5 µA Fig.15 Pin 10; VVCO. 1998 Nov 09 MHB233 MHB232 Fig.16 Pin 11; VoDVB. 14 Philips Semiconductors Product specification Downconverter for DVB TDA9829T handbook, halfpage + + handbook, halfpage 200 µA 14 12 2.5 mA MHB234 1 kΩ 1 kΩ MHB235 Fig.17 Pin 12; TAGC. handbook, halfpage Fig.18 Pin 14; AFC. + 420 Ω 15 handbook, halfpage GND 17 + MHB237 16 420 Ω 2.8 V MHB236 Fig.19 Pin 15; VCO1 and pin 16; VCO2. 1998 Nov 09 Fig.20 Pin 17; GND. 15 Philips Semiconductors Product specification Downconverter for DVB TDA9829T handbook, halfpage + + 50 kΩ 18 + handbook, halfpage + 19 + MHB239 200 µA 200 µA MHB238 Fig.21 Pin 18; CAGC. handbook, halfpage Fig.22 Pin 19; VP. + 20 13 kΩ 3.6 V MHB240 Fig.23 Pin 20; MUTESWI. 1998 Nov 09 16 Philips Semiconductors Product specification Downconverter for DVB TDA9829T PACKAGE OUTLINE SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.10 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.050 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013AC 1998 Nov 09 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-24 97-05-22 17 Philips Semiconductors Product specification Downconverter for DVB TDA9829T SOLDERING Wave soldering Introduction Wave soldering techniques can be used for all SO packages if the following conditions are observed: There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow. • The package footprint must incorporate solder thieves at the downstream end. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all SO packages. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. 1998 Nov 09 18 Philips Semiconductors Product specification Downconverter for DVB TDA9829T DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1998 Nov 09 19 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com © Philips Electronics N.V. 1998 SCA60 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545104/750/01/pp20 Date of release: 1998 Nov 09 Document order number: 9397 750 04575