Data Sheet Rev. A

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
15-12-01
C. SAFFLE
Make correction to group A subgroups 2 and 3 for output voltage high, (VOH),
A
test with conditions VS = ±15.0 V and RL = 2 kΩ in table I. -rrp
REV
SHEET
REV
A
A
A
A
A
A
A
A
A
A
SHEET
15
16
17
18
19
20
21
22
23
24
REV STATUS
REV
A
A
A
A
A
A
A
A
A
A
A
A
A
A
OF SHEETS
SHEET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PMIC N/A
PREPARED BY
RICK OFFICER
STANDARD
MICROCIRCUIT
DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil
CHECKED BY
RAJESH PITHADIA
APPROVED BY
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
CHARLES F. SAFFLE
DRAWING APPROVAL DATE
15-01-15
REVISION LEVEL
A
MICROCIRCUIT, LINEAR, 30 V, LOW NOISE,
LOW POWER DUAL, OPERATIONAL AMPLIFIER,
MONOLITHIC SILICON
SIZE
CAGE CODE
A
67268
SHEET
DSCC FORM 2233
APR 97
5962-13245
1 OF 24
5962-E094-16
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and
space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or
Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
R
13245
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
01
V
X
A
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
01
Circuit function
ADA4084-2
Radiation hardened 30 V low noise, low power
dual operational amplifier
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
X
Descriptive designator
CDFP3-F10
Terminals
10
Package style
Bottom brazed flat pack
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V.
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DSCC FORM 2234
APR 97
SIZE
5962-13245
A
REVISION LEVEL
A
SHEET
2
1.3 Absolute maximum ratings. 1/
Supply voltage ( +VS to –VS ) ....................................................................................... 36 V
Input voltage (VIN) ........................................................................................................
Differential input voltage ...............................................................................................
Output short circuit duration to GND .............................................................................
Power dissipation (PD) ..................................................................................................
Storage temperature range ...........................................................................................
Junction temperature range (TJ) ...................................................................................
Lead temperature (soldering, 60 seconds) ....................................................................
Thermal resistance, junction-to-case (θJC) ...................................................................
-VS to +VS
±0.6 V 2/
Indefinite
32 mW
-65°C to +150°C
+140°C
+300°C
40°C/W 3/
Thermal resistance, junction-to-ambient (θJA) .............................................................. 52°C/W 3/
1.4 Recommended operating conditions.
Supply voltage ( +VS to –VS ) ....................................................................................... ±1.5 V to ±15 V
Ambient operating temperature range (TA) ................................................................... -55°C to +125°C
1.4.1 Operating performance characteristics.
VS = ±1.5 V.
Differential input resistance .......................................................................................
Differential input capacitance .....................................................................................
Common mode input resistance ................................................................................
Common mode input capacitance .............................................................................
Unity gain crossover, VIN = 5 VPP, RL = 10 kΩ, AV = 1 ............................................
Phase margin ............................................................................................................
100 kΩ 3/
1.1 pF 3/
80 MΩ 3/
2.9 pF 3/
8.08 MHz
86 Degrees
Current noise density, f = 1 kHz ................................................................................ 0.55 pA/ Hz
VS = ±5.0 V.
Differential input resistance .......................................................................................
Differential input capacitance .....................................................................................
Common mode input resistance ................................................................................
Common mode input capacitance .............................................................................
Unity gain crossover, VIN = 5 VPP, RL = 10 kΩ, AV = 1 ............................................
Phase margin ............................................................................................................
100 kΩ 3/
1.1 pF 3/
200 MΩ 3/
2.5 pF 3/
9.6 MHz
85 Degrees
Current noise density ................................................................................................. 0.55 pA/ Hz
VS = ±15.0 V.
Differential input resistance .......................................................................................
Differential input capacitance .....................................................................................
Common mode input resistance ................................................................................
Common mode input capacitance .............................................................................
Unity gain crossover, VIN = 5 VPP, RL = 10 kΩ, AV = 1 ............................................
Phase margin ............................................................................................................
100 kΩ 3/
1.1 pF 3/
200 MΩ 3/
2.5 pF 3/
9.9 MHz
86 Degrees
Current noise density ................................................................................................. 0.55 pA/ Hz
______
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ For input differential voltages greater than 0.6 V, the input current should be limited to less than 5 mA to prevent
degradation or destruction of the input devices.
3/ Measurement taken under absolute worst case condition of still air and represent data taken with a thermal camera for
highest power density location. See MIL-STD-1835 for average package θJC thermal numbers with smaller die size.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-13245
A
REVISION LEVEL
A
SHEET
3
1.5 Radiation features.
Maximum total dose available (dose rate = 50 – 300 rads(Si)/s) .................................. 100 krads(Si) 4/
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://quicksearch.dla.mil or from the Standardization Document Order
Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 as specified herein, or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V.
3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Block diagram. The block diagram shall be as specified on figure 2.
3.2.4 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document
revision level control and shall be made available to the preparing and acquiring activity upon request.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
ambient operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table I.
_____
4/ These parts may be dose rate sensitive in a space environment and may demonstrate enhanced low dose rate effects.
Radiation end point limits for the noted parameters are guaranteed only for the conditions specified in MIL-STD-883,
method 1019, condition A.
STANDARD
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DSCC FORM 2234
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A
REVISION LEVEL
A
SHEET
4
TABLE I. Electrical performance characteristics.
Test
Symbol
Conditions 1/ 2/
VS = ±1.5 V, VCM = 0 V,
Group A
subgroups
Device
type
-55°C ≤ TA ≤ +125°C
unless otherwise specified
Limits
Unit
Min
Max
-100
100
2,3
-200
200
1
-100
100
Input characteristics.
Offset voltage
1
VOS
P, L, R
Offset voltage drift
∆VOS /
01
µV
2,3
01
1.75
µV/°C
1,2,3
01
150
µV
∆T
Offset voltage matching
Channel A versus channel B
P, L, R
Input bias current
1
IB
P, L, R
Input offset current
P, L, R
Common mode rejection ratio
CMRR
AVO
2,3
-450
450
1
-300
300
-25
25
2,3
-50
50
1
-25
25
-1.5
+1.5
01
-1.5
+1.5
01
01
1
1
VCM = ±1.5 V
P, L, R
Large signal voltage gain
300
1,2,3
VIN
150
-300
1
IOS
P, L, R
Input voltage range
1
01
64
2,3
60
1
64
RL = 2 kΩ,
1
-1.3 V ≤ VO ≤ +1.3 V
2
96
3
94
1
100
P, L, R
01
nA
nA
V
dB
100
dB
Output characteristics.
Output voltage high
VOH
1,2,3
RL = 10 kΩ to VCM
P, L, R
RL = 2 kΩ to VCM
P, L, R
01
1.4
1
1.4
1,2,3
1.35
1
1.35
V
See footnote at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-13245
A
REVISION LEVEL
A
SHEET
5
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 1/ 2/
VS = ±1.5 V, VCM = 0 V,
Group A
subgroups
Device
type
-55°C ≤ TA ≤ +125°C
unless otherwise specified
Limits
Min
Unit
Max
Output characteristics - continued.
Output voltage low
VOL
1,2,3
RL = 10 kΩ to VCM
P, L, R
RL = 2 kΩ to VCM
P, L, R
Short circuit current
ISC
Source
source
ISC
Sink
sink
P, L, R
-1.45
1
-1.45
1
-1.4
2,3
-1.35
1
-1.4
1,2,3
P, L, R
01
01
1
-19
V
mA
-19
1,2,3
+20
1
+20
Power supply.
Power supply rejection ratio
PSRR
1
VS = ±1.25 V to ±1.75 V
P, L, R
Supply current both amplifiers
IS
P, L, R
100
2
90
3
80
1
100
1
IO = 0 mA
01
dB
±1350
01
2,3
±1900
1
±1350
µA
Dynamic performance
Slew rate 3/
SR
Gain bandwidth product 3/
GBP
4
RL = 2 kΩ
VIN = 5 mVPP, RL = 10 kΩ,
01
1.7
5
2
6
1.3
V/µs
4,5,6
01
14.4
MHz
4,5
01
11.3
MHz
AV = 100
-3 dB closed loop bandwidth 3/
-3 dB
AV = 1, VIN = 5 mVPP
6
4.8
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-13245
A
REVISION LEVEL
A
SHEET
6
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 1/ 2/
Group A
subgroups
Device
type
-55°C ≤ TA ≤ +125°C
unless otherwise specified
Noise performance
Voltage noise 3/
Limits
Min
enpp
en
Input characteristics.
Offset voltage
0.1 Hz to 10 Hz
4
f = 10 kHz
4
01
0.2
∆VOS /∆T
Offset voltage matching
Channel A versus channel B
P, L, R
CMRR
VCM = ±5 V
P, L, R
AVO
-100
100
2,3
-200
200
1
-100
100
nV/
Hz
01
01
1.75
µV/°C
1,2,3
01
150
µV
1
150
01
-300
300
2,3
-450
450
1
-300
300
-25
25
2,3
-50
50
1
-25
25
-5
+5
-5
+5
01
01
1
01
106
1
106
1,2,3
76
1
76
RL = 2 kΩ,
1
-4 V ≤ VO ≤ 4 V
2
103
3
96
1
108
P, L, R
µV
2,3
1,2,3
VCM = ±4 V
P, L, R
Large signal voltage gain
2.8
1,2,3
VIN
P, L, R
Common mode rejection ratio
3.7
6
1
IOS
P, L, R
Input voltage range
01
4.4
1
IB
P, L, R
Input offset current
0.22
5
1
P, L, R
Input bias current
µVPP
VS = ±5.0 V, VCM = 0 V
VOS
Offset voltage drift
Max
VS = ±1.5 V, VCM = 0 V
5,6
Voltage noise density 3/
Unit
01
nA
nA
V
dB
108
dB
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
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COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-13245
A
REVISION LEVEL
A
SHEET
7
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 1/ 2/
VS = ±5.0 V, VCM = 0 V,
Group A
subgroups
Device
type
-55°C ≤ TA ≤ +125°C
unless otherwise specified
Limits
Min
Unit
Max
Output characteristics.
Output voltage high
VOH
1
RL = 10 kΩ to VCM
P, L, R
RL = 2 kΩ to VCM
P, L, R
Output voltage low
VOL
P, L, R
RL = 2 kΩ to VCM
P, L, R
Short circuit current
ISC
Source
source
ISC
Sink
sink
4.8
1
4.9
1
4.8
2,3
4.7
1
4.8
P, L, R
01
V
-4.9
2,3
-4.8
1
-4.9
1
-4.8
2,3
-4.7
1
-4.8
1,2,3
P, L, R
4.9
2,3
1
RL = 10 kΩ to VCM
01
01
1
-36
V
mA
-36
1,2,3
+35
1
+35
Power supply.
Power supply rejection ratio
PSRR
1
VS = ±2 V to ±18 V
P, L, R
Supply current both amplifiers
IS
P, L, R
110
2,3
105
1
110
1
IO = 0 mA
01
01
dB
±1400
2,3
±2000
1
±1400
µA
See footnotes at end of table.
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DSCC FORM 2234
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REVISION LEVEL
A
SHEET
8
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 1/ 2/
VS = ±5.0 V, VCM = 0 V,
Group A
subgroups
Device
type
-55°C ≤ TA ≤ +125°C
unless otherwise specified
Limits
Min
Unit
Max
Dynamic performance.
Slew rate 3/
SR
4
RL = 2 kΩ to VCM
01
5
GBP
VIN = 5 mVPP, RL = 10 kΩ,
V/µs
2.4
6
Gain bandwidth product 3/
1.8
1.4
4,5,6
01
14.9
MHz
4,5
01
12.9
MHz
AV = 100
-3 dB closed loop bandwidth 3/
-3 dB
AV = 1, VIN = 5 mVPP
6
5.2
Noise performance.
Voltage noise 3/
enPP
0.1 Hz to 1o Hz
4
01
5,6
Voltage noise density 3/
en
f = 10 kHz
4
0.2
µVPP
0.22
01
3.8
5
4.5
6
2.9
nV/ Hz
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
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COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
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REVISION LEVEL
A
SHEET
9
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 1/ 2/
VS = ±15.0 V, VCM = 0 V,
Group A
subgroups
Device
type
-55°C ≤ TA ≤ +125°C
unless otherwise specified
Limits
Unit
Min
Max
-100
100
2,3
-200
200
1
-100
100
Input characteristics.
Offset voltage
1
VOS
P, L, R
Offset voltage drift
01
µV
2,3
01
1.75
µV/°C
Channel A versus channel B
1
01
150
µV
P, L, R
1
∆VOS /
∆T
Offset voltage matching
Input bias current
1
IB
P, L, R
Input offset current
P, L, R
Input voltage range
CMRR
VCM = ±15 V
P, L, R
AVO
2,3
-450
450
1
-300
300
-25
25
2,3
-50
50
1
-25
25
-15
+15
01
-15
+15
01
01
1
1,2,3
VCM = ±14 V
P, L, R
Large signal voltage gain
300
1,2,3
VIN
P, L, R
Common mode rejection ratio
-300
1
IOS
150
01
106
1
106
1,2,3
85
1
85
RL = 2 kΩ,
1
-13.5 V ≤ VO ≤ +13.5 V
2
105
3
100
1
110
P, L, R
01
nA
nA
V
dB
110
dB
Output characteristics.
Output voltage high
VOH
1,2,3
RL = 10 kΩ to VCM
P, L, R
RL = 2 kΩ to VCM
P, L, R
01
14.8
1
14.8
1,2
14.5
3
13.0
1
14.5
V
See footnotes at end of table.
STANDARD
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DSCC FORM 2234
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REVISION LEVEL
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SHEET
10
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 1/ 2/
VS = ±15.0 V, VCM = 0 V,
Group A
subgroups
Device
type
-55°C ≤ TA ≤ +125°C
unless otherwise specified
Limits
Min
Unit
Max
Output characteristics - continued.
Output voltage low
VOL
1
RL = 10 kΩ to VCM
P, L, R
RL = 2 kΩ to VCM
P, L, R
Short circuit current
ISC
Source
source
ISC
sink
-14.8
1
-14.9
1
-14.8
2,3
-14.7
1
-14.8
01
1
Sink
P, L, R
-14.9
2,3
1,2,3
P, L, R
01
-71
V
mA
-71
1,2,3
+35
1
+35
Power supply.
Power supply rejection ratio
PSRR
1
VS = ±2 V to ±18 V
P, L, R
Supply current both amplifiers
IS
P, L, R
110
2,3
105
1
110
1
IO = 0 mA
01
dB
±1500
01
2,3
±2100
1
±1500
µA
Dynamic performance
Slew rate 3/
SR
Gain bandwidth product 3/
GBP
4
RL = 2 kΩ
VIN = 5 mVPP, RL = 10 kΩ,
01
1.9
5
2.4
6
1.5
V/µs
4,5,6
01
14.9
MHz
4,5
01
12.9
MHz
AV = 100
-3 dB closed loop bandwidth 3/
-3 dB
AV = 1, VIN = 5 mVPP
6
6
See footnotes at end of table.
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REVISION LEVEL
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11
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions 1/ 2/
VS = ±15.0 V, VCM = 0 V,
Group A
subgroups
Device
type
-55°C ≤ TA ≤ +125°C
unless otherwise specified
Limits
Min
Unit
Max
Noise performance
Voltage noise 4/ 5/
enPP
0.1 Hz to 10 Hz
4
01
5,6
Voltage noise density 3/
en
f = 1 kHz
4
0.2
µVPP
0.22
01
3.9
5
4.6
6
3.1
nV/ Hz
1/ Device type 01 supplied to this drawing has been characterized through all levels P, L, R of irradiation.
Pre and Post irradiation values are identical unless otherwise specified in Table I. When performing post irradiation
electrical measurements for any RHA level, TA = +25°C.
2/ These parts may be dose rate sensitive in a space environment and may demonstrate enhanced low dose rate effects.
Radiation end point limits for the noted parameters are guaranteed only for the conditions specified in MIL-STD-883,
method 1019, condition A.
3/ Parameter is part of device initial characterization which is only repeated after major design and process changes or with
subsequent wafer lots. Not tested post irradiation.
4/ Not tested post irradiation.
5/ The test parameter enPP is 100% production tested at VS = ±15 V, TA = ambient temperature.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance
submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the
manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall
be provided with each lot of microcircuits delivered to this drawing.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-13245
A
REVISION LEVEL
A
SHEET
12
Device type
01
Case outline
X
Terminal
number
Terminal
symbol
1
NC/GND
2
OUTA
3
-INA
Operational amplifier negative input, amplifier A.
4
+INA
Operational amplifier positive input, amplifier A.
5
-VS
6
NC/GND
7
+INB
Operational amplifier positive input, amplifier B.
8
-INB
Operational amplifier negative input, amplifier B.
9
OUTB
10
+VS
Description
No connect or ground. No internal circuitry
connected so user may ground pin if desired.
Operational amplifier output, amplifier A.
Negative power supply.
No connect or ground. No internal circuitry
connected so user may ground pin if desired.
Operational amplifier output, amplifier B.
Positive power supply.
FIGURE 1. Terminal connections.
STANDARD
MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-13245
A
REVISION LEVEL
A
SHEET
13
FIGURE 2. Block diagram.
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MICROCIRCUIT DRAWING
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DSCC FORM 2234
APR 97
SIZE
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A
REVISION LEVEL
A
SHEET
14
4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection.
4.2.1 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections, and as specified herein.
4.4.1 Group A inspection.
a.
Tests shall be as specified in table IIA herein.
b.
Subgroups 7, 8, 9, 10, and 11 in table I, method 5005 of MIL-STD-883 shall be omitted.
c.
Subgroups 4, 5, and 6 are tested as part of device initial characterization and after design and process
changes or with subsequent wafer lots as indicated in Table I.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
STANDARD
MICROCIRCUIT DRAWING
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DSCC FORM 2234
APR 97
SIZE
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REVISION LEVEL
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SHEET
15
TABLE IIA. Electrical test requirements.
Test requirements
Interim electrical
parameters (see 4.2)
Final electrical
parameters (see 4.2)
Group A test
requirements (see 4.4)
Group C end-point electrical
parameters (see 4.4)
Group D end-point electrical
parameters (see 4.4)
Group E end-point electrical
parameters (see 4.4)
1
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Device
Device
class Q
class V
1
1, 2, 3, 1/
4, 5, 6
1, 2, 3, 4, 5, 6
1, 2, 3, 4, 5, 6
1, 2, 3, 1/ 2/
4, 5, 6
1, 2, 3,
4, 5, 6
1, 2, 3, 4 2/
1, 2, 3
1, 2, 3
---
1
1/ PDA applies to subgroup 1.
2/ Delta limits as specified in table IIB shall be required where specified,
and the delta limits shall be completed with reference to the zero hour
electrical parameters (see table I).
TABLE IIB. Burn-in and operating life test delta parameters. 1/
Parameters
Symbol
Delta limits
Units
Supply current at VS = ±1.5 V
IS
±33
µA
Supply current at VS = ±5 V
IS
±21
µA
Supply current at VS = ±15 V
IS
±12
µA
Offset voltage at VS = ±1.5 V
VOS
±36
µV
Offset voltage at VS = ±5 V
VOS
±35
µV
Offset voltage at VS = ±15 V
VOS
±35
µV
Input bias current at VS = ±1.5 V
IB
±7
nA
Input bias current at VS = ±5 V
IB
±10
nA
Input bias current at VS = ±15 V
IB
±6
nA
1/ 240 hour burn in and group C end point electrical parameters.
Deltas are performed at TA = +25°C.
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DSCC FORM 2234
APR 97
SIZE
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16
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a.
End-point electrical parameters shall be as specified in table IIA herein.
b.
For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. All device classes must meet the postirradiation end-point
electrical parameter limits as defined in table I at TA = +25°C ±5°C, after exposure, to the subgroups specified in
table IIA herein.
4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883
method 1019, condition A and as specified herein.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform DLA Land and Maritime when a system application requires
configuration control and which SMD's are applicable to that system. DLA Land and Maritime will maintain a record of users and
this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-8108.
6.4 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990,
or telephone (614) 692-0540.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in
MIL-HDBK-103 and QML-38535. The vendors listed in MIL-HDBK-103 and QML-38535 have submitted a certificate of
compliance (see 3.6 herein) to DLA Land and Maritime-VA and have agreed to this drawing.
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MICROCIRCUIT DRAWING
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COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
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REVISION LEVEL
A
SHEET
17
6.7 Application notes.
6.7.1 Functional description. The device is a precision single supply, rail-to-rail operational amplifier. Intended for portable
instrumentation, the device combines the attributes of precision, wide bandwidth, and low noise to make it an ideal choice in
single supply applications that require both ac and precision dc performance. Other low supply voltage applications for which
the device is well suited are active filters, audio microphone preamplifiers, power supply control, and telecommunications.
To combine all of these attributes with rail-to-rail input/output operation, novel circuit design techniques are used.
Figure 3. Equivalent input circuit.
For example, figure 3 illustrates a simplified equivalent circuit for the input stage of the device. It comprises a pnp differential
pair, Q1 and Q2, and an npn differential pair, Q3 and Q4, operating concurrently. Diode D100 and diode D101 serve to clamp
the applied differential input voltage to the device, thereby protecting the input transistors against zener breakdown of the
emitter-base junctions. Input stage voltage gains are kept low for input rail-to-rail operation. The two pairs of differential
output voltages are connected to the second stage of the device, which is a modified compound folded cascade gain stage.
It is also in the second gain stage, where the two pairs of differential output voltages are combined into a single-ended output
signal voltage used to drive the output stage.
A key issue in the input stage is the behavior of the input bias currents over the input common-mode voltage range. Input bias
currents in the device are the arithmetic sum of the base currents in Q1 and Q4 and in Q2 and Q3. As a result of this design
approach, the input bias currents in the device not only exhibit different amplitudes; they also exhibit different polarities.
This effect is best illustrated by figure 4, figure 5, and figure 6. It is therefore important that the effective source impedances
connected to the device inputs be balanced for optimum dc and ac performance.
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DSCC FORM 2234
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Figure 4. Input bias current versus VCM and temperature.
______________________________________
Figure 5. Input bias current versus VCM and temperature.
______________________________________
Figure 6. Input bias current versus VCM and temperature.
______________________________________
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6.7.1 Functional description - continued. To achieve rail-to-rail output, the device output stage design employs a unique
topology for both sourcing and sinking current. This circuit topology is illustrated in figure 7. The output stage is voltage driven
from the second gain stage. The signal path through the output stage is inverting; that is, for positive input signals,
Q13 provides the base current drive to Q19 so that it conducts (sinks) current. For negative input signals, the signal path via
Q18 → mirror → Q24 provides the base current drive for Q23 to conduct (source) current. Both transistors provide output
current until they are forced into saturation.
Figure 7. Equivalent output circuit.
Thus, the saturation voltage of the output transistors sets the limit on the device maximum output voltage swing. Output shortcircuit current limiting is determined by the maximum signal current into the base of Q13 from the second gain stage. The
output stage also exhibits voltage gain. This is accomplished by the use of common-emitter amplifiers, and, as a result, the
voltage gain of the output stage (thus, the open-loop gain of the device) exhibits a dependence on the total load resistance at
the output of the device.
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MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
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REVISION LEVEL
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SHEET
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6.7.2 Startup characteristics. The device is specified to operate from 3 V to 30 V (±1.5 V to ±15 V) under nominal power
supplies. During power up as the supply voltage increases from 0 V to the nominal power supply voltage, the supply current (IS)
increases as well to the point at which it stabilizes and the amplifier is ready to operate. The stabilization varies with
temperature, as shown in figure 8, below such that at −40°C it takes a higher voltage and stabilizes at a lower supply current
than at hot temperatures where it takes a lower voltage but stabilizes at a higher current. In all cases, the device is specified to
start up and operate at a minimum of 3 V under all temperature conditions.
Figure 8. Supply current versus supply voltage.
6.7.3 Input protection. As with any semiconductor device, if conditions exist where the applied input voltages to the device
exceed either supply voltage, the input overvoltage I-to-V characteristic of the device must be considered. When an overvoltage
occurs, the amplifier may be damaged, depending on the magnitude of the applied voltage and the magnitude of the fault
current.
The D1, D2, D4, and D5 diodes conduct when the input common-mode voltage exceeds either supply pin by a diode drop. This
varies with temperature and is in the range of 0.3 V to 0.8 V. As illustrated in the simplified equivalent circuit shown in figure 3,
the device does not have any internal current limiting resistors; thus, fault currents can quickly rise to damaging levels.
This input current is not inherently damaging to the device, provided that it is limited to 5 mA or less. If a fault condition causes
more than 5 mA to flow, an external series resistor should be added at the expense of additional thermal noise. Figure 9
illustrates a normal noninverting configuration for an overvoltage-protected amplifier where the series resistance, RS, is chosen,
such that: RS = ( VIN(MAX) – VSUPPLY ) / 5 mA.
For example, a 1 kΩ resistor protects the device against input signals up to 5 V above and below the supplies. Note that the
thermal noise of a 1 kΩ resistor at room temperature is 4 nV/ Hz , which exceeds the voltage noise of the device. For other
configurations where both inputs are used, each input should be protected against abuse with a series resistor. Again, to
ensure optimum dc and ac performance, it is recommended that source impedance levels be balanced.
Figure 9. Resistance in series with input limits overvoltage currents to safe values.
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MICROCIRCUIT DRAWING
DLA LAND AND MARITIME
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DSCC FORM 2234
APR 97
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6.7.3 Input protection - continued. To protect Q1-Q2 and Q3-Q4 from large differential voltages that may result in Zener
breakdown of the emitter-base junction, D100 and D101 are connected between the two inputs. This precludes operation as a
comparator. For a more complete description, see the manufacturer’s datasheet.
6.7.4 Output phase reversal. Some operational amplifiers designed for single-supply operation exhibit an output voltage
phase reversal when their inputs are driven beyond their useful common-mode range. Normally, for single-supply bipolar
operational amplifiers, the negative supply determines the lower limit of their common mode range. With these devices, external
clamping diodes, with the anode connected to ground and the cathode to the inputs, prevent input signal excursions from
exceeding the negative supply of the device (that is, GND), preventing a condition that causes the output voltage to change
phase. JFET input amplifiers can also exhibit phase reversal, and, if so, a series input resistor is usually required to prevent it.
The device is free from reasonable input voltage range restrictions, provided that input voltages no greater than the supply
voltages are applied.
Although device output does not change phase, large currents can flow through the input protection diodes. Therefore, the
technique recommended in the input protection section should be applied to those applications where the likelihood of input
voltages exceeding the supply voltages is high.
6.7.5 Designing low noise circuits in single supply applications. In single supply applications, devices like the device extend
the dynamic range of the application through the use of rail-to-rail operation. Referring to the operational amplifier noise model
circuit configuration illustrated in figure 10, the expression for an amplifier’s total equivalent input noise voltage for a source
resistance level, RS, is given by
enT =
2
2
2
2[(enR) + (inOA x RS) ] + (enOA) , units in V/ Hz .
2
where: RS = 2R, the effective, or equivalent, circuit source resistance. (enR) is the source resistance thermal noise voltage
power (4kTR). k is the Boltzmann’s constant, 1.38 × 10
–23
J/K. T is the ambient temperature in Kelvin of the circuit,
2
273.15 + TA (°C). (inOA) is the operational amplifier equivalent input noise current spectral power (1 Hz bandwidth). (enOA)
is the operational amplifier equivalent input noise voltage spectral power (1 Hz bandwidth).
2
Figure 10. Operational amplifier noise circuit mode.
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6.7.5 Designing low noise circuits in single supply applications - continued. As a design aid, figure 11 shows the total
equivalent input noise of the device and the total thermal noise of a resistor for comparison. Note that for source resistance less
than 1 kΩ, the equivalent input noise voltage of the device is dominant.
Figure 11. Equivalent thermal noise versus total source resistance.
Because signal to noise ratio (SNR) circuit is the critical parameter in the final analysis, the noise behavior of a circuit is
sometimes expressed in terms of its noise figure, NF. The noise figure is defined as the ratio of a circuit’s output signal to noise
to its input signal to noise.
Noise figure is generally used for RF and microwave circuit analysis in a 50 Ω system. This is not very useful for operational
amplifier circuits where the input and output impedances can vary greatly. For a more complete description of noise figure, see
the manufacturer’s datasheet.
Signal levels in the application invariably increase to maximize circuit SNR, which is not an option in low voltage, single-supply
applications.
Therefore, to achieve optimum circuit SNR in single-supply applications, it is recommended that an operational amplifier with the
lowest equivalent input noise voltage be chosen, along with source resistance levels that are consistent with maintaining low
total circuit noise.
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MICROCIRCUIT DRAWING
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6.7.6 Comparator operation. Although operational amplifiers are quite different from comparators, occasionally an unused
section of a dual or a quad operational amplifier can be used as a comparator; however, this is not recommended for any rail-torail output operational amplifiers. For rail-to-rail output operational amplifiers, the output stage is generally a ratioed current
mirror with bipolar or metal oxide semiconductor field effect transistors (MOSFET). With the part operating open loop, the
second stage increases the current drive to the ratioed mirror to close the loop. However, it cannot, which results in an increase
in supply current. With the operational amplifier configured as a comparator, the supply current can be significantly higher (see
figure 12). An unused section should be configured as a voltage follower with the noninverting input connected to a voltage
within the input voltage range. The device has unique second stage and output stage designs that greatly reduce the excess
supply current when the operational amplifier is operating open loop.
Figure 12. Supply current versus supply voltage.
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MICROCIRCUIT DRAWING
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STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 15-12-01
Approved sources of supply for SMD 5962-13245 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DLA Land and Maritime-VA. This information
bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DLA Land and Maritime
maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962R1324501VXA
24355
ADA4084-2AF/QMLR
1/ The lead finish shown for each PIN representing a hermetic package
is the most readily available from the manufacturer listed for that part.
If the desired lead finish is not listed contact the vendor to determine
its availability.
2/ Caution. Do not use this number for item acquisition. Items acquired
to this number may not satisfy the performance requirements of this drawing.
Vendor CAGE
number
24355
Vendor name
and address
Analog Devices
Route 1 Industrial Park
P.O. Box 9106
Norwood, MA 02062
Point of contact: 7910 Triad Center
Greensboro, NC 27409-9605
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.