Supertex inc. HV738DB1 HV738 ±65V 0.75A Ultrasound Pulser Demoboard Introduction The HV738 is a monolithic four channel, high speed, high voltage, ultrasound transmitter pulser. This integrated, high performance circuit is in a single 7x7mm, 48-lead QFN package. The HV738 can deliver up to ±0.75A source and sink current to a capacitive transducer. It is designed for medical ultrasound imaging and ultrasound material NDT applications. It can also be used as a high voltage driver for other piezoelectric or capacitive MEMS transducers, or for ATE systems and pulse signal generators as a signal source. HV738’s circuitry consists of controller logic circuits, level translators, gate driving buffers and a high current and high voltage MOSFET output stage. The output stages of each channel are designed to provide peak output currents over ±1.1A for pulsing, when MC0 = 1 and MC1 = 1, with up to ±65V swings. When in mode 1, all the output stages drop the peak current to ±140mA for low-voltage CW mode operation to save power. Two floating 8.0VDC power supplies, referenced to VPP and VNN, supply the P- and N-type power FET gate drivers. This pulser waveform’s frequency upper limit is 20MHz depending on the load capacitance. One HV738 can also be used as four damping circuits to generate fast return-to-zero waveforms by working with another HV738 as four pulsing circuits. It also has built-in under-voltage and over-temperature protection functions. Designing a Pulser with HV738 This demoboard data sheet describes how to use the HV738DB1 to generate the basic high voltage pulse waveform as an ultrasound transmitting pulser. The HV738 circuit uses the DC coupling method in all level translators. There are no external coupling capacitors needed. The VPP and VNN rail voltages can be changed rather quickly, compared to a high voltage capacitor gate coupled driving pulser. This direct coupling topology of the gate drivers not only saves two high voltage capacitors per channel, but also makes the PCB layout easier. The input stage of the HV738 has high-speed level translators that are able to operate with logic signals of 1.2 to 5.0V and are optimized at 2.5 to 3.3V. In this demoboard, the control logic signals are connected to a high-speed ribbon cable connector. The control signal logic-high voltage should be the same as the VCC voltage of the demoboard, and the logic-low should be reference to GND. The HV738DB1 output waveforms can be displayed by using an oscilloscope probe directly connected to the test point TX1~4 and GND. The soldering jumper can select whether or not to connect the on-board equivalent-load, a 330pF, 200V capacitor, parallel with a 2.5kΩ, 1W resistor. Also, a coaxial cable can be used to connect the user’s transducer to easily drive and evaluate the HV738 transmitter pulser. Typical Application Circuit +2.5V VCC +8.0V VLL +65V VDD VPP-8V VSUB 0V to +65V VPP VPF OTP EN RGND MC0 Level Translator MC1 Logic Control PIN1 P-Driver TXP1 NIN1 HV738 GREF Level Translator TXN1 RGND VNF VSS GND GND N-Driver 1 of 4 Channels Shown Doc.# DSDB-HV738DB1 B070114 HVOUT1 VNN + 8V VNN 0 to -65V Supertex inc. www.supertex.com HV738DB1 The PCB Layout Techniques Testing the Integrated Pulser The large thermal pad at the bottom of the HV738 package is connected to the VSUB pins to ensure that it always has the highest potential of the chip, in any condition. VSUB is the connection of the IC’s substrate. PCB designers need to pay attention to the connecting traces as the output TXP1~4, TXN1~4 high-voltage and high-speed traces. In particular, low capacitance to the ground plane and more trace spacing need to be applied in this situation. This HV738 pulser demoboard should be powered up with multiple lab DC power supplies with current limiting functions. The following power supply voltages and current limits have been used in the testing: VPP = 0 to +65V 5.0mA, VNN = 0 to -65V 5.0mA, VDD = +8.0V 10mA, (VPP - VPF) = +8.0V 10mA, (VNF - VNN) = +8.0V 10mA. VCC = +2.5V 5.0mA for HV738 VLL does not include the user’s logic circuits. The power-up or down sequences of the voltage supply ensure that the HV738 chip substrate VSUB is always at the highest potential of all the voltages supplied to the IC. High-speed PCB trace design practices that are compatible with about 50 to 100MHz operating speeds are used for the demoboard PCB layout. The internal circuitry of the HV738 can operate at quite a high frequency, with the primary speed limitation being load capacitance. Because of this high speed and the high transient currents that result when driving capacitive loads, the supply voltage bypass capacitors and the driver to the FET’s gate-coupling capacitors should be as close to the pins as possible. The VSS pin pads should have low inductance feed-through connections that are connected directly to a solid ground plane. The VDD, VPP, VPF, VNF and VNN supplies can draw fast transient currents of up to ±1.5A, so they should be provided with a low-impedance bypass capacitor at the chip’s pins. A ceramic capacitor of up to 0.22 to 1.0µF may be used. Minimize the trace length to the ground plane, and insert a ferrite bead in the power supply lead to the capacitor to prevent resonance in the power supply lines. For applications that are sensitive to jitter and noise and using multiple HV738 ICs, insert another ferrite bead between VDD and decouple each chip supply separately. The (VPP - VPF) and (VNF - VNN) are the two floating power supplies. They are only 8.0V, but floating with VPP and VNN. The floating voltages can be trimmed within the range of +7.5 to +10V to match the rising and falling time of the output pulses for the best HD2. Do not exceed the maximum voltage of +10V. The VPP and VNN are the positive and negative high voltages. They can be varied from 0 to +/-65V maximum. Note when the VPP = VNN =0, the VPF and VNF in respect to the ground voltage is -8.0V and +8.0V. The on-board dummy load 330pF//2.5kΩ should be connected to the high voltage pulser output through the solder jumper when using an oscilloscope’s high impedance probe to meet the typical loading conditions. To evaluate different loading conditions, one may change the values of RC within the current and power limit of the device. In order to drive piezo transducers with a cable, one should match the output load impendence properly to avoid cable and transducer reflections. A 70 to 75Ω coaxial cable is recommended. The coaxial cable end should be soldered to the TX1~4 and GND directly with very short leads. If a user’s load is being used, the on board dummy load should be disconnected by cutting the small shorting copper trace in between the zero ohm resistors R7, R8, R9 or R10 pads. They are shorted by factory default. Pay particular attention to minimizing trace lengths and using sufficient trace width to reduce inductance. Surface mount components are highly recommended. Since the output impedance of HV738’s high voltage power stages are very low, in some cases it may be desirable to add a small value resistor in series with the output TXP1~4 and TXN1~4 to obtain better waveform integrity at the load terminals. This will, of course, reduce the output voltage slew rate at the terminals of a capacitive load. Be aware of the parasitic coupling from the outputs to the input signal terminals of HV738. This feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. Since the input operates with signals down to 1.2V, even small coupling voltages may cause problems. Use of a solid ground plane and good power and signal layout practices will prevent this problem. Also ensure that the circulating ground return current from a capacitive load cannot react with common inductance to create noise voltages in the input logic circuitry. Doc.# DSDB-HV738DB1 B070114 All the on-board test points are designed to work with the high impedance probe of the oscilloscope. Some probes may have limited input voltage. When using the probe on these high voltage test-points, make sure that VPP/VNN voltages do not exceed the probe limit. Using the high impendence oscilloscope probe for the on-board test points, it is important to have short ground leads to the circuit board ground plane. Precautions need to be applied to not overlap the logic-high time periods of the control signals. Otherwise, permanent damage to the device may occur when cross-conduction or shoot-through current exceed the device’s maximum limits. 2 Supertex inc. www.supertex.com HV738DB1 Schematic D1 BAV99 TP1 1 TP15 TP12 TP17 TP19 3 4 TP13 5 6 TP18 7 8 TP20 9 10 43 VPP 44 45 17 VPF VPF VSUB 16 25 36 VSUB VSUB VSUB VDD VDD PIN2 NIN2 PIN3 NIN3 PIN4 NIN4 47 TXP1 34 TXN1 33 TXP2 U1 HV738K6 PIN1 NIN1 GREF HEADER 12X2 TP11 31 TXP3 30 TXN3 29 TXP4 28 TXN4 27 C13 VNF 2 1 D9 VCC D10 B1100-13 1 2 VNN R12 1 VNF VNN VDD R13 10 VNN R14 10 R15 10 VPP VPF R16 10 1 2 3 4 5 6 7 8 VPP VPP B1100-13 1 2 VDD D7 2 1 BAT54DW-7 VPP D5 VSUB B1100-13 D8B B1100-13 4 VNN VSUB 3 6 D8A 1 VPF BAT54DW-7 3 BAT54DW-7 VCC D6B 4 D6A VNF BAT54DW-7 6 VCC 1 VDD C15 1µ 100V C14 1µ 100V J2 HEADER 8 R17 10 VSUB R4 10 R2 2.55K 1W TP14 D3 BAV99 TP16 1 3 TX3 R9 0 2 C11 330p 250V TP21 R3 2.55K 1W D4 BAV99 TP22 0.22 TX2 R8 0 C10 330p 250V 32 TXN2 3 2 1 C12 0.22 TP8 1 RGND RGND TP7 R1 2.55K 1W TP3 D2 BAV99 26 35 TP6 EN NIN1 PIN1 NIN2 PIN2 NIN3 PIN3 NIN4 PIN4 OTP MC1 MC0 VNN VNN VNN VNN VNN VNN 2 4 6 8 10 12 14 16 18 20 22 24 37 1 3 5 7 9 11 13 15 17 19 21 23 VLL OTP EN MC1 MC0 VSS VSS J1 VCC 48 13 46 14 15 TP10 2 11 R11 1K TP9 C6 0.22 C5 1µ 100V 18 19 20 41 42 C4 0.22 1 12 C3 0.22 C1 330p 250V C9 1µ 100V TX1 R7 0 2 VPP C8 TP2 1µ 100V C7 0.22 40 39 38 23 22 21 C2 0.22 TP5 TP25 VPF VNF VNF TP4 VSUB VPP VPP VPP VPP VPP VDD 24 VCC 3 R5 0 TP23 3 R10 0 2 +65V > VSUB > VPP VCC = +3.3V VDD = +8V (VPP - VPF) = +8V (VNF - VNN) = +8V VPP = 0 to +65V VNN = 0 to -65V TX4 C16 330p 250V TP24 R6 2.55K 1W Board Layout Doc.# DSDB-HV738DB1 B070114 3 Supertex inc. www.supertex.com HV738DB1 Board Voltage Supply Power-Up Sequence VSUB 1 VCC 2 VDD 3 4 VPF and VNF 5 VPP / VNN 6 Logic Active +65V>VSUB/VPP positive bias voltages +1.2 to 5.0V positive logic supply voltage +8V positive drive supply voltage Floating supply voltages, (VPP - VPF) = +8.0V and (VNF - VNN) = +8.0V 0 to +/-65V positive and negative high voltages Any logic control active high signals Connector and Test Pin Description Logic Control Signal Input Connector 1 VCC Logic-high reference voltage input, VLL, +1.2 to 5.0V, normally from control circuit. 2 EN Pulser output enable logic signal input, active high. 3 GND Logic signal ground, 0V(2). 4 NIN1 Logic signal input for CH1 negative pulse output, active high.(1) 5 GND Logic signal ground, 0V. 6 PIN1 Logic signal input for CH1 positive pulse output, active high.(1) 7 GND Logic signal ground, 0V. 8 NIN2 Logic signal input for CH2 negative pulse output, active high.(1) 9 GND Logic signal ground, 0V. 10 PIN2 Logic signal input for CH2 positive pulse output, active high.(1) 11 GND Logic signal ground, 0V. 12 NIN3 Logic signal input for CH3 negative pulse output, active high.(1) 13 GND Logic signal ground, 0V. 14 PIN3 Logic signal input for CH3 positive pulse output, active high.(1) 15 GND Logic signal ground, 0V. 16 NIN4 Logic signal input for CH4 negative pulse output, active high.(1) 17 GND Logic signal ground, 0V. 18 PIN4 Logic signal input for CH4 positive pulse output, active high.(1) 19 GND Logic signal ground, 0V. 20 OTP Over temperature protection open drain output, active low, 1.0k pull up to VCC. 21 GND Logic signal ground, 0V. 22 MC1 Logic signal input of mode control MSB. 23 GND Logic signal ground, 0V. 24 MC0 Logic signal input of mode control LSB. Power Supply Connector Logic-high reference voltage supply, +1.2 to 5.0V current limit 5.0mA (if for VLL only). 1 VCC 2 GND 3 VDD +8V positive driver voltage supply with current limit to 10mA. 4 VNN 0 to -65V Negative high voltage supply with current limit to 5.0mA 5 VNF Floating voltage supply (VNF - VNN)= +8.0V with current limit to 10mA.(3) 6 VPF Floating voltage supply (VPP - VPF)= +8.0V with current limit to 10mA.(3) 7 VPP 0 to +65V positive high voltage supply with current limit to 2.0mA 8 VSUB Chip substrate bias voltage, must be (+65V>VSUB/VPP) with limit to 5.0mA Low voltage power supply ground, 0V Note: (1). Overlap control signals logic-high periods of PIN and NIN may cause the device permanent damage. (2). Due to the speed of logic control signal, every GND wire in the ribbon cable must connect to signal source ground. (3). (VPP-VPF) and (VNF-VNN) floating voltage can be trimmed from +7.5V to +10V for tr/tf time matching. Do not exceed the maximum +10V. Doc.# DSDB-HV738DB1 B070114 4 Supertex inc. www.supertex.com HV738DB1 HV738DB1 Waveforms Figure 1: Output waveform of 20MHz, VLL= 2.5V, VDD = +8.0V, (VPP- VPF) = +8.0V, (VNF- VNN) = +8.0V, VPP/VNN= +/-65V, MC0=MC1=1, HV738 TX4 via 200Ω and 20dB Attenuator & SMA-BNC RG316 cable to Ch4 50Ω oscilloscope input. Figure 2: Output waveform of 10MHz VLL = 2.5V, VDD = +8.0V, (VPP- VPF) = +8.0V, (VNF-VNN) = +8.0V, VPP/VNN= +/-65V, MC0=MC1=1, TX4 via 200Ω and 20dB Attenuator & SMA-BNC RG316 cable to Ch4 50Ω oscilloscope input. Doc.# DSDB-HV738DB1 B070114 5 Supertex inc. www.supertex.com HV738DB1 Figure 3: Input to output propagation delay on rise is 17.6ns VLL= 2.5V, VDD=+8.0V, (VPP- VPF) = +8.0V, (VNF- VNN) = +8.0V, VPP/VNN = +/-65V, MC0=MC1=1, TX4 via 200Ω and 20dB Attenuator & SMA-BNC RG316 cable to Ch4 50Ω oscilloscope input. Figure 4: Input to output propagation delay on fall is 17.6ns. VLL= 2.5V, VDD = +8.0V, (VPP- VPF) = +8.0V, (VNF- VNN) = +8.0V, VPP/VNN = +/-65V, MC0=MC1=1, TX4 via 200Ω and 20dB Attenuator & SMA-BNC RG316 cable to Ch4 50Ω oscilloscope input. Doc.# DSDB-HV738DB1 B070114 6 Supertex inc. www.supertex.com HV738DB1 Figure 5: Output rise and fall time is 31ns and 40ns. VLL = 2.5V, VDD = +8.0V, (VPP- VPF) = +8.0V, (VNF- VNN) = +8.0V, VPP/VNN = +/-65V, MC0=MC1=1, with load of 330pF//2.5kΩ. TX1 via 200Ω and 20dB Attenuator & SMA-BNC RG316 cable to Ch4 50Ω oscilloscope input. Figure 6: Output waveform of 5.0MHz, VLL = 2.5V, VDD = +8.0V, (VPP- VPF) = +8.0V, (VNF- VNN) = +8.0V, VPP/VNN = +/-5.0V, MC0=MC1=1, with load of 330pF//2.5kΩ. HV738 TX1 via 200Ω and 20dB Attenuator & SMA-BNC RG316 cable to Ch4 50Ω oscilloscope input. Doc.# DSDB-HV738DB1 B070114 7 Supertex inc. www.supertex.com HV738DB1 Figure 7: Output waveform of 5.0MHz, VLL = 2.5V, VDD = +8.0V, (VPP- VPF) = +8.0V, (VNF -VNN) = +8.0V, VPP/VNN = +/-5.0V, MC0=0, MC1=1, with load of 330pF//2.5kΩ. TX1 via 200Ω and 20dB Attenuator & SMA-BNC RG316 cable to Ch4 50Ω oscilloscope input. Figure 8: Output waveform of 5.0MHz, VLL = 2.5V, VDD = +8.0V, (VPP- VPF) = +8.0V, (VNF - VNN) = +8.0V, VPP/VNN = +/-5.0V, MC0=1, MC1=0, with load of 330pF//2.5kΩ. TX1 via 200Ω and 20dB Attenuator & SMA-BNC RG316 cable to Ch4 50Ω oscilloscope input. Doc.# DSDB-HV738DB1 B070114 8 Supertex inc. www.supertex.com HV738DB1 Figure 9: Output waveform of 5.0MHz, VLL= 2.5V, VDD = +8.0V, (VPP - VPF) = +8.0V, (VNF - VNN) = +8.0V, VPP/VNN = +/-5.0V, MC0=0, MC1=0, with load of 330pF//2.5kΩ. TX1 via 200Ω and 20dB attenuator & SMA-BNC RG316 cable to Ch4 50Ω oscilloscope input. Figure 10: Output waveform of 20MHz, VLL= 2.5V, VDD= +8.0V, (VPP - VPF) = +8.0V, (VNF - VNN) = +8.0V, VPP/VNN = +/-5.0V, MC0=1, MC1=1, with load of 330pF//2.5kΩ. TX1 via 200Ω and 20dB Attenuator & SMA-BNC RG316 cable to Ch4 50Ω oscilloscope input. Doc.# DSDB-HV738DB1 B070114 9 Supertex inc. www.supertex.com HV738DB1 Bill of Materials Component Description Manufacturer Part Number C1, C10, C11, C16 CAP CERAMIC 330PF 200V X7R 0603 Panasonic ECJ-1VB2D331K C2, C3, C4, C6, C7, C12, C13 CAP CER .22µF 16V X7R 10% 0603 TDK Corp C1608X7R1C224K080AC C5, C8, C9, C14, C15 CAP CER 1µF 100V X7R 20% 1210 TDK Corp C3225X7R2A105M200AA D1, D2, D3, D4 DIODE DUAL SW 75V 350MW SOT-23 Diodes Inc BAV99-7 D5, D7, D9, D10 DIODE SCHOTTKY 100V 1A SMA Diodes Inc B1100-13-F D6, D8 DIODE SCHOTTKY DUAL 30V SOT-363 Diodes Inc BAT54CDW-7-F J1 CONN HEADER 24POS .100 VERT GOLD Molex 10897242 J2 CONN HEADER VERT .100 8POS 30AU TE Connectivity 3-641215-8 R1, R2, R3, R6 RES 2.55kΩ 1W 1% 2512 SMD Panasonic ERJ-1TNF2551U R11 RES 1.00kΩ 1/16W 1% 0603 SMD Panasonic ERJ-3EKF1001V R12 RES 1.00Ω 1/10W 1% 0603 SMD Yageo RC0603FR-071RL R4, R13, R14, R15, R16, R17 RES 10.0Ω 1/10W 1% 0603 SMD Panasonic ERJ-3EKF10R0V TP3, TP5, TP14, TP21, TP24 TEST POINT PC Mill-max 3132-0-00-15-00-00-08-0 U1 Ultrasound Pulser Supertex Inc. HV738K6-G Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2014 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSDB-HV738DB1 B070114 10 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com