Power-Factor Controller (PFC) IC for High Power Factor and Active Harmonic Filter TDA 4862 Advanced Information Bipolar IC Features • IC for sinusoidal line-current consumption • Power factor approaching 1 • Controls boost converter as an active harmonics filter • Internal start-up with low current consumption • Zero current detector for discontinuous operation mode • High current totem pole gate driver • Trimmed ± 1.4% internal reference • Undervoltage lock-out with hysteresis • Very low start-up current consumption • Pin compatible to world standard • Fast overvoltage regulator • Current sense input with internal low pass filter P-DIP-8-1 P-DSO-8-1 Type Ordering Code Package ▼ TDA 4862 Q67000-A8368-A205 P-DIP-8-1 ▼ TDA 4862 G Q67006-A8369-A703 P-DSO-8-1 ▼ = New type Semiconductor Group 1 1998-02-16 TDA 4862 Description The TDA 4862 is excellent convenient for designing a preconverter in ballasts and switched mode power supplies with sinusoidal line current consumption and a power factor approaching unity. The TDA 4862 controls a boost converter as an active harmonics filter in a discontinuous mode (free oscillating triangular shaped current mode). The TDA 4862 comprises an internal start-up timer, a high gain voltage amplifier, an one quadrant multiplier for approaching unity power factor, a zero current detector, PWM and logic circuitry, and totem pole MOSFET gate driver. Protective features are: input undervoltage lockout with hysteresis, VCC zener clamp, cycle-by-cycle current limiting, output voltage limiting for fast and slow load changes up to open circuit, and a sinking gate driver current activated whenever undervoltage mode occurs. The output voltage of this preconverter is regulated with high accuracy. Therefore the device can be used for world-wide line voltages without switches. The TDA 4862 is the improved version of the TDA 4817 with a pinout equivalent to world standard. TDA 4862 G TDA 4862 V SENSE 1 8 V CC V AOUT 2 7 GTDRV MULTIN 3 6 GND Ι SENSE 4 5 DETIN IEP01748 V SENSE 1 8 V CC V AOUT 2 7 GTDRV MULTIN 3 6 GND Ι SENSE 4 5 DETIN IEP01749 Figure 1 Pin Configuration (top view) Semiconductor Group 2 1998-02-16 TDA 4862 Pin Definitions and Functions Pin Symbol Function 1 VSENSE Voltage Amplifier Inverting Input; VSENSE is connected via a resistive divider to the boost converter output. With a capacitor connected to VAOUT it forms an integrator. 2 VAOUT Voltage Amplifier Output; VAOUT is connected internally to the first multiplier input. To prevent overshoot the input voltage will be clamped at 5 V. Input voltage less than 2.2 V is inhibiting the gate driver. If the current flowing into this pin is exceeding an internal defined margin the multiplier output voltage is reduced to prevent the MOSFET from overvoltage damage. 3 MULTIN Multiplier Input; MULTIN is the second multiplier input and connected via a resistive divider to the rectifier output voltage. 4 ISENSE Current Sense Minus; ISENSE is connected to a sense resistor controlling the MOSFET source current. The input is internally clamped at – 0.3 V to prevent negative input voltage interaction. An internal low pass filter suppresses voltage spikes when turning the MOSFET on. 5 DETIN Zero Current Detector Input; DETIN is connected to an auxiliary winding monitoring the zero crossing of the inductor current. 6 GND Ground; All voltages are measured with respect to GND. VCC should be bypassed directly to GND with a 0.1 µF or larger ceramic capacitor. 7 GTDRV Gate Drive Output; GTDRV is the output of a totem-pole circuitry for direct driving a MOSFET. A clamping network bypasses low state source current and high state sink current. 8 VCC Positive Supply Voltage; VCC should be connected to a stable source slightly above the VCC turn-ON threshold for normal operation. A 100 nF or lager ceramic capacitor connected to VCC absorbs supply current spikes required to charge external MOSFET gate capacitances. Semiconductor Group 3 1998-02-16 TDA 4862 Functional Description Introduction Conventional electronic ballasts and switching power supplies are designed with a bridge rectifier and bulk capacitor. Their disadvantage is that the circuit draws power from the line when the instantaneous AC voltage exceeds the capacitor’s voltage. This occurs near the line voltage peak and causes a high charge current spike with following characteristics: the apparent power is higher than the real power that means low power factor condition, the current spikes are non-sinusoidal with a high content of harmonics causing line noise, the rectified voltage depends on load condition and requires a large bulk capacitor, special efforts in noise suppression are necessary. With the TDA 4862 preconverter a sinusoidal current is achieved which varies in direct instantaneous proportion to the input voltage half sine wave and means a power factor near 1. This is due to the appearance of almost any complex load like a resistive one at the AC line. The harmonic distortions are reduced and comply with the IEC555 standard. Operating Description The TDA 4862 contains a wide bandwidth voltage amplifier used in a feedback loop, an overvoltage regulator, an one quadrant multiplier with a wide linear operating range, a current sense comparator, zero current detector, a PWM and logic circuitry, a totem-pole MOSFET driver, an internal trimmed voltage reference, a restart timer and an undervoltage lockout circuitry. These functional blocks are described below. Voltage Amplifier The voltage amplifier is internally compensated and yields a gain bandwidth of 0.8 MHz and a phase margin of 80 degrees. The non-inverting input is biased at 2.5 V and is not pinned out. The inverting input is sensing the output voltage via a resitive devider. The voltage amplifier output VAOUT and the inverting input VSENSE are connected in a simplest way via an external capacitor. It forms an integrator which monitors the average output voltage over several line cycles. Typically the bandwidth is set below 20 Hz. ln order to keep the output voltage constant the voltage amplifier output is connected to the multiplier input for regulation. Overvoltage Regulator Fast changes of the output voltage can’t be regulated by the integrator formed with the voltage amplifier This occurs during initial start-up, sudden load removal, or output arcing and leads to a current peak at the voltage amplifier input while the voltage amplifier’s differential input voltages remains zero. The peak current is flowing through the external capacitor into VAOUT. Exceeding an internal defined margin causes a regulation circuitry to reduce the multiplier output voltage. Semiconductor Group 4 1998-02-16 TDA 4862 Functional Description (cont’d) MuItiplier A one quadrant multiplier is the crucial circuitry that regulates the gate driver with respect of the DC output voltage and the AC haversine input voltage of the preregulator. Both inputs are designed for good linearity over a wide dynamic range, 0 V to 4.0 V for the MULTIN and 2.5 V to 4.0 V for the VAOUT. Current Sense Comparator and RS Latch The multiplier output voltage is compared with the current sense voltage which represents the current through the MOSFET. The current sense comparator in addition with the logic ensures that only a single pulse appears at the drive output during a given cycle. The multiplier output and the current sense threshold are internally clamped at 1.3 V. So the gate drive MOSFET is protected against critical operating, as they occur during start up. To prevent the input from negative pulses a special protection circuitry is implemented. Switch-on current peaks are reduced by an internal RC-Filter. Zero Current Detector The zero current detector senses the inductor current via an auxiliary winding and ensures that the next on-time is initiated immediately when the inductor current has reached zero. This diminishes the reverse recovery losses of the boost converter diode. Output switch conduction is terminated when the voltage drop of the shunt resistor reaches the threshold level of the multiplier output. So the boost current waveform has a triangular shape and there are no deadtime gaps between the cycles. This leads to a continuous AC line current limiting the peak current to twice of the average current. To prevent false tripping the zero current detector is designed as a Schmitt trigger with a hysteresis of 0.6 V. An internal 5 V clamp protects the input from overvoltage breakdown, a 0.6 V clamp prevents substrate injection. An external resistor must be used in series with the auxiliary winding to limit the current through the clamps. Timer A restart timer function was added to the IC to eliminate the need for an oscillator when used in stand-alone applications. The timer starts or restarts the TDA 4862 if the drive output has been off for more than 15 µs after the inductor current reaches zero. Semiconductor Group 5 1998-02-16 TDA 4862 Functional Description (cont’d) Undervoltage Lockout An undervoltage lockout circuitry enables the output stage when VCC reaches the upper threshold VCC and terminates the output stage when VCC is falling below the lower threshold VCCL. In the standby mode the supply current is typically 75 µA. An internal clamp has been added from VCC to ground to protect the IC from an overvoltage condition. The external circuitry is created with a start-up resistor connected from VCC to the input supply voltage and a storage capacitor from VCC to ground. Bootstrap power supply is created with the previous mentioned auxiliary winding and a diode. Output The TDA 4862 totem pole output stage is MOSFET compatible. An internal protection circuitry is activated when VCC is within the stand by mode and ensures that the MOSFET is turned-OFF. The totem pole output has been optimized to minimize cross conduction current during high speed operation. The addition of two 4 Ω resistors, one in series with the source output transistor and one in series with the sink output transistor, reduces the cross conduction current. Semiconductor Group 6 1998-02-16 Figure 2 Block Diagram Semiconductor Group Undervoltage Lockout OverVoltage Regulation Voltage Amplifier 1 V CC Reference Voltage 11 V / 8.5 V V SENSE V REF + Clamp 2 1.3 V V AOUT Clamp 4V 0.9 V Multiplier 8 V CC Current Comp + 7 3 Driver and Logic 7 GTDRV MULTIN 30 k Ω Filter Ι SENSE 6 10 pF TDA 4862; G GND 4 Clamp 5V 0.6 V 5 DETIN V CCZ-Clamp 1998-02-16 IEB01747 TDA 4862 2.5 V / 1.9 V Detector Figure 3 8 Application Circuit with TDA 4862; G Semiconductor Group V IN AC 90-270 V RF-Filter and Rectifier C1 0.22 µF R1 1.3 M Ω C4 100 nF BYP 101 250 µH Tr1 D1 R8 1N4148 100 Ω R3 100 k Ω C3 100 µF V OUT C5 470 µF D2 400 V R3 22 k Ω DETIN 5 8 Detector + V TH Multipler Q1 Current OP MULTIN 3 PWM Logic Driver 7 GTDRV BUZ 334 + Voltage OP R2 12 k Ω GND + 6 V Ref TDA 4862 G 1 V SENSE R7 0.1 Ω 2 R6 10 k Ω C6 1998-02-16 470 nF IES01750 TDA 4862 V AOUT R5 1.6 M Ω 4 Ι SENSE TDA 4862 Absolute Maximum Ratings Parameter Supply voltage at supply + Z-current Symbol Limit Values Unit VCC Pin 8 VCC VCC-GND Pin 8 ICCZ Current into GTDRV Clamping current into GTDRV Clamping current into GTDRV Pin 7 IGTDRV Pin 7 IGTDCH Pin 7 IGTDCL max. – 0.3 0 – 70 – 400 500 100 – – 100 – V mA – observe Pmax mA mA mA observe Pmax VGTDRV > VCC VGTDRV < – 0.3 V – – – – – 0.3 – 0.3 – 0.3 – 10 – – 10 17 6 17 17 50 – V V V V mA mA VDETIN > 6 V VDETIN < 0.9 V – 40 150 °C – Storage temperature VVSENSE VVAOUT VMULTIN VISENSE IDETINH IDETINL Tj Tstg – 50 150 °C – Thermal resistance system-air TDA 4862 TDA 4862 G RthSA RthSA – – 100 180 K/W K/W P-DIP-8-1 P-DSO-8-1 Voltage at Voltage at Voltage at Voltage at Current into Current into VSENSE VAOUT min. Notes Pin 1 Pin 2 MULTIN Pin 3 ISENSE Pin 4 DETIN Pin 5 DETIN Pin 5 Junction temperature Operating Range Parameter Symbol Limit Values Unit min. Supply voltage Z-current Junction temperature Voltage at ISENSE 1) VCC IZ Tj VISENSE Notes max. VCCON VZ V 1) 0 50 mA observe Pmax – 40 150 °C – –5 VZ V – VCCON means VCCH has been exceeded but the supply voltage is still above VCCL. The device has switched from standby to active. For VCCH and VCCL values see Electrical Characteristics. If 0 V < VCC < VCCON, the device is in standby and output GTDRV is active low. Semiconductor Group 9 1998-02-16 TDA 4862 Electrical Characteristics Unless otherwise stated, VCC = 12 V, – 40 °C < Tj < 150 °C. Parameter Symbol Limit Values Unit Test Condition min. typ. max. ICCL Supply current, ON ICCH Supply current, dynamic ICCDY – 75 200 µA 0 V < VCC < VCCH – 4 6 mA Output low – 4.2 8 mA fDETIN = 50 kHz, CGTDRV = 1 nF VCC turn-ON threshold VCC turn-OFF threshold VCC turn-ON/OFF VCCH VCCL VCCHY – 11 11.5 V – 8.0 8.5 – V – 1.8 2.3 3.0 V – VZ 15 17 19 V ICCZ = 50 mA Voltage feedback threshold VFB 2.465 2.5 2.53 5 V Tj = 25 °C, Voltage feedback threshold VFB 2.45 – 2.55 V Pin 1 to Pin 2 Line regulation ∆VFBL – – 5 mV VCC = 10 V to 15 V Input bias current –1 – – µA – – 80 – dB – Unity gain bandwidth1) IBVSENSE GV BW – 0.8 – MHz – Phase margin1) ΦM – 80 – Degr – Inhibit threshold voltage VVAOUTI – 2.2 – V – Output current source IVAOUTH – – 12 – mA Output current sink IVAOUTL – 4 – mA VVAOUT = 0 V, VVSENSE = 2.3 V VVAOUT = 4 V, VVSENSE = 2.8 V Overall Supply current, OFF hysteresis VCC clamp Voltage Amplifier Open loop voltage gain1) 1) Pin 1 to Pin 2 Guaranteed by design, not 100 % tested in production. Semiconductor Group 10 1998-02-16 TDA 4862 Electrical Characteristics (cont’d) Unless otherwise stated, VCC = 12 V, – 40 °C < Tj < 150 °C. Parameter Symbol Limit Values Unit Test Condition min. typ. max. Output voltage swing high state VVAOUTH 3.8 4.3 5.0 V Output voltage swing low state VVAOUTL – 0.9 – V IRVAOUT 20 30 45 µA IVAOUT = – 0.2 mA VVSENSE = 2.3 V IVAOUT = 0.5 A VVSENSE = 2.8 V Overvoltage Regulator Regulation current VVAOUT = VMULTIN = 4 V, VISENSE = 0.5 V Current Comparator Input bias current Input offset voltage Max threshold voltage Delay to output1) IBISENSE – 1 VISENSEO – – – µA – 25 – mV VMULTIN = 0 V, VVAOUT = 2.4 V VISENSEM 1.05 tPHL – 1.25 1.5 V – 250 – ns – Detector Upper threshold voltage VDETINU (VDETIN increasing) – 2.5 2.75 V – Lower threshold voltage VDETINL (VDETIN decreasing) 1.5 1.9 – V – 0.6 – V – Input current VDETINHY – IBDETIN –1 – – µA 1.5 V < VDETIN < 2.75 V Input clamp voltage High state Low state VDETINHC 4 VDETINLC – 5 0.6 – 1 V V IDETIN = 5 mA IDETIN = – 5 mA Hysteresis 1) Guaranteed by design, not 100 % tested in production. Semiconductor Group 11 1998-02-16 TDA 4862 Electrical Characteristics (cont’d) Unless otherwise stated, VCC = 12 V, – 40 °C < Tj < 150 °C. Parameter Symbol Limit Values Unit Test Condition min. typ. max. IBMULTIN –1 – – VAOUT VMULTIN VVAOUT Multiplier gain 1) Multiplier µA – 0 to 3 0 to 4 – VFB to VFB to – VFB + 1 VFB + 1.5 V V VVAOUT = 2.75 V VMULTIN = 1.0 V K 0.45 0.65 0.85 1/V VMULTIN = 2 V VVAOUT = VFB + 1 V tDLY 75 190 400 µs – Output voltage low state VGTDRVL – 0.8 1.8 – V V Output voltage high state VGTDRVH – 9.4 8.7 – V Output voltage active shut down VGTDRVU – 2.0 2.6 V Rise time 2) tr tf – 100 – – – 40 – – IGTDRV = 20 mA IGTDRV = 200 mA IGTDRV = – 20 mA IGTDRV = – 200 mA IGTDRV = 50 mA VCC increasing: 0 < VCC < VCCH, VCC decreasing: 0 < VCC < VCCL CGTDRV = 1 nF CGTDRV = 1 nF Input bias current Dynamic voltage range MULTIN Restart Timer Restart time delay Gate Driver Fall time 2) 1) K = VISENSE / (VMULTIN × (VVAOUT – VFB)) 2) Guaranted by design, not 100% tested in production. Semiconductor Group 12 1998-02-16 TDA 4862 Supply Current ICC versus Supply Voltage VCC IED01751 6 Ι CC Supply Current ICC versus Junction Temperature Tj mA Ι CC 5 4 4 3 2 =3V =3V =1V = 0.5 V =2V = 25 C =3V =3V =1V = 0.5 V =2V 2 1 0 -50 0 0 V VSENSE V VAOUT V MULTIN V ISENSE V DETIN 3 1 5 10 15 V V CC 20 IED01753 12 0 50 100 C 150 Tj Open Loop Gain GV and Phase Φ versus Frequency f Turn-ON/-OFF Threshold Voltage VCC versus Junction Temperature Tj V CC mA 5 V VSENSE V VAOUT V MULTIN V ISENSE V DETIN Tj IED01752 6 IED01754 100 V V CC = 12 V 3.0 < V VAOUT < 3.5 V T j = 25 C dB V CCH GV 11 80 0 deg 30 Φ A0 10 60 9 40 60 Φ V CCL 20 8 7 -50 0 50 Semiconductor Group 0 10 -2 10 -1 10 0 10 1 10 2 100 C 150 Tj 13 90 ΦM 120 150 kHz 10 f 4 1998-02-16 TDA 4862 Threshold Voltage Change ∆VFB versus Junction Temperature Tj ∆V FB Threshold Voltage VISENSE versus Regulation Current IRVAOUT IED01755 10 mV IED01756 1.4 V CC =12 V V ISENSE V CC = 12 V Pin 1 connected to Pin 2 V 5 1.0 0 -40 C 0.8 25 C 0.6 -5 150 C 0.4 -10 0.2 -15 -50 0 50 0 29 100 C 150 Tj Threshold Voltage VDETIN versus Junction Temperature Tj 30 31 32 33 µ A 34 Ι RVAOUT Current Sense Threshold VISENSE versus Multiplier Input VMULTIN IED01757 3.00 IED01758 1.4 4.0 V V ISENSE 1/V V DETIN V CC = 12 V V MULTIN = 1 V V VSENSE = GND V ISENSE = GND 2.75 V 3.5 V 1.0 2.50 3.0 V V DETINupper 0.8 2.25 0.6 2.75 V 2.00 0.4 V DETINlow 1.75 0.2 V VAOUT = 2.5 V 0 -50 0 Semiconductor Group 50 0 100 C 150 Tj 0 1 2 3 4 V 5 V MULTIN 14 1998-02-16 TDA 4862 Current Sense Threshold VISENSE versus Voltage Amplifier Output VVAOUT Multiplier Gain K versus Junction Temperature Tj IED01759 1.4 V MULTIN = 3 V V ISENSE IED01760 1.2 K V 2V = 12 V =2V = VFB + 1 V V CC V MULTIN V VAOUT 1/V 0.9 1.0 1V 0.8 0.6 0.6 0.5 V 0.4 0.3 0.2 0 2.5 3.0 4.0 3.5 0 -50 4.5 V 5.0 V VAOUT Restart Time Delay tDLY versus Junction Temperature Tj 50 100 C 150 Tj Output Voltage Low/High State VSAT versus Load Current IGTDRV IED01761 240 µs 0 IED01762 6 t DLY V SAT VCC = 12 V T = 10 ms t p = 200 µ s V 5 220 VCC VGTDRVH 4 VGTDRVL at VCC = 7 V 200 3 180 2 VGTDRVL 160 140 -50 1 0 0 Semiconductor Group 50 100 C 150 Tj 0 100 200 300 mA 400 Ι GTDRV 15 1998-02-16 TDA 4862 Package Outlines GPD05025 Plastic Package, P-DIP-8-1 (Plastic Dual In-line Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. Dimensions in mm Semiconductor Group 16 1998-02-16 TDA 4862 GPS05121 Plastic Package, P-DSO-8-1 (Plastic Dual Small Outline Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 17 Dimensions in mm 1998-02-16