UC1855A/B UC2855A/B UC3855A/B High Performance Power Factor Preregulator FEATURES DESCRIPTION • Controls Boost PWM to Near Unity Power Factor The UC1855A/B provides all the control features necessary for high power, high frequency PFC boost converters. The average current mode control method allows for stable, low distortion AC line current programming without the need for slope compensation. In addition, the UC1855 utilizes an active snubbing or ZVT (Zero Voltage Transition technique) to dramatically reduce diode recovery and MOSFET turn-on losses, resulting in lower EMI emissions and higher efficiency. Boost converter switching frequencies up to 500kHz are now realizable, requiring only an additional small MOSFET, diode, and inductor to resonantly soft switch the boost diode and switch. Average current sensing can be employed using a simple resistive shunt or a current sense transformer. Using the current sense transformer method, the internal current synthesizer circuit buffers the inductor current during the switch on-time, and reconstructs the inductor current during the switch off-time. Improved signal to noise ratio and negligible current sensing losses make this an attractive solution for higher power applications. • Fixed Frequency Average Current Mode Control Minimizes Line Current Distortion • Built-in Active Snubber (ZVT) allows Operation to 500kHz, improved EMI and Efficiency • Inductor Current Synthesizer allows Single Current Transformer Current Sense for Improved Efficiency and Noise Margin • Accurate Analog Multiplier with Line Compensator allows for Universal Input Voltage Operation • High Bandwidth (5MHz), Low Offset Current Amplifier • Overvoltage and Overcurrent protection • Two UVLO Threshold Options • 150µA Startup Supply Current Typical • Precision 1% 7.5V Reference The UC1855A/B also features a single quadrant multiplier, squarer, and divider circuit which provides the programming signal for the current loop. The internal multiplier current limit reduces output power during low line conditions. An overvoltage protection circuit disables both controller outputs in the event of a boost output OV condition. Low startup supply current, UVLO with hysteresis, a 1% 7.5V reference, voltage amplifier with softstart, input supply voltage clamp, enable comparator, and overcurrent comparator complete the list of features. Available packages include: 20 pin N, DW, Q, J, and L. BLOCK DIAGRAM License Patent from Pioneer Magnetics. Pin numbers refer to DIL-20 J or N packages. 6/98 UDG-94001-2 UC1855A/B UC2855A/B UC3855A/B CONNECTION DIAGRAMS ABSOLUTE MAXIMUM RATINGS Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . Internally Limited VCC Supply Clamp Current . . . . . . . . . . . . . . . . . . . . . . . 20mA PFC Gate Driver Current (continuous) . . . . . . . . . . . . . . ± 0.5A PFC Gate Driver Current (peak) . . . . . . . . . . . . . . . . . . . ± 1.5A ZVT Drive Current (continuous) . . . . . . . . . . . . . . . . . . . ± 0.25A ZVT Drive Current (peak) . . . . . . . . . . . . . . . . . . . . . . . ± 0.75A Input Current (IAC, RT, RVA) . . . . . . . . . . . . . . . . . . . . . . . 5mA Analog Inputs (except Peak Limit) . . . . . . . . . . . . . . −0.3 to 10V Peak Limit Input . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 to 6.5V Softstart Sinking Current . . . . . . . . . . . . . . . . . . . . . . . . . 1.5mA Storage Temperature . . . . . . . . . . . . . . . . . . . −65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . −55°C to +150°C Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C PLCC-20 & LCC-20 (Top View) Q or L Package Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. All voltages are referenced to GND. DIL–20 (Top View) J or N Package SOIC-20 (Top View) DW Package ELECTRICAL CHARACTERISTICS: Unless otherwise specified: VCC = 18V, RT = 15k, RVS = 23k, CT = 470pF, CI = 150pF, VRMS = 1.5V, IAC = 100µA, ISENSE = 0V, CAOUT = 4V, VAOUT= 3.5V, VSENSE = 3V. TA = TJ. TA = –55°C to 125°C (UC1855A/B), –40°C to 85°C (UC2855A/B), 0°C to 70°C (UC3855A/B). PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Overall CAO, VAOUT = 0V, VCC = UVLO −0.3V 150 VCC Turn-On Threshold UC1855A VCCTurn-Off Threshold UC1855A,B VCC Turn-On Threshold UC1855B VCC Clamp I(VCC) = ICC(on) + 5mA Supply Current, OFF Supply Current, OPERATING 9 500 µA 17 25 mA 15.5 17.5 V 10 V 10.5 10.8 V 20 22 V 3.1 V −500 25 500 nA 18 Voltage Amplifier Input Voltage 2.9 VSENSE Bias Current Open Loop Gain VOUT = 2 to 5V 65 80 VOUT High ILOAD = –300µA 5.75 6 6.25 V VOUT Low ILOAD = 300µA 0.3 0.5 V Output Short Circuit Current VOUT = 0V 0.6 3 mA 2 dB UC1855A/B UC2855A/B UC3855A/B ELECTRICAL CHARACTERISTICS: Unless otherwise specified: VCC = 18V, RT = 15k, RVS = 23k, CT = 470pF, CI = 150pF, VRMS = 1.5V, IAC = 100µA, ISENSE = 0V, CAOUT = 4V, VAOUT= 3.5V, VSENSE = 3V. TA = TJ. TA = –55°C to 125°C (UC1855A/B), –40°C to 85°C (UC2855A/B), 0°C to 70°C (UC3855A/B). PARAMETER Current Amplifier Input Offset Voltage Input Bias Current (Sense) Open Loop Gain VOUT High VOUT Low Output Short Circuit Current Common Mode Range Gain Bandwidth Product Reference Output Voltage Load Regulation Line Regulation Short Circuit Current Oscillator Initial Accuracy Voltage Stability Total Variation Ramp Amplitude (P–P) Ramp Valley Voltage Enable/OVP/Current Limit Enable Threshold OVP Threshold OVP Hysteresis OVP Propagation Delay OVP Input Bias Current PKLIMIT Threshold PKLIMIT Input Current PKLIMIT Prop. Delay Multiplier Output Current - IAC Limited Output Current - Zero Output Current - Power Limited Output Current Gain Constant Gate Driver Output Output High Voltage Output Low Voltage Output Low Voltage Output Low (UVLO) Output RISE/FALL Time Output Peak Current TEST CONDITIONS VCM = − 2.5V VCM = 2.5V VCM = 2.5V, VOUT = 2 to 6V ILOAD = −500µA ILOAD = 500µA VOUT = 0V MIN −4 −500 80 TYP 4 500 110 6 0.3 1 FIN = 100kHz, 10mV, P–P, TA = 25°C −0.3 2.5 IREF = 0mA, TA = 25°C IREF = 0mA IREF = 1 to 10 mA VCC = 15 to 35V REF = 0V 7.388 7.313 −15 −10 20 7.5 7.5 170 200 1 TA = 25°C VCC = 12 to 18V Line, Temp. V= 7.5V 1.25 VPKLIMIT = 1.5V IAC = 100µA, VRMS = 1V IAC = 0µA VRMS = 1.5V, VAOUT = 5.5V VRMS = 1.5V, VAOUT = 2V VRMS = 1.5V VAOUT = 5V VRMS = 5V, VAOUT = 2V VRMS = 5V, VAOUT = 5V Refer to Note 1 lOUT = −200mA, VCC = 15V lOUT = 200mA lOUT = 10mA lOUT = 50mA, VCC = 0V CLOAD = 1nF CLOAD = 10nF 3 −235 −2 −250 −0.95 12 0.5 3 5 5 45 160 4.9 1.1 200 MAX UNITS mV nA dB V V mA V MHz 7.613 7.688 15 10 65 V V mV mV mA 230 kHz % kHz V V 240 5.9 1.6 1.8 7.5 400 200 1 1.5 100 100 2.2 7.66 600 −205 −0.2 −209 −26 −190 −3 −17 −0.85 −175 2 −160 −0.75 µA µA µA µA µA µA µA 1/V 12.8 1 300 2.2 500 V V mV 0.9 35 1.5 10 1.75 1.5 V V mV ns µA V µA ns V ns A UC1855A/B UC2855A/B UC3855A/B ELECTRICAL CHARACTERISTICS: Unless otherwise specified: VCC = 18V, RT = 15k, RVS = 23k, CT = 470pF, CI = 150pF, VRMS = 1.5V, IAC = 100µA, ISENSE = 0V, CAOUT = 4V, VAOUT= 3.5V, VSENSE = 3V. TA = TJ. TA = –55°C to 125°C (UC1855A/B), –40°C to 85°C (UC2855A/B), 0°C to 70°C (UC3855A/B). PARAMETER TEST CONDITIONS MIN TYP MAX UNITS ZVT Reset Threshold 2.3 2.6 2.9 V 6 20 µA Input Bias Current V = 2.5V, VCT = 0 Propagation Delay Measured at ZVTOUT 100 ns Maximum Pulse Width 400 ns 12 12.8 V Output High Voltage lOUT = −100mA, VCC = 15V 1 2.2 V Output Low Voltage lOUT = 100mA 300 900 mV lOUT = 10mA Output Low (UVLO) lOUT = 50mA, VCC = 0V 0.9 1.5 V 35 ns Output RISE/FALL Time CLOAD = 1nF 0.75 A Output Peak Current CLOAD = 10nF Current Synthesizer VION = 0V 30 50 mV ION to CS Offset Cl Discharge Current IAC = 50µA 105 118 140 µA IAC = 500µA 5 µA IAC Offset Voltage 0.3 0.65 1.1 V ION Buffer Slew Rate 10 V/µs 2 15 µA ION Input Bias Current VION = 2V RVS Output Voltage 23k from RVS to GND 2.87 3 3.13 V Note 1: Gain constant (K) = IAC •(VAOUT 1. 5V ) at V = 1.5V, VA = 5.5V. RMS OUT 2 (VRMS • IMO ) PIN DESCRIPTIONS CS: The reconstructed inductor current waveform generated on the CI pin is level shifted down a diode drop to this pin. Connect the current amplifier input resistor between CS and the inverting input of the current amplifier. The waveform on this pin is compared to the multiplier output waveform through the average current sensing current amplifier. The input to the peak current limiting comparator is also connected to this pin. A voltage level greater than 1.5 volts on this pin will trip the comparator and disable the gate driver output. CA−: This is the inverting input to the current amplifier. Connect the required compensation components between this pin and CAOUT. The common mode operating range for this input is between −0.3V and 5V. CAO: This is the output of the wide bandwidth current amplifier and one of the inputs to the PWM duty cycle comparator. The output signal generated by this amplifier commands the PWM to force the correct input current. The output can swing from 0.1V to 7.5V. CT: A capacitor from CT to GND sets the PWM oscillator frequency according to the following equation: CI: The level shifted current sense signal is impressed upon a capacitor connected between this pin and GND. The buffered current sense transformer signal charges the capacitor when the boost switch is on. When the switch is off, the current synthesizer discharges the capacitor at a rate proportional to the dI/dt of the boost inductor current. In this way, the discharge current is approximately equal to f≈ 1 . 11200 • CT Use a high quality ceramic capacitor with low ESL and ESR for best results. A minimum CT value of 200pF insures good accuracy and less susceptibility to circuit layout parasitics. The oscillator and PWM are designed to provide practical operation to 500kHz. 3V IAC . – RRVS 4 Discharging the CI capacitor in this fashion, a “reconstructed” version of the inductor current is generated using only one current sense transformer. GND: All voltages are measured with respect to this pin. All bypass and timing capacitors connected to GND should have leads as short and direct as possible. 4 UC1855A/B UC2855A/B UC3855A/B PIN DESCRIPTIONS (cont.) REF: REF is the output of the precision reference. The output is capable of supplying 25mA to peripheral circuitry and is internally short circuit current limited. REF is disabled and low whenever VCC is below the UVLO threshold, and when OVP is below 1.8V. A REF “GOOD” comparator senses REF and disables the stage until REF has attained approximately 90% of its nominal value. Bypass REF to GND with a 0.1µF or larger ceramic capacitor for best stability. GTOUT: The output of the PWM is a 1.5A peak totem pole MOSFET gate driver on GTOUT. A series resistor between GTOUT and the MOSFET gate of at least 10 ohms should be used to limit the overshoot on GTOUT. In addition, a low VF Schottky diode should be connected between GTOUT and GND to limit undershoot and possible erratic operation. IAC: This is a current input to the multiplier. The current into this pin should correspond to the instantaneous value of the rectified AC input line voltage. This is accomplished by connecting a resistor directly between IAC and the rectified input line voltage. The nominal 650mV level present on IAC negates the need for any additional compensating resistors to accommodate for the zero crossings of the line. A current equal to one fourth of the IAC current forms one of the inductor current synthesizer inputs. RVS: The nominal 3V signal present on the VSENSE pin is buffered and brought out to the RVS pin. A current proportional to the output voltage is generated by connecting a resistor between this pin and GND. This current forms the second input to the current synthesizer. VAO: This is the output of the voltage amplifier. At a given input RMS voltage, the voltage on this pin will vary directly with the output load. The output swing is limited from approximately 100mV to 6V. Voltage levels below 1.5V on this pin will inhibit the multiplier output. IMO: This is the output of the multiplier, and the noninverting input of the current amplifier. Since this output is a current, connect a resistor between this pin and ground equal in value to the input resistor of the current amplifier. The common mode operating range for this pin is −0.3V to 5V. VCC: Positive supply rail for the IC. Bypass this pin to GND with a 1µF low ESL, ESR ceramic capacitor. This pin is internally clamped to 20V. Current into this clamp should be limited to less than 10mA. The UC1855A has a 15.5V (nominal) turn on threshold with 6 volts of hysteresis while the UC1855B turns on at 10.5V with 500mV of hysteresis. ION: This pin is the current sensing input. It should be connected to the secondary side output of a current sensing transformer whose primary winding is in series with the boost switch. The resultant signal applied to this input is buffered and level shifted up a diode to the CI capacitor on the CI pin. The ION buffer has a source only output. Discharge of the CI cap is enabled through the current synthesizer circuitry. The current sense transformer termination resistor should be designed to obtain a 1V input signal amplitude at peak switch current. VRMS: This pin is the feedforward line voltage compensation input to the multiplier. A voltage on VRMS proportional to the AC input RMS voltage commands the multiplier to alter the current command signal by 2 1/VRMS to maintain a constant power balance. The input to VRMS is generally derived from a two pole low pass filter/voltage divider connected to the rectified AC input voltage. This feature allows universal input supply voltage operation and faster response to input line fluctuations for the PFC boost preregulator. For most designs, a voltage level of 1.5V on this pin should correspond to low line, and 4.7V for high line. The input range for this pin extends from 0 to 5.5V. OVP: This pin senses the boost output voltage through a voltage divider. The enable comparator input is TTL compatible and can be used as a remote shutdown port. A voltage level below 1.8V, disables VREF, oscillator, and the PWM circuitry via the enable comparator. Between 1.8V and VREF (7.5V) the UC1855 is enabled. Voltage levels above 7.5V will set the PWM latch via the hysteretic OVP comparator and disable both ZVTOUT and GTOUT until the OVP level has decayed by the nominal hysteresis of 400mV. If the voltage divider is designed to initiate an OVP fault at 5% of OV, the internal hysteresis enables normal operation again when the output voltage has reached its nominal regulation level. Both the OVP and enable comparators have direct logical connections to the PWM output and exhibit typical propagation delays of 200ns. VSENSE: This pin is the inverting input of the voltage amplifier and serves as the output voltage feedback point for the PFC boost converter. It senses the output voltage through a voltage divider which produces a nominal 3V. The voltage loop compensation is normally connected between this pin and VAO. The VSENSE pin must be above 1.5V at 25°C, (1.9V at –55°C) for the current synthesizer to work properly. 5 UC1855A/B UC2855A/B UC3855A/B PIN DESCRIPTIONS (cont.) ZVS: This pin senses when the drain voltage of the main MOSFET switch has reached approximately zero volts, and resets the ZVT latch via the ZVT comparator. A minimum and maximum ZVTOUT pulse width are programmable from this pin. To directly sense the ≈400V drain voltage of the main switch, a blocking diode is connected between ZVS and the high voltage drain. When the drain reaches 0V, the level on ZVS is ≈0.7V which is below the 2.6V ZVT comparator threshold. The maximum ZVTOUT pulse width is approximately equal to the oscillator blanking period time. ZVTOUT: The output of the ZVT block is a 750mA peak totem pole MOSFET gate driver on ZVTOUT. Since the ZVT MOSFET switch is typically 3X smaller than the main switch, less peak current is required from this output. Like GTOUT, a series gate resistor and Schottky diode to GND are recommended. This pin may also be used as a high current synchronization output driver. For more information see Unitrode Applications Note U-153. 5.992 496 516 MHz 120 Gain -90 100 120 Phase Phase Margin degrees -45 Phase 80 Gain (dB) Degrees 0 60 100 80 60 40 Open-Loop 40 20 Gain dB 0 20 0 -20 0.1 -20 1 10 100 1000 10000 Frequency kHz -40 -60 10kHz 1MHz 100kHz 10MHz log f Figure 1. Current Amplifier Frequency Response Figure 2. Voltage Amplifier Gain Phase vs Frequency 24 3.10 3.08 22 3.06 20 3.04 3.02 18 mA VOLTS 3.00 2.98 2.96 16 14 2.94 12 2.92 2.90 10 -60 -40 -20 0 20 40 60 80 100 120 140 -60 TEMPERATURE °C -40 -20 0 20 40 60 TEMPERATURE °C Figure 3. Voltage Amplifier Input Threshold Figure 4. Supply Current ON 6 80 100 120 140 UC1855A/B UC2855A/B UC3855A/B 230 -0.75 225 -0.77 220 -0.79 215 210 -0.83 205 -0.85 200 kHz GAIN CONSTANT (K) -0.81 -0.87 195 190 -0.89 185 -0.91 180 -0.93 175 -0.95 170 -60 -40 -20 0 20 40 60 80 100 120 140 -60 TEMPERATURE °C -40 -20 0 20 40 60 TEMPERATURE °C Figure 5. Multiplier Current Gain Constant Figure 6. Oscillator Initial Accuracy 7 80 100 120 140 UC1855A/B UC2855A/B UC3855A/B TYPICAL APPLICATION UDG-95165-1 Figure 7. Typical Application UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. 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