HV5122 / HV5222 32-Channel, Serial-to-Parallel Converter with Open-Drain Outputs Features Description • Processed with High Voltage CMOS technology • Output voltages to 225V using a ramped supply voltage • SINK current minimum 100mA • Shift register speed 8.0MHz • Strobe and enable inputs • CMOS compatible inputs • Forward and reverse shifting options HV5122 / HV5222 are low-voltage serial to high-voltage parallel converters with open-drain outputs. These devices are primarily designed for use as a driver for AC electroluminescent displays. HV5122 / HV5222 can also be used in any application requiring multiple highvoltage, current-sinking output capabilities such as driving inkjet and electrostatic print heads, plasma panels, vacuum fluorescent, or large matrix LCD displays. These devices consist of a 32-bit shift register and control logic to perform the Output Enable and all-on functions. Data is shifted through the shift register on the high-to-low transition of the clock. HV5122 shifts in the counter-clockwise direction when viewed from the top of the package and HV5222 shifts in the clockwise direction. For cascading devices, HV5122 / HV5222 provides a data output buffer that reflects he current status of the last bit of the shift register. Operation of the shift register is not affected by the OE (Output Enable) or the STR (Strobe) inputs. HV5122 / HV5222 are designed to be used in systems which either switch off the high voltage supply before changing the state of the high voltage outputs or which limit the current through each output. 2015 Microchip Technology Inc. DS20005418B-page 1 HV5122 / HV5222 Package Type 6 1 44 40 44 1 44-Lead PQFP 44-Lead PLCC See Table 2-1 for pin information Functional Block Diagram STR OE HVOUT1 DATA INPUT HVOUT2 • • • 28 Additional Outputs • • • CLK 32 bit Static Shift Register HVOUT31 HVOUT32 Data Out DS20005418B-page 2 2015 Microchip Technology Inc. HV5122 / HV5222 1.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS† Supply voltage, VDD ...................................................................................................................................-0.5V to +15V Supply voltage, VPP .................................................................................................................................-0.5V to +250V Logic input levels ............................................................................................................................... -0.5V to VDD+0.5V Ground current1 ....................................................................................................................................................... 1.5A Continuous total power dissipation2 .................................................................................................................. 1200mW Operating temperature range.................................................................................................................. -40°C to +85°C Storage temperature range ................................................................................................................... -65°C to +150°C † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 1: 2: Duty cycle is limited by the total power dissipated in the package. For operation above 25°C ambient derate linearly to maximum operating temperature at 20mW/°C. TABLE 1-1: ELECTRICAL CHARACTERISTICS Electrical Specifications: Over recommended conditions unless otherwise specified Symbol Parameter DC Characteristics IDD VDD supply current Quiescent VDD supply current IDDQ IO(OFF) IIH IIL VOH VOL Off-state output current High level logic input current Low level logic input current High level output data out Low level output voltage HVOUT Data out HVOUT clamp voltage VOC AC Characteristics (VDD = 12V, TA=25°C) fCLK Clock frequency tW Clock width, high or low tSU tH tON tDHL tDLH TABLE 1-2: Data setup time before CLK falls Data hold time after CLK falls Turn-on time, HVOUT from strobe Data output delay after H to L CLK Data output delay after L to H CLK Min Max Units Conditions - 15 mA - 100 µA - 10 1.0 -1.0 µA µA µA - V VDD 1.0V - 15 1.0 -1.5 V - 8.0 MHz 62 25 10 - 500 100 100 ns ns ns ns ns ns V fCLK= 8.0MHz, fDATA= 4.0MHz DIN= 0V, all input logic pins = 0V, all outputs off All outputs high, all switches parallel VIN= VDD VIL= 0 IDOUT= -100µA IHVOUT= +100mA IDOUT= +100µA IOL= -100mA RL= 2.0kΩ to 200V CL= 15pF CL= 15pF TYPICAL THERMAL RESISTANCE Package θja 44-Lead PQFP 51°C/W 44-Lead PLCC 37°C/W 2015 Microchip Technology Inc. DS20005418B-page 3 HV5122 / HV5222 2.0 PIN DESCRIPTION The locations of the pins are listed in Package Type. TABLE 2-1: Pin # PIN DESCRIPTION PQFP HV5122 HV5222 1 HVOUT11 HVOUT22 2 HVOUT12 HVOUT21 3 HVOUT13 HVOUT20 4 HVOUT14 HVOUT19 5 HVOUT15 HVOUT18 6 HVOUT16 HVOUT17 7 HVOUT17 HVOUT16 8 HVOUT18 HVOUT15 9 HVOUT19 HVOUT14 10 HVOUT20 HVOUT13 11 HVOUT21 HVOUT12 12 HVOUT22 HVOUT11 Description High voltage outputs. 13 HVOUT23 HVOUT10 14 HVOUT24 HVOUT9 15 HVOUT25 HVOUT8 16 HVOUT26 HVOUT7 17 HVOUT27 HVOUT6 18 HVOUT28 HVOUT5 19 HVOUT29 HVOUT4 20 HVOUT30 HVOUT3 21 HVOUT31 HVOUT2 22 HVOUT32 HVOUT1 23 DATA OUT DATA OUT N/C N/C No connect. Data output for cascading to the data input of the next device. 24 25 26 27 28 OE OE Output enable input. When OE is LOW, all HV outputs are forced into a LOW state, regardless of data in each channel. When OE is HIGH, all HV outputs reflect data latched. 29 CLK CLK Data shift register clock. Input are shifted into the shift register on the positive edge of the clock. 30 GND GND Logic and high voltage ground. 31 VDD VDD Low voltage logic power rail. 32 STR STR Strobe. 33 DATA IN DATA IN 34 N/C N/C DS20005418B-page 4 Serial data input. Data needs to be present before each rising edge of the clock. No connect. 2015 Microchip Technology Inc. HV5122 / HV5222 TABLE 2-1: PIN DESCRIPTION PQFP (CONTINUED) Pin # HV5122 HV5222 35 HVOUT1 HVOUT32 36 HVOUT2 HVOUT31 37 HVOUT3 HVOUT30 38 HVOUT4 HVOUT29 39 HVOUT5 HVOUT28 40 HVOUT6 HVOUT27 41 HVOUT7 HVOUT26 42 HVOUT8 HVOUT25 43 HVOUT9 HVOUT24 44 HVOUT10 HVOUT23 TABLE 2-2: Pin # Description High voltage outputs. PIN DESCRIPTION PLCC HV5122 HV5222 1 HVOUT16 HVOUT17 2 HVOUT17 HVOUT16 3 HVOUT18 HVOUT15 4 HVOUT19 HVOUT14 5 HVOUT20 HVOUT13 6 HVOUT21 HVOUT12 7 HVOUT22 HVOUT11 8 HVOUT23 HVOUT10 Description 9 HVOUT24 HVOUT9 10 HVOUT25 HVOUT8 11 HVOUT26 HVOUT7 12 HVOUT27 HVOUT6 13 HVOUT28 HVOUT5 14 HVOUT29 HVOUT4 15 HVOUT30 HVOUT3 16 HVOUT31 HVOUT2 17 HVOUT32 HVOUT1 18 DATA OUT DATA OUT N/C N/C No connect. High voltage outputs Data output for cascading to the data input of the next device. 19 20 21 22 23 OE OE Output enable input. When OE is LOW, all HV outputs are forced into a LOW state, regardless of data in each channel. When OE is HIGH, all HV outputs reflect data latched. 24 CLK CLK Data shift register clock. Input are shifted into the shift register on the positive edge of the clock. 25 GND GND Logic and high voltage ground. 26 VDD VDD Low voltage logic power rail. 27 STR STR Strobe. 2015 Microchip Technology Inc. DS20005418B-page 5 HV5122 / HV5222 TABLE 2-2: PIN DESCRIPTION PLCC (CONTINUED) Pin # HV5122 HV5222 28 DATA IN DATA IN 29 N/C N/C 30 HVOUT1 HVOUT32 31 HVOUT2 HVOUT31 32 HVOUT3 HVOUT30 33 HVOUT4 HVOUT29 34 HVOUT5 HVOUT28 35 HVOUT6 HVOUT27 36 HVOUT7 HVOUT26 37 HVOUT8 HVOUT25 38 HVOUT9 HVOUT24 39 HVOUT10 HVOUT23 40 HVOUT11 HVOUT22 41 HVOUT12 HVOUT21 42 HVOUT13 HVOUT20 43 HVOUT14 HVOUT19 44 HVOUT15 HVOUT18 DS20005418B-page 6 Description Serial data input. Data needs to be present before each rising edge of the clock. No connect. High voltage outputs. 2015 Microchip Technology Inc. HV5122 / HV5222 3.0 FUNCTIONAL DESCRIPTION Table 3-1 provides HV5122 / HV5222. TABLE 3-1: functional information about FUNCTIONAL TABLE Inputs Function Outputs Data In CLK OE All on X X X All off X X L Load S/R H/L ↓ L Output Enable X H/L H Shift Reg STR HV Outputs 1 Data Out 1 2...32 2...32 L ● ●...● ON ON...ON ● H ● ●...● OFF OFF...OFF ● H H/L Q1...Q31 OFF OFF...OFF Q32 H H/L ●...● ON/OFF ●...● ● Note 1: H = high level, L = low level, X = irrelevant, ↓ = high-to-low transition 2: ●= dependent on previous stage’s state before the last CLK high-to-low transition 3.1 Power-Up and Recommended Operating Conditions To power-up HV5122 / HV5222, perform the following power-up sequence: 1. 2. 3. Connect ground Apply VDD Set all inputs to a known state To power-down the device, reverse the steps above. TABLE 3-2: Symbol RECOMMENDED OPERATING CONDITIONS Parameter VDD Logic voltage supply HVOUT High voltage output Min Typ Max Units 10.8 12 13.2 V V -0.3 - 225 VIH High-level input voltage VDD-2.0 - VDD V VIL Low-level input voltage 0 - 2.0 V fCLK Clock frequency - - 8.0 MHz -40 - +85 °C TA Operating free-air temperature VDD VDD HVOUT DATA OUT INPUT HVIN GND GND GND Logic Inputs FIGURE 3-1: Logic Data Output High Voltage Outputs Input and Output Equivalent Circuits 2015 Microchip Technology Inc. DS20005418B-page 7 HV5122 / HV5222 12V DATA IN Data Valid 1 0V tSU tH 12V CLK 50% 50% 50% 0V tWH tWL DATA OUT 50% tDHL DATA OUT tDLH STR 50% tON HVOUT FIGURE 3-2: DS20005418B-page 8 15V Switching Waveforms 2015 Microchip Technology Inc. HV5122 / HV5222 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 44-lead PQFP Example XXXXXXXXXX XXXXXXXXXX XXXXXXXX e3 YYWWNNN HV5122PG e3 1526343 44-lead PLCC Example XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXX e3 YYWWNNN HV5122PJ e3 1526343 Legend: XX...X Y YY WW NNN e3 * Note: Product Code or Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for product code or customer-specific information. Package may or not include the corporate logo. 2015 Microchip Technology Inc. DS20005418B-page 9 HV5122 / HV5222 44-Lead PQFP Package Outline (PG) 10.00x10.00mm body, 2.35mm height (max), 0.80mm pitch D D1 E E1 Note 1 (Index Area D1/4 x E1/4) 44 1 b e Top View View B A L2 A2 Gauge Plane Seating Plane L A1 θ L1 Side View Seating Plane View B Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging. Note: 1. $3LQLGHQWL¿HUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWL¿HUFDQEHDPROGHGPDUNLGHQWL¿HUDQHPEHGGHGPHWDOPDUNHURU a printed indicator. Symbol MIN Dimension NOM (mm) MAX A A1 A2 b D D1 E E1 1.95* 0.00 1.95 0.30 13.65* 9.80* 13.65* 9.80* - - 2.00 - 13.90 10.00 13.90 10.00 2.35 0.25 2.10 0.45 14.15* 10.20* 14.15* 10.20* e L L1 L2 0.80 BSC 0.88 1.03 ș 0O 0.73 1.95 REF 0.25 BSC 3.5O 7O JEDEC Registration MO-112, Variation AA-2, Issue B, Sep.1995. 7KLVGLPHQVLRQLVQRWVSHFL¿HGLQWKH-('(&GUDZLQJ Drawings not to scale. S D # DSPD 44PQFPPG V i C041309 DS20005418B-page 10 2015 Microchip Technology Inc. HV5122 / HV5222 44-Lead PLCC Package Outline (PJ) .653x.653in body, .180in height (max), .050in pitch D D1 1 44 .048/.042 x 45O 6 .150 MAX .056/.042 x 45O 40 Note 1 (Index Area) .075 MAX E1 E Note 2 .020max (3 Places) Top View Vertical Side View View B b1 A Base Plane A2 .020 MIN Seating Plane e A1 b Horizontal Side View R View B Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging. Notes: 1. $3LQLGHQWL¿HUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWL¿HUFDQEHDPROGHGPDUNLGHQWL¿HUDQHPEHGGHGPHWDOPDUNHURU a printed indicator. 2. $FWXDOVKDSHRIWKLVIHDWXUHPD\YDU\ Symbol MIN Dimension (inches) A A1 A2 b b1 D D1 E E1 .165 .090 .062 .013 .026 .685 .650 .685 .650 NOM .172 .105 - - - .690 .653 .690 .653 MAX .180 .120 .083 .021 .036† .695 .656 .695 .656 e R .025 .050 BSC .035 .045 JEDEC Registration MS-018, Variation AC, Issue A, June, 1993. † This dimension differs from the JEDEC drawing. Drawings not to scale. 2015 Microchip Technology Inc. DS20005418B-page 11 HV5122 / HV5222 APPENDIX A: REVISION HISTORY Revision A (August 2015) • Update file to new format Revision B (October 2015) • Updated Continuous total power dissipation in Absolute Maximum Ratings on page 3 • Corrected a typo on page 13 DS20005418B-page 12 2015 Microchip Technology Inc. HV5122 / HV5222 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device - XX X - Package Environmental Options X Media Type Device: HV5122 = 32-Channel Serial to Parallel Converter, data shifts in counter-clockwise direction HV5222 = 32-Channel Serial to Parallel Converter, data shifts in clockwise direction Package: PG PJ = 44-Lead PQFP = 44-Lead PLCC Environmental G = Lead (Pb)-free/ROHS-compliant package Media Type: (blank) = 96/Tray for PG package = 27/Tube for PJ package 2015 Microchip Technology Inc. Examples: a) HV5122PG-G b) HV5222PJ-G Data shifts in counterclockwise direction, 44Lead PQFP package, 96/Tray Data shifts in clockwise direction, 44-Lead PLCC package, 27/Tube DS20005418B-page 13 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-882-6 QUALITYMANAGEMENTSYSTEM CERTIFIEDBYDNV == ISO/TS16949== DS20005418B-page 14 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 2015 Microchip Technology Inc. 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