HV5523 DATA SHEET (04/15/2011) DOWNLOAD

Supertex inc.
HV5523
32-Channel Serial To Parallel Converter
With Open Drain Outputs
Features
►►
►►
►►
►►
►►
Processed with HVCMOS® technology
Sink current minimum 100mA
Shift register speed 16MHz
Polarity and blanking inputs
CMOS compatible inputs
Applications
►► Inkjet and Electrostatic Print Heads
►► AC-Electroluminescent Displays
►► MEMS Applications
General Description
The HV5523 is a low-voltage serial to high-voltage parallel converter
with open drain outputs. This device has been designed for use as
a driver for AC-electroluminescent displays. It can also be used in
any application requiring multiple output high voltage current sinking
capabilities, such as driving inkjet and electrostatic print heads,
plasma panels, and vacuum fluorescent or large matrix LCD displays.
This device consists of a 32-bit shift register, 32 latches, and control
logic to perform the polarity selection and blanking of the outputs.
Data are shifted through the shift register on the high to low transition
of the clock. The HV5523 shifts in a counter-clockwise direction when
viewed from the top of the package. A data output buffer is provided
for cascading devices. This output reflects the current status of the last
bit of the shift register. Operation of the shift register is not affected by
the LE (latch enable), BL (blanking), or POL (polarity) inputs. Transfer
of data from the shift register to the latch occurs when the LE (latch
enable) input is high. The data in the latch is stored when LE is low.
Block Diagram
POL
BL
LE
HVOUT1
DATA
INPUT
Latch
HVOUT2
CLK
Latch
32-Bit
Shift
Register
(Outputs 3 to 30
not shown)
HVOUT31
Latch
HVOUT32
DATA
OUTPUT
Supertex inc.
Latch
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
HV5523
Ordering Information
Pin Configuration
High Voltage
Output
HVOUT
Device
44
44-Lead QFN
(max V)
7.00x7.00mm body,
0.80mm height (max),
0.50mm pitch
220
HV5523K7-G
HV5523
1
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter
Value
Output voltage, HVOUT
-0.5V to +230V
1
Logic input levels
44-Lead QFN (K7)
(top view)
-0.5V to +7.0V
Supply voltage, VDD1
-0.5V to VDD +0.5V
1
Ground current2
Product Marking
1.5A
Continuous total power dissipation3
Operating temperature range
HV5523K7
LLLLLLLLL
YYWW
AAA CCC
3.4W
-40°C to +85°C
Storage temperature range
-65°C to +150°C
Maximum junction temperature
+125°C
Thermal resistance (θja)3
29OC/W
L = Lot Number
YY = Year Sealed
WW = Week Sealed
A = Assembler ID
C = Country of Origin
= “Green” Packaging
Package may or may not include the following marks: Si or
44-Lead QFN (K7)
Notes:
1. Voltages are referenced to VSS.
2. Duty cycle is limited by the total power dissipated in the package.
3. 1.0oz 4-layer 3x4” PCB.
Operating Supply Voltages and Conditions
Sym
Parameter
Min
Typ
Max
Units
Conditions
VDD
Logic supply voltage
4.5
-
5.5
V
---
HVOUT
High voltage output
-0.3
-
+220
V
---
VIH
High-level input voltage
0.8VDD
-
VDD
V
---
VIL
Low-level input voltage
0
-
0.2VDD
V
---
fCLK
Clock frequency
-
-
16
MHz
---
TA
Operating free-air temperature
-40
-
+85
°C
---
Notes:
Power-up sequence should be the following:
1. Connect ground.
2. Apply VDD.
3. Set all inputs to a known state. Power-down sequence should be the reverse of the above.
Supertex inc.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
2
HV5523
DC Electrical Characteristics
Sym
(Over operating supply voltages and temperature, unless otherwise noted)
Parameter
Min
Typ
Max
Units
Conditions
IDD
VDD supply current
-
-
25
mA
IDDQ
Quiescent VDD supply current
-
-
100
µA
Off state output current
-
-
10
µA
IIH
High-level logic input current
-
-
1.0
µA
VIH = VDD
IIL
Low-level logic input current
-
-
-1.0
µA
VIL = 0V
VDD -1.0V
-
-
V
IDOUT = -10mA
HVOUT
-
-
15
V
IHVOUT = +100mA
DATA OUT
-
-
1.0
V
IDOUT = +10mA
-
-
-1.5
V
IOL = -100mA
Min
Typ
Max
Units
Conditions
-
-
16
MHz
---
IO(OFF)
VOH
High level output
VOL
Low level output
VOC
HVOUT clamp voltage
AC Electrical Characteristics (V
DD
Sym
fCLK = 16MHz, fDATA = 8.0MHz
DIN = 0V, all input logic pins = 0V,
all outputs off
All outputs high,
all switches parallel
= 5.0V, Tj = 25OC)
Parameter
fCLK
Clock frequency
tW
Clock high / low pulse width
31
-
-
ns
---
tSU
Data setup time before clock falls
25
-
-
ns
---
tH
Data hold time after clock falls
10
-
-
ns
---
tON
Turn on time, HVOUT from Enable
-
-
400
ns
RL = 2.0kΩ to VPP max
tDHL
Delay time clock to data high to low
-
-
35
ns
CL = 15pF
tDLH
Delay time clock to data low to high
-
-
35
ns
CL = 15pF
tDLE
Delay time clock to LE low to high
20
-
-
ns
---
tWLE
Width of LE pulse
20
-
-
ns
---
tSLE
LE set-up time before clock falls
20
-
-
ns
---
CIN
Digital logic input capacitance
-
-
15
pF
---
Input and Output Equivalent Circuits
VDD
VDD
HVOUT
DATA
OUTPUT
DATA
INPUT
VSS
VSS
VSS
Logic Inputs
Supertex inc.
Logic Data Output
High Voltage Outputs
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
3
HV5523
Switching Waveforms
DATA
INPUT
50%
Data Valid
tSU
CLK
50%
VIH
50%
VIL
tH
50%
50%
tWH
50%
tWL
VOL
tDLH
VOH
50%
VOL
tDHL
VIH
50%
50%
LE
tWLE
tDLE
VIL
tSLE
HV OUT
w/ S/R HIGH
VOH
10%
VOL
tON
Function Table
Function
Inputs
Outputs
Shift Reg
1 2...32
HV Outputs
1 2...32
Data Out
*
Data
CLK
LE
BL
POL
All ON
X
X
X
L
L
*
*...*
On
On...On
*
All Off
X
X
X
L
H
*
*...*
Off
Off...Off
*
Invert mode
X
X
L
H
L
*
*...*
Load S/R
H or L
↓
L
H
H
H or L
X
H or L
↑
H
H
*
X
H or L
↑
H
L
L
↓
H
H
H
↓
H
H
Load latches
Transparent latch
mode
*
*...*
*
*
*...*
*
*...*
*
*...*
*
*
*...*
*
*...*
*
H
L
*...*
Off
*...*
*
H
H
*...*
On
*...*
*
*...*
Notes:
H = high level, L = low level, X = irrelevant, ↓ = high-to-low transition, ↑ = low-to-high transition
* = dependent on previous stage’s state before the last CLK↓ or last LE high.
Supertex inc.
VIL
VOH
50%
DATA
OUTPUT
VIH
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
4
HV5523
Pin Description
Pin #
Function
1
HVOUT11
2
HVOUT12
3
HVOUT13
4
HVOUT14
5
HVOUT15
6
HVOUT16
7
HVOUT17
8
HVOUT18
9
HVOUT19
10
HVOUT20
11
HVOUT21
12
HVOUT22
13
HVOUT23
14
HVOUT24
15
HVOUT25
16
HVOUT26
17
HVOUT27
18
HVOUT28
19
HVOUT29
20
HVOUT30
21
HVOUT31
Description
High voltage outputs.
22
HVOUT32
23
DATA OUT
24
N/C
25
N/C
26
N/C
27
POL
Inverts the polarity of the HVOUT pins
28
CLK
Clock pin, shift registers shifts data on falling edge of input clock.
29
VSS
Reference voltage, usually ground.
30
VDD
Logic supply voltage.
31
LE
32
DATA IN
Data output pin.
No internal connection.
Latch enable pin, data is shifted from shift register to latches on logic input high.
Data input pin.
33
BL
Blanking pin sets all HVout pins ON or OFF depending upon state of polarity. See function table.
34
N/C
No internal connection.
35
HVOUT1
36
HVOUT2
37
HVOUT3
38
HVOUT4
39
HVOUT5
40
HVOUT6
41
HVOUT7
42
HVOUT8
43
HVOUT9
44
HVOUT10
Center Tab
High voltage outputs.
Connect to VSS
Supertex inc.
● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com
5
HV5523
44-Lead QFN Package Outline (K7)
7.00x7.00mm body, 0.80mm height (max), 0.50mm pitch
D2
D
44
Note 1
(Index Area
D/2 x E/2)
44
Note 1
(Index Area
D/2 x E/2)
1
1
E2
E
Top View
View B
Bottom View
Note 3
θx4
L
A
A3
Seating
Plane
L1
Note 2
A1
b
e
Side View
View B
Notes:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present.
3. The inner tip of the lead may be either rounded or square.
Symbol
Dimension
(mm)
A
A1
MIN
0.70
0.00
NOM
0.75
0.02
MAX
0.80
0.05
A3
0.20
REF
b
D
D2
E
E2
0.18
6.85*
5.00
6.85*
5.00
0.25
7.00
5.15†
7.00
5.15†
0.30
7.15*
5.25†
7.15*
5.25†
†
e
†
0.50
BSC
L
L1
θ
0.00
0O
0.55†
-
-
0.65†
0.15
14O
0.45
†
JEDEC Registration MO-220, Variation WKKD-3, Issue K, June 2006
* This dimension is not specified in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc. #: DSPD-44QFNK77X7P050, Version A122309.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
Supertex inc.
©2011 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Doc.# DSFP-HV5523
A041511
6
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com