Supertex inc. HV9408 32-Channel Serial to Parallel Converter With High Voltage Push-Pull Outputs Features ►► Processed with HVCMOS® technology ►► Low power level shifting ►► Shift register speed 8.0MHz ►► Latched data outputs ►► 5.0V CMOS compatible inputs ►► Diode to VPP allows efficient power recovery General Description The HV9408 is a low voltage serial to high voltage parallel converter with push-pull outputs. This device has been designed for use as a driver for AC-electroluminescent displays. It can also be used in any application requiring multiple output, high voltage current sourcing and sinking capabilities such as driving plasma panels, vacuum fluorescent, or large matrix LCD displays. This device consists of a 32-bit shift register, 32 latches, and control logic to enable outputs. HVOUT1 is connected to the first stage of the shift register through the Output Enable logic. Data is shifted through the shift register on the low to high transition of the clock. The HV9408 shifts in the counter-clockwise direction when viewed from the top of the package. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register (32). Operation of the shift register is not affected by the LE (latch enable) or the OE (output enable) inputs. Transfer of data from the shift register to the latch occurs when the LE input is high. The data in the latch is retained when LE is low. Block Diagram Output Enable Latch Enable VPP DATA INPUT HVOUT1 CLOCK 32 bit Static Shift Register 32 Latches HVOUT2 • • • 32 Outputs Total • • • HVOUT31 DATA OUT Doc.# DSFP-HV9408 B072213 HVOUT32 Supertex inc. www.supertex.com HV9408 Ordering Information Pin Configuration Part Number Package Options Packing HV9408PJ-G 44-Lead PLCC 27/Tube HV9408PJ-G M903 44-Lead PLCC 500/Reel 6 1 44 40 -G denotes a lead (Pb)-free / RoHS compliant package Absolute Maximum Ratings Parameter Value Supply voltage, VDD -0.5V to +7.0V Supply voltage, VPP -0.5V to +90V Logic input levels 44-Lead Plastic Leaded Chip Carrier (top view) -0.5V to VDD +0.5V Ground current1 1.5A Continuous total power dissipation2 1200W Product Marking Top Marking -40 to +85 C Operating temperature range O Storage temperature range YYWW AAA HV9408PJ -65 to +150OC LLLLLLLLLL Bottom Marking Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. CCCCCCCCCCC YY = Year Sealed WW = Week Sealed L = Lot Number A = Assembler ID C = Country of Origin* = “Green” Packaging *May be part of top marking Package may or may not include the following marks: Si or 44-Lead Plastic Leaded Chip Carrier Typical Thermal Resistance Notes: 1. Duty cycle is limited by the total power Package θja dissipated in the package. 2. For operation above 25°C ambient derate linearly to maximum operatin 44-Lead PLCC at 20mW/°C. temperature 37OC/W Mounted on FR-4 board, 25mm x 25mm x 1.57mm Recommended Operating Conditions Sym Parameter Min Max Units VDD Logic voltage supply 4.5 5.5 V VPP High voltage supply 8.0 80 V VIH Input high voltage VDD - 0.5 VDD V VIL Input low voltage 0 0.5 V fCLK Clock frequency 0 8.0 MHz TA Operating free-air temperature -40 +85 Doc.# DSFP-HV9408 B072213 2 C O Supertex inc. www.supertex.com HV9408 Electrical Characteristics (V DC Characteristics Sym PP = 60V, VDD = 5.0V, TA = 25°C) Parameter Min Max Units Conditions IPP VPP supply current - 100 µA HVOUTPUTS high to low IDDQ IDD supply current (quiescent) - 100 µA All inputs = VDD or GND IDD IDD supply current (operating) - 15 mA VDD = VDD max, fCLK = 8.0 MHz VOH (Data) Shift register output voltage VDD -0.5 - V IO = -100µA VOL (Data) Shift register output voltage - 0.5 V IO = 100µA IIH Current leakage, any input - 1.0 µA Input = VDD IIL Current leakage, any input - -1.0 µA Input = GND VOC HV output clamp diode voltage - -1.5 V IOC = -5.0mA VOH HV output when sourcing 52 - V IOH = -20mA, 0 to 70°C VOL HV output when sinking - 4.0 V IOL = 5.0mA, 0 to 70°C AC Characteristics Sym Min Max Units Conditions - 8.0 MHz --- Clock width, high or low 62 - ns --- tSU Setup time before CLK rises 25 - ns --- tH Hold time after CLK rises 10 - ns --- tDLH (Data) Data output delay after L to H CLK - 110 ns CL = 15pF tDHL (Data) Data output delay after H to L CLK - 110 ns CL = 15pF fCLK tWL or tWH Parameter Clock frequency tDLE LE delay after L to H CLK 50 - ns --- tWLE Width of LE pulse 50 - ns --- tSLE LE setup time before L to H CLK 50 - ns --- tON Delay from LE to HVOUT, L to H - 500 ns --- tOFF Delay from LE to HVOUT, H to L - 500 ns --- Power-Up Sequence 1. Connect ground 2. Apply VDD 3. Set all inputs (Data, CLK, Enable, etc.) to a known state 4. Apply VPP Power-down sequence should be the reverse of the above. The VPP should not drop below VDD during operations. Doc.# DSFP-HV9408 B072213 3 Supertex inc. www.supertex.com HV9408 Input and Output Equivalent Circuits VDD VDD VPP Data Out Input GND GND Logic Inputs HVOUT GND Logic Data Output High Voltage Outputs Switching Waveforms VIH DATA INPUT Data Valid 50% 50% VIL tSU tH VIH CLOCK 50% 50% 50% tWL 50% tWH VOH 50% VOL tDLH DATA OUT VOH 50% VOL tDHL VOH 50% 50% Latch Enable tWLE tDLE HVOUT w/ S/R LOW VIL tSLE 90% 10% VOL VOH VOL tOFF 10% HVOUT w/ S/R HIGH Doc.# DSFP-HV9408 B072213 tON 4 VOH 90% VOL Supertex inc. www.supertex.com HV9408 Function Tables Data Input Data Output Data Input LE OE HV Output H H X X L L L All HVOUT = low X L H Previous latched data H H H H L H H L X CLK No No change = low to high level transition. Pin Description Pin Function 1 HVOUT16 2 HVOUT17 3 HVOUT18 4 HVOUT19 5 HVOUT20 6 HVOUT21 7 HVOUT22 8 HVOUT23 9 HVOUT24 10 HVOUT25 11 HVOUT26 12 HVOUT27 13 HVOUT28 14 HVOUT29 15 HVOUT30 16 HVOUT31 17 HVOUT32 18 Data Out 19 N/C 20 N/C 21 N/C 22 CLK 23 GND Logic and high voltage ground. 24 VPP High voltage power rail. 25 VDD Low voltage logic power rail. Doc.# DSFP-HV9408 B072213 Description High voltage outputs. High voltage push-pull outputs, which, depending on controlling low voltage data, can drive loads either to a GND, or to VPP rail levels. Serial data output Data output for cascading to the data input of the next device. No connect. Data shift register clock. Input are shifted into the shift register on the positive edge of the clock. 5 Supertex inc. www.supertex.com HV9408 Pin Function Description Latch enable input. 26 Latch Enable 27 Data In When LE is high, shift register data is transferred into a data latch. When LE is low, data is latched, and new data can be clocked into the shift register. Serial data input. Data needs to be present before each rising edge of the clock. Output enable input. 28 Output Enable 29 N/C 30 HVOUT1 31 HVOUT2 32 HVOUT3 33 HVOUT4 34 HVOUT5 35 HVOUT6 36 HVOUT7 37 HVOUT8 38 HVOUT9 39 HVOUT10 40 HVOUT11 41 HVOUT12 42 HVOUT13 43 HVOUT14 44 HVOUT15 Doc.# DSFP-HV9408 B072213 When OE is low, all HV outputs are forced into a low state, regardless of data in each channel. When OE is high, all HV outputs reflect data latched. No connect. High voltage outputs. High voltage push-pull outputs, which, depending on controlling low voltage data, can drive loads either to a GND, or to VPP rail levels. 6 Supertex inc. www.supertex.com HV9408 44-Lead PLCC Package Outline (PJ) .653x.653in body, .180in height (max), .050in pitch D D1 .048/.042 x 45O 1 44 6 .150max .056/.042 x 45O 40 Note 1 (Index Area) .075max E E1 Note 2 e .020max (3 Places) Top View Vertical Side View View B b1 A A1 Base .020min Plane A2 Seating Plane b Horizontal Side View R View B Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Actual shape of this feature may vary. Symbol Dimension (inches) A A1 A2 b b1 D D1 E E1 MIN .165 .090 .062 .013 .026 .685 .650 .685 .650 NOM .172 .105 - - - .690 .653 .690 .653 MAX .180 .120 .083 .021 .036† .695 .656 .695 .656 e .050 BSC R .025 .035 .045 JEDEC Registration MS-018, Variation AC, Issue A, June, 1993. † This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc. #: DSPD-44PLCCPJ, Version F031111. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV9408 B072213 7 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com