HV5630 DATA SHEET (06/27/2014) DOWNLOAD

Supertex inc.
HV5630
32-Channel Serial to Parallel Converter
With Open Drain Outputs
Features
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Processed with HVCMOS technology
Sink current minimum 100mA
Shift register speed 8.0MHz
Polarity and Blanking inputs
CMOS compatible inputs
Forward and reverse shifting options
Diode to VPP allows efficient power recovery
®
General Description
The HV5630 is a low-voltage serial to high-voltage parallel
converter with open drain outputs. This device has been designed
for use as a driver for AC-electroluminescent displays. It can also
be used in any application requiring multiple output high voltage
current sinking capabilities such as driving inkjet and electrostatic
print heads, plasma panels, vacuum fluorescent, or large matrix
LCD displays.
This device consists of a 32-bit shift register, 32 latches, and control
logic to perform the polarity select and blanking of the outputs. Data
is shifted through the shift register on the high to low transition of the
clock. The HV5630 shifts in the clockwise direction when viewed
from the top of the package. A data output buffer is provided for
cascading devices. This output reflects the current status of the last
bit of the shift register. Operation of the shift register is not affected
by the LE (latch enable), BL (blanking), or the POL (polarity) inputs.
Transfer of data from the shift register to the latch occurs when the
LE (latch enable) input is high. The data in the latch is stored when
LE is low.
Functional Block Diagram
POL
BL
LE
HVOUT1
DATA
IN
Latch
HVOUT2
CLK
Latch
32-Bit
Shift
Register
(Outputs 3 to 30 not shown)
HVOUT31
Latch
HVOUT32
DATA
OUT
Doc.# DSFP-HV5630
C072313
Latch
Supertex inc.
www.supertex.com
HV5630
Pin Configuration
Ordering Information
Part Number
Package
Packing
HV5630PJ-G
44-Lead PLCC
27/Tube
HV5630PJ-G M903
44-Lead PLCC
500/Reel
6
1 44
40
-G denotes a lead (Pb)-free / RoHS compliant package
Absolute Maximum Ratings
Parameter
44-Lead PLCC
Value
Supply voltage, VDD1
-0.5V to +15V
Output voltage, VPP1
-0.5V to +315V
Logic input levels1
(top view)
Product Marking
-0.5V to VDD +0.5V
Ground current2
YY = Year Sealed
WW = Week Sealed
LLLLLLLLLL
L = Lot Number
A = Assembler ID
Bottom Marking
C = Country of Origin*
= “Green” Packaging
1.5A
Continuous total power dissipation3
YYWW AAA
HV5630PJ
1200mW
Operating temperature range
Storage temperature range
Top Marking
-40 C to +85OC
O
-65OC to +150OC
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. Continuous operation of the device
at the absolute rating level may affect device reliability. All voltages are referenced to device
ground.
Notes:
1. All voltages are referenced to VSS
2. Duty cycle is limited by the total power dissipated in the package
3. For operation above 25°C ambient derate linearly to maximum operating temperature at 20mW/°C.
CCCCCCCCCCC
*May be part of top marking
44-Lead PLCC
Package may or may not include the following marks: Si or
Typical Thermal Resistance
Package
θja
44-Lead PLCC
37OC/W
Recommended Operating Conditions
Symbol
Parameter
Min
Max
Units
Conditions
VDD
Logic voltage supply
10.8
13.2
V
---
HVOUT
High voltage output
-0.3
+300
V
---
VIH
Input high voltage
VDD -2.0
VDD
V
---
VIL
Input low voltage
0
2.0
V
---
fCLK
Clock frequency
-
8.0
MHz
---
TA
Operating free-air temperature
-40
+85
C
---
O
Power-Up Sequence
Power-up sequence should be the following:
1. Connect ground
2. Apply VDD
3. Set all inputs to a known state
Power-down sequence should be the reverse of the above.
Doc.# DSFP-HV5630
C072313
2
Supertex inc.
www.supertex.com
HV5630
Electrical Characteristics (over recommended operating conditions unless otherwise noted)
DC Characteristics
Sym
Parameter
Min
Max
Units
Conditions
IDD
VDD supply current
-
15
mA
fCLK = 8.0MHz, FDATA = 4.0MHz
IDDQ
VDD supply current (quiescent)
-
100
µA
VIN = 0V
Off state output current
-
10
µA
All outputs high, all SWS parallel
IIH
High-level logic input current
-
1.0
µA
VIH = VDD
IIL
Low-level logic input current
-
-1.0
µA
VIL = 0V
VDD -1.0V
-
V
IDOUT = -100µA
HVOUT
-
15
V
IHVOUT = +100mA
DATA OUT
-
1.0
V
IDOUT = +100µA
-
-1.5
V
IOL = -100mA
Min
Max
Units
Conditions
-
8.0
MHz
---
IO(OFF)
VOH
High-level output data out
VOL
Low-level output voltage
VOC
HVOUT clamp voltage
AC Characteristics
Sym
(VDD = 12V, TC = 25OC)
Parameter
fCLK
Clock frequency
tW
Clock width, high or low
62
-
ns
---
tSU
Data set-up time before CLK falls
25
-
ns
---
tH
Data hold time after CLK falls
10
-
ns
---
tON
Turn-on time, HVOUT from enable
-
500
ns
RL = 2.0KΩ to VPP max.
tDHL
Delay time clock to data high to low
-
100
ns
CL = 15pF
tDLH
Delay time clock to data low to high
-
100
ns
CL = 15pF
tDLE
Delay time clock to LE low to high
50
-
ns
---
tWLE
Width of LE pulse
50
-
ns
---
tSLE
LE setup time before clock falls
50
-
ns
---
Input and Output Equivalent Circuits
VDD
VDD
HVOUT
DATA
OUT
DATA
IN
HVIN
VSS
VSS
VSS
Logic Inputs
Doc.# DSFP-HV5630
C072313
Logic Data Output
3
High Voltage Outputs
Supertex inc.
www.supertex.com
HV5630
Switching Waveforms
VIH
DATA
IN
50%
Data Valid
50%
tSU
CLK
VIL
tH
VIH
50%
50%
50%
tWH
50%
tWL
VOH
50%
DATA
OUT
VOL
tDLH
VOH
50%
VOL
tDHL
VIH
50%
50%
LE
tWLE
tDLE
VIL
VIL
tSLE
VOH
HVOUT
w/ S/R HIGH
10%
VOL
tON
Functional Table
Inputs
Function
Outputs
1
2...32
Data Out
*
L
*
*...*
On
On...On
*
L
H
*
*...*
Off
Off...Off
*
L
H
L
*
*...*
*
*...*
*
↓
L
H
H
H or L
*...*
*
*...*
*
X
H or L
↑
H
H
*
*...*
*
*...*
*
X
H or L
↑
H
L
*
*...*
*
*...*
*
L
↓
H
H
H
L
*...*
Off
*...*
*
H
↓
H
H
H
H
*...*
On
*...*
*
LE
BL
POL
All on
X
X
X
L
All off
X
X
X
Invert mode
X
X
Load S/R
H or L
Transparent latch
mode
HV Outputs
2...32
CLK
Load latches
Shift Reg
1
Data
Notes:
H = high level, L = low level, X = irrelevant, ↓ = high-to-low transition, ↑ = low-to-high transistion.
* dependent on previous stage’s state before the last CLK ↓ or last LE high.
Doc.# DSFP-HV5630
C072313
4
Supertex inc.
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HV5630
44-Lead PLCC Pin Description
Pin
Function
1
HVOUT17
2
HVOUT16
3
HVOUT15
4
HVOUT14
5
HVOUT13
6
HVOUT12
7
HVOUT11
8
HVOUT10
9
HVOUT9
10
HVOUT8
Description
High voltage outputs.
11
HVOUT7
12
HVOUT6
13
HVOUT5
14
HVOUT4
15
HVOUT3
16
HVOUT2
17
HVOUT1
18
DATA OUT
19
N/C
20
N/C
21
N/C
22
POL
Inverts the polarity of the HVOUT pins
23
CLK
Clock pin, shift registers shift data on falling edge of input clock.
24
VSS
Reference voltage, usually ground.
25
VDD
Logic supply voltage.
26
LE
27
DATA IN
28
BL
Blanking pin sets all HVout pins low or high depending upon state of polarity.
See function table.
29
N/C
No internal connection.
30
HVOUT32
31
HVOUT31
32
HVOUT30
33
HVOUT29
34
HVOUT28
35
HVOUT27
36
HVOUT26
37
HVOUT25
38
HVOUT24
39
HVOUT23
40
HVOUT22
41
HVOUT21
42
HVOUT20
43
HVOUT19
44
HVOUT18
Doc.# DSFP-HV5630
C072313
Data output pin.
No internal connection.
Latch enable pin, data is shifted from shift register to latches on logic input high.
Data input pin.
High voltage outputs.
5
Supertex inc.
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HV5630
44-Lead PLCC Package Outline (PJ)
.653x.653in body, .180in height (max), .050in pitch
D
D1
.048/.042
x 45O
1
6
44
.150max
.056/.042
x 45O
40
Note 1
(Index Area)
.075max
E
E1
Note 2
e
.020max
(3 Places)
Top View
Vertical Side View
View
B
b1
A
A1
Base .020min
Plane
A2
Seating
Plane
b
Horizontal Side View
R
View B
Notes:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
2. Actual shape of this feature may vary.
Symbol
Dimension
(inches)
A
A1
A2
b
b1
D
D1
E
E1
MIN
.165
.090
.062
.013
.026
.685
.650
.685
.650
NOM
.172
.105
-
-
-
.690
.653
.690
.653
MAX
.180
.120
.083
.021
.036
.695
.656
.695
.656
†
e
.050
BSC
R
.025
.035
.045
JEDEC Registration MS-018, Variation AC, Issue A, June, 1993.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc. #: DSPD-44PLCCPJ, Version F031111.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
Supertex inc.
©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Doc.# DSFP-HV5630
C072313
6
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com