HV66 DATA SHEET (06/27/2014) DOWNLOAD

Supertex inc.
HV66
32-Channel LCD Driver
with Separate Backplane Output
Features
General Description
►► HVCMOS® technology
►► 32 push-pull CMOS output up to 60V
►► Low power level shifting
►► Shift register speed 5.0MHz
►► Latched data outputs
►► Bidirectional shift register (DIR)
►► Backplane output
The HV66 is a low voltage serial to high voltage parallel converter
with push-pull outputs. This device has been designed for use as
a driver circuit for LCD displays. It can also be used in any application requiring multiple output high voltage current sourcing and
sinking capabilities. The inputs are fully CMOS compatible.
The device consists of a 32-bit shift register, 32 latches, and control logic to perform blanking and polarity control of the outputs.
HVOUT1 is connected to the first stage of the shift register. Data is
shifted through the shift register on the logic rising transition of the
clock. A DIR pin causes data shifting clockwise when grounded
and counter clockwise when connected to VDD. A data output
buffer is provided for cascading devices. This output reflects the
current status of the last bit of the shift register. Operation of the
shift register is not affected by the LE (latch enable), BL (blank) or
the POL (polarity) inputs. Transfer of data from the shift register to
the latch occurs when the LE (latch enable) input is high. The data
in the latch is stored after LE transitions from high to low.
Functional Block Diagram
VPP
POL
BL
LE
VDD
DATA IN
Latch
CLK
Latch
DIR
32-Bit
Shift
Register
HVOUT2
(Outputs 3 to 30
not shown)
Latch
DATA OUT
HVOUT1
Latch
HVOUT31
HVOUT32
BPOUT
GND
Doc.# DSFP-HV66
C070313
Supertex inc.
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HV66
Pin Configuration
Ordering Information
Part Number
Package Option
Packing
HV66PG-G
44-Lead PQFP
96/Tray
HV66PG-G M919
44-Lead PQFP
500/Reel
HV66PJ-G
44-Lead PLCC
27/Tube
HV66PJ-G M903
44-Lead PLCC
500/Reel
44
1
44-Lead PQFP
(top view)
-G denotes a lead (Pb)-free / RoHS compliant package
6
40
1 44
Absolute Maximum Ratings1
Parameter
Value
Supply voltage, VDD
2
-0.5V to +7.0V
Supply voltage, VPP2
-0.5V to +70V
Logic input levels
-0.5V to VDD +0.5V
Ground current3
1.5A
Continuous total power dissipation4
1200mW
Operating temperature range
-40°C to +85°C
Storage temperature range
-65°C to +125°C
Absolute Maximum Ratings are those values beyond which damage to the
device may occur. Functional operation under these conditions is not implied.
Continuous operation of the device at the absolute rating level may affect device
reliability. All voltages are referenced to GND.
Notes:
1. Device will survive (but operation may not be specified or guaranteed)
at these extremes
2. All voltages are referenced to GND
3. Duty cycle is limited by the total power dissipated in the package
4. For operation above 25°C ambient derate linearly to 85°C at 20mW/°C
44-Lead PLCC
(top view)
Product Marking
Top Marking
YYW W
HV66PG
LLLLLLLLL
Bottom Marking
CCCCCCCC
AAA
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Package may or may not include the following marks: Si or
44-Lead PQFP
Top Marking
YYWW AAA
YY = Year Sealed
WW = Week Sealed
A = Assembler ID
L = Lot Number
Bottom Marking
C = Country of Origin*
= “Green” Packaging
HV66PJ
LLLLLLLLLL
Typical Thermal Resistance
Package
θja
44-Lead PQFP
51 C/W
44-Lead PLCC
37OC/W
CCCCCCCCCCC
*May be part of top marking
O
Package may or may not include the following marks: Si or
44-Lead PLCC
Recommended Operating Conditions
Sym
Parameter
Min
Max
Units
VDD
Logic supply voltage
4.5
5.5
V
VPP
High voltage supply
12
60
V
VIH
High-level input voltage
2.4
VDD
V
VIL
Low-level input voltage
0
0.8
V
fCLK
Clock frequency
0
5.0
MHz
TA
Operating free-air temperature
-40
+85
°C
IOD
Allowable current through output diodes
-
200
mA
Doc.# DSFP-HV66
C070313
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Supertex inc.
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HV66
Electrical Characteristics (over recommended operating conditions unless otherwise noted)
DC Characteristics (V
DD
Sym
= 5.0V, VPP = 60V)
Parameter
Min
Max
Units
Conditions
-
15
mA
VDD = 5.5V, fCLK = 5.0MHz
-
0.5
mA
Outputs high
-
0.5
mA
Outputs low
-
0.5
mA
All VIN = GND or VDD
HVOUT
50
-
DATA OUT
4.6
-
HVOUT
-
8.0
DATA OUT
-
0.4
IDD
VDD supply current
IPPQ
Quiescent VPP supply current
IDDQ
Quiescent VDD supply current
VOH
High-level output
VOL
Low-level output
IIH
High-level input current
-
1.0
µA
VIH = VDD
IIL
Low-level input current
-
-1.0
µA
VIL = 0V
VOLBP
Low-level output voltage, backplane
-
3.0
V
IO = +10mA
VOHBP
High-level output voltage, backplane
57
-
V
IO = -10mA
AC Characteristics (V
DD
fCLK
V
V
IO = -5.0mA, VPP = +60V
IO = -100µA
IO = +5.0mA, VPP = +60V
IO = +100µA
= 5.0V, VPP = 60V, TA = 25OC, logic input rise/fall time = 10ns.)
-
5.0
MHz
---
Clock width high or low
100
-
ns
---
tSU
Data set-up time before clock rises
25
-
ns
---
tH
Data hold time after clock rises
50
-
ns
---
tWL, tWH
Clock frequency
tHON, tHOFF
Time from latch enable or POL to HVOUT
-
500
ns
CL = 20pF
tBON, tBOFF
Time from POL to BPOUT
-
500
ns
CL = 20pF
tDHL
Delay time clock to data high to low
-
200
ns
CL = 10pF
tDLH
Delay time clock to data low to high
-
200
ns
CL = 10pF
tDLE
Delay time clock to LE low to high
50
-
ns
---
tWLE
Width of LE pulse
100
-
ns
---
tSLE
LE set-up time before clock rises
50
-
ns
---
BPOUT rise/fall time
10
1000
µs
CL = 350pF
-
100
µs
CL = 350pF
tBR, tBF
|tBR - tBF|
BPOUT rise and fall difference
Power-up sequence should be the following:
1. Connect ground.
2. Apply VDD.
3. Set all inputs (Data, CLK, EN, etc.) to a known state.
4. Apply VPP.
The VPP should not drop below VDD during operation.
Power-down sequence should be the reverse of the above.
Doc.# DSFP-HV66
C070313
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Supertex inc.
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HV66
Function Table
Inputs
Function
Load S/R,
R/L Shift
Load Latches
Transparent
Mode
Blank
Control
Outputs
Data
CLK
LE
BL
POL
DIR
Shift Reg
1, 2, ... 32
HVOUT
1, 2, ... 32
Data Out
BPOUT
L or H
↑
L
Ignore
Ignore
H
Data → Q1... → Q32
Ignore
Q32
Ignore
L or H
↑
L
Ignore
Ignore
L
Q1← ...Q32 ← Data
Ignore
Q1
Ignore
X
H or L
H
H
H
X
*...*
/*...*
No Change
H
X
H or L
H
H
L
X
*...*
*...*
No Change
L
L or H
↑
H
H
H
H
Data → Q1... → Q32
/*...*
Q32
H
L or H
↑
H
H
L
H
Data → Q1... → Q32
*...*
Q32
L
L or H
↑
H
H
H
L
Q1← ...Q32 ← Data
/*...*
Q1
H
L or H
↑
H
H
L
L
Q1← ...Q32 ← Data
*...*
Q1
L
X
X
X
L
L
X
X
L...L
Ignore
L
X
X
X
L
H
X
X
H...H
Ignore
H
Notes:
H
- High level
L
- Low level
X
- Don’t care
Ignore
- The state of the specific input or output is irrelevant to demonstrate the occurred event
↑
- Low to High transition
*
- Dependent on previous stage’s state before the last CLK or last LE high
Switching Waveforms
DATA
IN
Data Valid
50%
tSU
CLK
VIH
50%
VIL
tH
50%
50%
50%
tWL
50%
tWH
VOL
tDLH
VOH
50%
VOL
tDHL
50%
LE
tDLE
BPOUT
VOH
50%
VOL
tHOFF
VOH
50%
VOL
tHON
VIH
50%
50%
tBOFF
tBON
50%
50%
10%
VIL
4
VOHBP
90%
tBR
Doc.# DSFP-HV66
C070313
VIL
tSLE
HVOUT
w/ S/R HIGH
POL
(ASYNCH
w/ CLK)
VIH
50%
tWLE
HVOUT
w/ S/R LOW
VIL
VOH
50%
DATA
OUT
VIH
tBF
VOLBP
Supertex inc.
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HV66
44-Lead PQFP Pin Description
Pin #
Function
Pin #
Function
Pin #
Function
1
HVOUT11
16
HVOUT26
31
DIR
2
HVOUT12
17
HVOUT27
32
DATA IN
3
HVOUT13
18
HVOUT28
33
VPP
4
HVOUT14
19
HVOUT29
34
BPOUT
5
HVOUT15
20
HVOUT30
35
HVOUT1
6
HVOUT16
21
HVOUT31
36
HVOUT2
7
HVOUT17
22
HVOUT32
37
HVOUT3
8
HVOUT18
23
DATA OUT
38
HVOUT4
9
HVOUT19
24
GND
39
HVOUT5
10
HVOUT20
25
N/C
40
HVOUT6
11
HVOUT21
26
BL
41
HVOUT7
12
HVOUT22
27
POL
42
HVOUT8
13
HVOUT23
28
LE
43
HVOUT9
14
HVOUT24
29
VDD
44
HVOUT10
15
HVOUT25
30
CLK
44-Lead PLCC Pin Description
Pin
Function
Pin
Function
Pin
Function
1
HVOUT16
16
HVOUT31
31
HVOUT2
2
HVOUT17
17
HVOUT32
32
HVOUT3
3
HVOUT18
18
DATA OUT
33
HVOUT4
4
HVOUT19
19
GND
34
HVOUT5
5
HVOUT20
20
N/C
35
HVOUT6
6
HVOUT21
21
BL
36
HVOUT7
7
HVOUT22
22
POL
37
HVOUT8
8
HVOUT23
23
LE
38
HVOUT9
9
HVOUT24
24
VDD
39
HVOUT10
10
HVOUT25
25
CLK
40
HVOUT11
11
HVOUT26
26
DIR
41
HVOUT12
12
HVOUT27
27
DATA IN
42
HVOUT13
13
HVOUT28
28
VPP
43
HVOUT14
14
HVOUT29
29
BPOUT
44
HVOUT15
15
HVOUT30
30
HVOUT1
Doc.# DSFP-HV66
C070313
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Supertex inc.
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HV66
44-Lead PQFP Package Outline (PG)
10.00x10.00mm body, 2.35mm height (max), 0.80mm pitch
D
D1
E1 E
Note 1
(Index Area
D1/4 x E1/4)
44
1
e
b
θ1
Top View
View B
A
A2
Seating
Plane
A1
L
L1
Side View
L2
Gauge
Plane
θ
Seating
Plane
View B
Note:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
Symbol
MIN
Dimension
NOM
(mm)
MAX
A
A1
A2
b
D
D1
E
E1
1.95*
0.00
1.95
0.30
13.65*
9.80*
13.65*
9.80*
-
-
2.00
-
13.90
10.00
13.90
10.00
2.35
0.25
2.10
0.45
14.15*
10.20* 14.15* 10.20*
e
0.80
BSC
L
0.73
0.88
1.03
L1
L2
1.95
REF
0.25
BSC
θ
0O
3.5O
7O
JEDEC Registration MO-112, Variation AA-2, Issue B, Sep.1995.
* This dimension is not specified in the JEDEC drawing.
Drawings not to scale.
Supertex Doc. #: DSPD-44PQFPPG, Version C041309.
Doc.# DSFP-HV66
C070313
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Supertex inc.
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HV66
44-Lead PLCC Package Outline (PJ)
.653x.653in body, .180in height (max), .050in pitch
D
D1
.048/.042
x 45O
1 44
6
.150max
.056/.042
x 45O
40
Note 1
(Index Area)
.075max
E
E1
Note 2
e
.020max
(3 Places)
Top View
Vertical Side View
View
B
b1
A
A1
Base .020min
Plane
A2
Seating
Plane
b
Horizontal Side View
R
View B
Notes:
1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or
a printed indicator.
2. Actual shape of this feature may vary.
Symbol
Dimension
(inches)
A
A1
A2
b
b1
D
D1
E
E1
MIN
.165
.090
.062
.013
.026
.685
.650
.685
.650
NOM
.172
.105
-
-
-
.690
.653
.690
.653
MAX
.180
.120
.083
.021
.036†
.695
.656
.695
.656
e
.050
BSC
R
.025
.035
.045
JEDEC Registration MS-018, Variation AC, Issue A, June, 1993.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.
Supertex Doc. #: DSPD-44PLCCPJ, Version F031111.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
Supertex inc.
©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.
Doc.# DSFP-HV66
C070313
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1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com