D a ta S h e e t , R ev . 1 . 5 1, J u n e 20 0 7 TLE 7263E I n t e g r a t e d H S - C A N , L IN , L D O a n d HS Switch System Basis Chip Automotive Power Never stop thinking. Integrated HS-CAN, LIN, LDO and HS Switch System Basis Chip 1 TLE 7263E Overview Features • • • • • • • • • • • • • Two Low Drop Voltage Regulators Window watchdog Standard 16-bit SPI-interface Supports µController Stop Mode Sleep Mode (50µA) VBAT Monitoring and fail-safe output Overtemperature and short circuit protection Power on and undervoltage reset generator High side switch, 150 mA 4 Monitoring / wake-up inputs Exposed Pad Package AEC Qualified Green (RoHS Compliant) product PG-DSO-36-24 HS CAN Transceiver • • • • • CAN data transmission rate up to 1 MBaud Low power mode management Supports sleep and receive-only modes Bus wake-up capability via CAN message Bus pins are short circuit proof to ground and battery voltage LIN Transceiver • • • • • Single-wire transceiver Transmission rate up to 20 kBaud Compatible to LIN specification 1.3 and 2.0 Very low current consumption in Sleep Mode Short circuit proof to GND and battery Type Package TLE 7263E PG-DSO-36-24 Data Sheet Marking 2 Rev. 1.51, 2007-06-22 TLE 7263E Overview Dual-Voltage Regulator • • • Low-dropout voltage regulator, dual voltage-supply V1, 150 mA, 5 V ±2% for external devices, e.g. microcontrollers V2, 150 mA, 5 V ±2% for internal CAN module and external devices. Description The TLE 7263E is a monolithic integrated circuit in an enhanced power package. The IC is designed for CAN-LIN gateway applications. To support these applications the TLE 7263E covers smart power functions such as HSCAN transceiver and LIN transceiver for data transmission, dual low dropout voltage regulator (LDO) for external 5 V supply, and high-side switch as well as a 16-bit SPI (serial peripheral interface) to control and monitor the IC. There is also a window watchdog circuit with a reset feature, a fail-safe output, a voltage sensing input and a undervoltage reset feature implemented. The device offer low power modes in order to support modules directly connected to the battery (KL. 30). A wake-up from the low power mode is possible via a message on the bus or via the bi level sensitive monitoring/wake-up inputs. The integrated High-Side switch can also be used to periodically supply an external wake-up circuitry in the low power mode, by choosing a special function. The integrated bus transceivers offer a receive-only mode for software diagnosis functions. The IC is designed to withstand the severe conditions of automotive applications. Data Sheet 3 Rev. 1.51, 2007-06-22 TLE 7263E Pin Configuration 2 Pin Configuration GND 1 36 GND GND 2 35 TxDLIN NC 3 34 RxDLIN LIN 4 33 FSO MTS 5 32 WKO GND 6 31 CSN OUTHS 7 30 CLK VS 8 29 MON1 MON2 9 DI DO 10 MON3 TLE7263E DSO 36 - Exposed Pad cooling tab (GND) 28 27 STS 11 26 RO MON4 12 25 RxDCAN SI 13 24 TxDCAN GND 14 23 GND VCC1 15 22 CANL VCC2 16 21 SPLIT INT 17 20 CANH GND 18 19 GND Pinnout_7263_SO-36EP Figure 1 Data Sheet Pin Configuration (top view) 4 Rev. 1.51, 2007-06-22 TLE 7263E Pin Configuration Table 1 Pin Pin Definitions and Functions Symbol Function 9 10 11 12 MON1, MON2, MON3, MON4 Monitoring / Wake-Up Inputs; bi level sensitive inputs used to monitor signals coming from, for example, an external switch panel; also used as wake-up input during cyclic sensing in low power modes (MON4 is exempted from “cyclic sense” as this input is permanently active) 8 VS Power Supply Input; block to GND directly at the IC with ceramic capacitor; (ferrite recommended for better EMC behavior) 15 VCC1 Voltage Regulator Output (V1); 5 V supply; to stabilize block to GND with an external capacitor CQ ≥ 10 µF, ESR < 6 Ω 16 VCC2 Voltage Regulator Output (V2); 5 V supply; to stabilize block to GND with an external capacitor CQ ≥ 10 µF, ESR < 6 Ω 32 WKO Wake-Up Event Output; indicates wake up via monitoring inputs, CAN or LIN during Sleep or Stop Mode; active low; wake up sets device to Standby Mode 33 FSO Fail Safe Output; to supervise and control critical applications, high when watchdog is correctly served, low at any reset condition; active low 26 RO Reset Output; open drain output, integrated pull-up, active low 13 SI Sense Comparator Input; for monitoring of external voltages, to program the detection level connect external voltage divider 17 INT Interrupt Output; output to monitor sense comparator input condition; input for enabling the Flash Programming Mode (voltage to be applied > 7 V) 5 MTS Master Termination Switch; output used to turn-on the termination/pull-up resistor of a LIN master 34 RxDLIN LIN Transceiver Data Output; according to the ISO 9141 and LIN specification 1.3 and 2.0; push-pull output; LOW in dominant state 35 TxDLIN LIN Transceiver Data Input; according to ISO 9141 and LIN specification 1.3 and 2.0 Data Sheet 5 Rev. 1.51, 2007-06-22 TLE 7263E Pin Configuration Table 1 Pin Pin Definitions and Functions (cont’d) Symbol Function 4 LIN LIN Bus; Bus Line for the LIN interface, according to ISO 9141 and LIN specification 1.3 and 2.0 29 DISPI SPI Data Input; receives serial data from the control device; serial data transmitted to DI is a 16-bit control word with the Least Significant Bit (LSB) transferred first: the input has a pull-down and requires CMOS logic level inputs; DI will accept data on the falling edge of CLK-signal 28 DOSPI SPI Data Output; this tri-state output transfers diagnosis data to the control device; the output will remain 3-stated unless the device is selected by a low on Chip-Select-Not (CSN) 30 CLKSPI SPI Clock Input; clock input for shift register; CLK has an internal pull-down and requires CMOS logic level inputs 31 CSNSPI SPI Chip Select Not Input; CSN is an active low input; serial communication is enabled by pulling the CSN terminal low; CSN input should only be transitioned when CLK is low; CSN has an internal pull-up and requires CMOS logic level inputs 7 OUTHS High Side Switch Output; controlled via SPI, in SBC Sleep Mode controlled by internal cyclic sense function when selected 24 TxDCAN CAN Transmit Data Input; integrated pull-up 25 RxDCAN CAN Receive Data Output 21 SPLIT CAN Termination Output; to support the recessive voltage level of the bus lines 20 CANH CAN High Line Output 22 CANL CAN Low Line Input 27 STS Send-to-Sleep; to switch the SBC back into low current mode during cyclic wake GND 1, 2, 6,14, 18,19, 23,36 Ground 3 NC Not Connected Internally; leave open or connect to GND EP EP Exposed Pad; internally connected to GND; connect to GND on board Data Sheet 6 Rev. 1.51, 2007-06-22 TLE 7263E Block Diagram 3 Block Diagram VS OUTHS Interrupt control Drive + Protection INT CSN Early Warning VS Supervisor SI STS CLK SPI DI DO VCC1 Over Current Over voltage Oscillator Timebase + Band Gap V CC1 Reset Generator + Window Watchdog LDO 1 RO FSO V CC2 Over Current Over voltage MON1 LDO 2 MON2 HS-CAN Mode Control Wake-Up Logic MON3 V CC1 MON4 CANH Output Stage CANL Driver Diagnosis Logic Temp.Protection WKO TxDCAN + timeout VCC1 SPLIT MUX Receiver + Bus Failure Detection HS-CAN Transceiver VS Vs LIN Output Stage MTS LIN Mode Control Driver 30 kOhm RxDCAN Temp.Protection V CC1 TxDLIN Receiver Filter / Wake-Up RxDLIN LIN Transceiver GND Figure 2 Data Sheet blockdiagramm7263 Functional Block Diagram 7 Rev. 1.51, 2007-06-22 TLE 7263E Features 4 Features The TLE 7263E incorporates a lot of features, that are listed in Table 2 below. A short description of the features is given in “Operation Modes” on Page 9. Table 2 Truth Table of the TLE 7263E Feature SBC Active Mode SBC Standby Mode SBC Stop Mode SBC Sleep Mode CAN RxD-only Mode VCC, V1, 5 V VCC, V2, 5 V ON ON ON OFF ON ON ON/OFF ON/OFF OFF1) ON Reset RO ON ON ON OFF ON Window Watchdog ON ON ON/OFF OFF/[ON] ON Fail Safe Output ON ON ON OFF ON Sense input ON ON ON OFF ON Monitoring pins ON ON ON ON ON HS-switch ON ON ON OFF ON HS-cyclic-sense OFF OFF ON ON OFF 16-bit SPI ON ON ON OFF ON CAN/LIN wake-up via bus message OFF/“Sleep” ON ON ON OFF CAN Transmit ON/“Sleep” OFF OFF OFF OFF CAN Receive ON/“Sleep” OFF OFF OFF ON LIN Transmit ON/“Sleep” OFF OFF OFF ON LIN Receive ON/“Sleep” OFF OFF OFF ON RxDLIN L/H active low wake-up interrupt active low wake-up interrupt low L/H RxDCAN L/H active low wake-up interrupt active low wake-up interrupt low L/H INT output active low early warning active low early warning active low early warning low active low early warning WKO output OFF active low wake-up active low wake-up low OFF 1) In Sleep Mode the Vcc2 should be switched off. This is the default setting at the SPI Data Sheet 8 Rev. 1.51, 2007-06-22 TLE 7263E Features 4.1 Operation Modes This System Basis Chip (SBC) offers five main operation modes that are controlled via three mode select bits MS1, MS2 and MS3 within the SPI: SBC Active, Standby, Sleep and Stop mode, as well as CAN Receive-Only mode. After powering-up the SBC, it starts-up in SBC Standby Mode, waiting for the microcontroller to finish its startup and initialization sequences. From this transition mode the SBC can be switched via SPI command into the desired operating mode (The device should not be switched directly from Standby Mode to Sleep or Stop Mode). All modes are selected via SPI bits or certain operation conditions, e.g. external wake-up events. The SBC Active Mode, that is used in order to transmit and receive CAN and LIN messages, supports two additional sub-modes, “CAN Sleep” and “LIN Sleep”. During these sub-modes the SBC remains its voltage regulators running in order to supply external devices. Also, the line termination of the “sleeping” bus transceiver is turned-off respectively. During SBC Sleep Mode, the lowest power consumption is achieved, by having its main voltage regulator switched-off. As the microcontroller can not be supplied, the integrated window watchdog might be disabled in Sleep Mode via SPI bit. However, it can be turned-on for periodically waking-up the system, e.g. ECU, by generating a reset. In case an external microcontroller needs to be supplied with its quiescent current, the SBC Stop Mode can be chosen. In this mode the main voltage regulator remains active. Optionally, the second voltage regulator can be turned-on or off via the SPI prior to entering one of the respective power saving modes. The integrated window watchdog remains active until the microcontroller enters its power saving mode (“Stop Mode”). This power saving mode is assumed to be reached once the current consumption is below a certain threshold (see Watchdog current threshold, Table and “Window Watchdog, Reset” on Page 26). In both low power modes the internal bus transceivers, including the line termination, are turned off while the wake-up capabilities via bus message or monitoring pins are still active. The SBC offers Sleep and Stop Mode in conjunction with or without the Cyclic Sense/Wake feature. If the Cyclic Sense/Wake feature is selected, two possible states can be entered during Sleep/Stop Mode: HS-On and HS-Off (see text and respective state diagram). The Cyclic Sense feature can be used to supply an external wake-up circuitry periodically, and is entered upon activation via SPI command. In cyclic sense HS-On state, the High-Side switch is activated for a certain “on-time” and provides supply voltage at its OUTHS pin. Within this on-time the SBC starts sampling of the monitoring/wake-up lines. On-time as well as time period are programmable via the SPI control word. A wake-up at the monitoring / wake-up pins during the on-time as well as a message at the CAN or LIN bus lines automatically sets the TLE 7263E into SBC Standby mode, and turns-on the main voltage regulator VCC1. The digital RxDCAN/RxDLIN lines, that are monitored by the microcontroller during power saving, are pulled low with Data Sheet 9 Rev. 1.51, 2007-06-22 TLE 7263E Features respect to the wake-up source (CAN or LIN). Furthermore, the wake-up source is indicated within the SPI status word. Additionally, the wake-up capabilities of the monitoring / wake-up pins can be configured via SPI. If Cyclic Wake is entered upon SPI command, the High-Side switch is turned-on immediately (HS-On state), providing supply voltage at the OUTHS pin. Once the HSOn state is entered, a transition to the HS-Off state can be triggered by a pulse with a minimum width at the STS pin (see STS pulse width, Table ). The microcontroller fully controls the signal level at the STS pin, and this way determines the duration of the HSOn state. As of now the HS-Off state is automatically terminated according to the Cyclic Wake period selected via SPI, or by a CAN or LIN message. Start Up Power Up SBC Standby Mode Vcc1 ON SBC Stop Mode MS2 1 MS1 1 MS0 1 SBC Sleep Mode Vcc1 ON MS2 1 MS1 0 MS0 0 Vcc1 OFF SBC Active Mode MS2 0 MS1 1 MS0 1 Vcc1 ON SBC Active Mode: „CAN Sleep“ MS2 0 MS1 0 MS0 1 CAN RxD Only Vcc1 ON MS2 1 SBC Active Mode: „LIN Sleep“ MS2 0 MS1 1 MS0 0 MS1 0 MS0 1 Vcc1 ON LIN RxD Only MS2 1 Vcc1 ON MS1 1 MS0 0 Vcc1 ON modes_TLE7263 Figure 3 Data Sheet Functional Overview “SBC Operation Modes” 10 Rev. 1.51, 2007-06-22 TLE 7263E Features 4.2 SBC Sleep Mode without Cyclic Sense In order to reduce the current consumption to a minimum, the SBC offers a Sleep Mode without Cyclic Sense (see Figure 4). This mode is entered via SPI command, and turnsoff the integrated bus transceivers and respective termination, main voltage regulator as well as the High-Side switch. Upon a voltage level change at the monitoring/wake-up pins or by a CAN or LIN message the SBC Sleep Mode will be terminated and the SBC Standby Mode will automatically be entered. SBC Active Mode MS2 0 MS1 0/1 MS0 0/1 SBC Standby Mode Vcc1 ON Vcc1 ON µController SPI-Command: - disable „cyclic sense function“ via SPI Timing Bits - select SBC Sleep Mode via SPI Mode Bits - window watchdog activation / deactivation via SPI [can remain active as periodic reset timer] Start Up Power Up transition caused by: - event at MONx inputs - CAN message - LIN message [SPI indicates source] Initialization of MONx inputs 1) SBC Sleep Mode MS2 1 MS1 0 MS0 0 Vcc1 OFF HS-Switch = OFF 1) if initialization fails, device is switched into SBC Standby mode sleep_TLE7263 Figure 4 State Diagram “SBC Sleep Mode without Cyclic Sense” Note: To switch into Low Power Mode from Standby Mode the device should be switched into Normal Mode first. This is required to reset the CAN and LIN transceiver to ensure correct wakeup as well as to ensure the correct function of the RO pin when going to Sleep Mode. The time the device is in Normal Mode before going to Low Power Mode should be long enough that the Vcc2 is up. This can be released by a wait time or by reading the status of Vcc2 via SPI (bit13). Data Sheet 11 Rev. 1.51, 2007-06-22 TLE 7263E Features 4.3 SBC Sleep Mode with Cyclic Sense In order to reduce the current consumption to a minimum, but still supply a wake-up circuit periodically, the SBC offers a Sleep Mode with Cyclic Sense (see Figure 5). This mode is entered via SPI command, and turns-off the integrated bus transceivers and respective termination, as well as the main voltage regulator. The High-Side switch is turned-on according to the SPI timings setting for cyclic sense, as there is the cyclic sense period and the on-time. Upon a voltage level change at the monitoring/wake-up pins or by a CAN or LIN message the SBC Sleep Mode will be terminated and the SBC Standby Mode will automatically be entered. The respective RxD pin of the transceiver that generated the wake-up will be pulled low. SBC Active Mode MS2 0 MS1 0/1 MS0 0/1 SBC Standby Mode Vcc1 ON Vcc1 ON µController SPI-Command: - select „cyclic sense period“ via SPI Timing Bits - select HS-Switch on-time via SPI „On-Time Bit“ - select SBC Sleep Mode via SPI Mode Bits - window watchdog activation / deactivation via SPI [can remain active as periodic reset timer] Initialization of MONx inputs 1) Start Up Power Up transition caused by: - event at MON1 - 3 inputs [only during HS-ON state] - event at MON4 input - CAN message - LIN message [SPI indicates source] SBC Sleep Mode MS2 1 MS1 0 MS0 0 Vcc1 OFF HS-Switch = OFF „sense period“ after „on-time“ HS cyclic sense MS2 1 MS1 0 MS0 0 Vcc1 OFF 1) if initialization fails, device is switched into SBC Standby mode HS-Switch = ON cyclic_sense_sleep_TLE7263 Figure 5 Data Sheet State Diagram “SBC Sleep Mode with Cyclic Sense” 12 Rev. 1.51, 2007-06-22 TLE 7263E Features 4.4 SBC Sleep Mode with Cyclic Wake The SBC Sleep Mode has the advantage of reducing the current consumption to a minimum. During this mode the integrated voltage regulator for external supply is turned off. In case the connected microcontroller needs to get activated periodically, the Cyclic Wake feature in combination with the SBC Sleep Mode can be activated (see Figure 6). SBC Active Mode MS2 0 MS1 0/1 MS0 0/1 SBC Standby Mode Vcc1 ON Start Up Power Up Vcc1 ON µController SPI-Command: - select „cyclic wake“ via SPI Bit - select „cyclic wake period“ via SPI Timing Bits - select HS-Switch on-time via SPI „On-Time Bit“ - select SBC Sleep Mode via SPI Mode Bits - window watchdog activation / deactivation via SPI SBC Sleep Mode MS2 1 Initialization of MONx inputs 1) MS1 1 select SBC operating mode Vcc1 OFF MS0 1 HS-Switch = OFF automatic transition by: - cyclic wake period - CAN message - LIN message STS µC 2) HS Cyclic Wake MS2 1 sampling of MON1…3 inputs [MON4 active permanently] MS1 1 MS0 1 Vcc1 ON Data Sheet cyclic wake-up HS-Switch = ON 1) if initialization fails, device is switched into SBC Standby mode Figure 6 WKO cyclic_wake_sleep_TLE7263 State Diagram “SBC Sleep Mode with Cyclic Wake” 13 Rev. 1.51, 2007-06-22 TLE 7263E Features 4.5 SBC Stop Mode without Cyclic Sense The SBC Stop Mode has the advantage of reducing the current consumption to a minimum, while supplying the microcontroller with its quiescent current during its power saving mode (“Stop”). This mode is entered via SPI command, and turns-off the integrated bus transceivers and respective termination, but the main voltage regulator remains active. A voltage level change at the monitoring / wake-up pins will, in contrast to the behavior in Sleep Mode, generate a pulse at the WKO pin that is monitored by the microcontroller, e.g. at an external interrupt input. In case the wake-up event was a CAN or LIN message, the respective RxD pin will be pulled low. (The microcontroller itself has to take care of switching SBC modes after a wake-up event notification (see Figure 7).) SBC Active Mode MS2 0 MS1 0/1 MS0 0/1 SBC Standby Mode Vcc1 ON Vcc1 ON µController SPI-Command: - disable „cyclic sense function“ via SPI Timing Bits - select SBC Stop Mode via SPI Mode Bits - window watchdog activation / deactivation via SPI [„off“ once current consumption below threshold] Start Up Power Up transition caused by: - event at MONx inputs - CAN message - LIN message [SPI indicates source] wake event notification [to µC]: - CAN msg. => RxDCAN (low) - LIN msg. => RxDLIN (low) - MONx => WKO Initialization of MONx inputs 1) SBC Stop Mode MS2 1 MS1 1 MS0 1 Vcc1 ON 1) if initialization fails, device is switched into SBC Standby mode HS-Switch = OFF stop_TLE7263 Figure 7 Data Sheet State Diagram “SBC Stop Mode without Cyclic Sense” 14 Rev. 1.51, 2007-06-22 TLE 7263E Features 4.6 SBC Stop Mode with Cyclic Sense The SBC Stop Mode has the advantage of reducing the current consumption to a minimum, while supplying the microcontroller with its quiescent current during its power saving mode (“Stop”). This mode is entered via SPI command, and turns-off the integrated bus transceivers and respective termination, but the main voltage regulator remains active. The High-Side switch is turned-on according to the SPI timings setting for cyclic sense, as there is the cyclic sense period and the on-time. A voltage level change at the monitoring/wake-up pins will, in contrast to the behavior in Sleep Mode, generate a pulse at the WKO pin that is monitored by the microcontroller, e.g. at an external interrupt input. In case the wake-up event was a CAN or LIN message, the respective RxD pin will be pulled low. (The microcontroller itself has to take care of switching SBC modes after a wake-up event notification (see Figure 8).) SBC Active Mode MS2 0 MS1 0/1 MS0 0/1 SBC Standby Mode Vcc1 ON Start Up Power Up Vcc1 ON µController SPI-Command: - select „cyclic sense period“ via SPI Timing Bits - select HS-Switch on-time via SPI „On-Time Bit“ - select SBC Stop Mode via SPI Mode Bits - window watchdog activation / deactivation via SPI [„off“ once current consumption below threshold] transition caused by: - event at MON1 - 3 inputs [only during HS-ON state] - event at MON4 input - CAN message - LIN message [SPI indicates source] Initialization of MONx inputs 1) SBC Stop Mode MS2 1 MS1 1 MS0 1 Vcc1 ON wake event notification [to µC]: - CAN msg. => RxDCAN (low) - LIN msg. => RxDLIN (low) - MONx => WKO HS-Switch = OFF “sense period“ after „on-time“ 1) if initialization fails, device is switched into SBC Standby mode HS Cyclic Sense MS2 1 MS1 1 MS0 1 Vcc1 ON HS-Switch = ON cyclic_sense_stop_TLE7263 Figure 8 Data Sheet State Diagram “SBC Stop Mode with Cyclic Sense” 15 Rev. 1.51, 2007-06-22 TLE 7263E Features 4.7 SBC Stop Mode with Cyclic Wake The SBC Stop Mode has the advantage of reducing the current consumption to a minimum, while supplying the microcontroller with its quiescent current during its power saving mode (“Stop”). This mode is entered via SPI command, and turns-off the integrated bus transceivers and respective termination, but the main voltage regulator remains active. In contrast to Cyclic Sense the HS-On state is entered once Cyclic Wake is selected, immediately providing supply voltage at the OUTHS pin. The microcontroller determines the duration of the HS-On state via the STS input pin (see Figure 9). Further transitions from that HS-Off into the HS-On state are done by the selected cyclic wake period or by a bus message. The microcontroller is notified by the WKO (Wake-Up Output) that the HS-On state has been entered. Further notification is done in the same way as for Cyclic Sense in Stop Mode. SBC Active Mode MS2 0 MS1 0/1 MS0 0/1 SBC Standby Mode Vcc1 ON Start Up Power Up Vcc1 ON µController SPI-Command: - select „cyclic wake“ via SPI Bit - select „cyclic wake period“ via SPI Timing Bits - select HS-Switch on-time via SPI „On-Time Bit“ - select SBC Stop Mode via SPI Mode Bits - window watchdog activation / deactivation via SPI [„off“ once current consumption below threshold] SBC Stop Mode MS2 1 Initialization of MONx inputs 1) MS1 1 select SBC operating mode Vcc1 ON MS0 1 HS-Switch = OFF automatic transition by: - cyclic wake period via STS pin - CAN message or - LIN message after „on-time“ STS µC 2) HS Cyclic Wake MS2 1 sampling of MON1…3 inputs [MON4 active permanently] MS1 1 MS0 1 Vcc1 ON WKO cyclic wake-up HS-Switch = ON µC wake-up inputs 1) if initialization fails, device is switched into SBC Standby mode 2) Figure 9 Data Sheet window watchdog activated automatically once current threshold is exceeded cyclic_wake_stop_TLE7263 State Diagram “SBC Stop Mode with Cyclic Wake” 16 Rev. 1.51, 2007-06-22 TLE 7263E Features Continuous Timer Mode (CTM) for “Cyclic Wake Timer” Upon start of the “cyclic wake timer” in Cyclic Wake Mode the operating mode might be changed to “SBC Active Mode” by the microcontroller, e.g. in order to transmit data via the CAN or LIN transceiver. In this case the timer continues running with the selected period started in Cyclic Wake Mode. This behavior guarantees the periodic generation of a wake-up signal at the WKO pin, even in case of a mode switch. However, this provides that the time spent in SBC Active Mode is not exceeding the selected period. Should a time-out (end of selected period) occur in SBC Active Mode before the Cyclic Wake Mode is re-entered, the SBC will generate an interrupt signal at its WKO pin if the CTM feature is enabled via the respective SPI bit (see Figure 11). When the CTM feature is set in the SPI, a wake-up event at the CAN bus in “SBC Active CAN Sleep” mode or at the LIN bus in the “SBC Active LIN Sleep” mode results in switching WKO “low” in addition to switching the RxD to “low”. 4.8 Dual Low Dropout Voltage Regulator The dual low dropout voltage regulator integrated in the TLE 7263E is able to drive external as well as internal loads, e.g. CAN-circuit supplied via VCC2, even in case of a bus short circuit. Its output voltage tolerance is better than ±2%. The maximum output current for external loads is limited to 150 mA (VCC1), e.g. for microcontroller supply, and 150 mA (VCC2) for internal CAN module and, e.g. for external sensor supply. The two voltage regulator outputs are protected against overload and overtemperature. The thermal pre-warning flag might be used by the microcontroller to reduce the power dissipation of the TLE 7263E by switching off functions of minor priority until the temperature threshold of the thermal shutdown is reached. An external reverse current protection is required at the pin VS to prevent the output capacitor from being discharged by negative transients or low input voltage. A capacitor of 10 µF at the supply voltage input VS buffers the input voltage. In combination with the required reverse polarity diode this prevents the device from detecting power down conditions in case of negative transients on the supply line. Stability of the output voltage is guaranteed for output capacitors CQ ≥ 100 nF, nevertheless it is recommended to use capacitors CQ ≥ 10 µF to buffer the output voltage and therefore improve the reset behavior at input voltage transients. Data Sheet 17 Rev. 1.51, 2007-06-22 TLE 7263E Features 4.9 CAN Transceiver The TLE 7263E is optimized for high speed data transmission up to 1 MBaud in automotive applications and is compatible to the ISO 11898 standard. It works as an interface between the CAN protocol controller and the physical bus lines. This HS-CAN module also supports extended bus error detection via a general error flag as well as individual notification flags, e.g. temperature shutdown and TxD time-out flag, within the SPI. To reduce EMI the dynamic slopes of the CANL and CANH signals both are limited and symmetric. This allows the use of an unshielded twisted or parallel pair of wires for the bus. Furthermore there is implemented a time-out feature to prevent the bus from being blocked by a permanently dominant TxD input signal. Both, the CANL and CANH output stage are automatically disabled after the delay time tTxD. In order to protect the transceiver output stages from being damaged by shorts on the bus lines, current limiting circuits are integrated. The CANL and CANH output stage respectively are protected by an additional temperature sensor, that disables them as soon as the junction temperature exceeds the maximum value. During the temperature shut-down condition of the CAN output stages receiving messages from the bus lines is still possible. Wake-Up Indication: A bus wake-up via a CAN message (minimum dominant time t > tWU) from low power mode sets the RxD pin and the WKO pin to low. In addition, the Vcc2, which supplies the CAN output stage is switched ON.The CAN transceiver has to be enabled to reset the wake-up capability after a bus wake event and after power-up. Bus Failure Flag: signalizes a bus line short circuit condition to GND, VS or VCCx via SPI bit 11 in the SPI Output Data “CAN Bus Failure”. Remarks: Flag is set after four consecutive recessive to dominant cycles on pin TxD when trying to drive the bus dominant. The bus failure flag is cleared upon 4 recessive to dominant edges at TxD without failure condition. Local Failure Flag: signalizes the local failure conditions listed in the text below via SPI bit 10 in the SPI Output Data “CAN Local Failure”. Remark: Flag is cleared upon dominant level at RxD while TxD is recessive. General: release of the transmitter stage only after transition into CAN RxD Only mode and transition back into SBC Active Mode. TxD Dominant Failure Detection At permanent dominant signal for t > tTxD at TxD the local failure flag is set and the transmitter stage is turned off. Remarks: none Data Sheet 18 Rev. 1.51, 2007-06-22 TLE 7263E Features RxD Permanent Recessive Clamping Internal RxD signal does not match signal at RxD pin because the RxD pin is pulled to HIGH (permanent HIGH). This results in setting the local failure flag and disabling of the receiver stage Remark: the flag is cleared when RxD signal gets dominant. TxD to RxD Short Circuit Caused by a short circuit between RxD and TxD. The local failure flag is set and the transmitter stage is disabled. Remark: the flag is cleared once the short circuit condition is removed. Bus Dominant Clamping At a permanent dominant signal at the CAN bus for t > tBUS the local failure flag is set. Remark: none Over Temperature Detection Once the maximum junction temperature at the driving stages exceeded, the local failure flag is set and the transmitter stage is disabled. Remark: the flag is cleared once RxD gets dominant. Bus only released after the next dominant bit in TxD. Split Circuit The split circuitry is activated during SBC Active and RxD Only Mode and deactivated (SPLIT pin high omic) during SBC Sleep, Stop and Standby Mode. The SPLIT pin is used to stabilize the recessive common mode signal in SBC Active Mode and RxD Only mode. This is realized with a stabilized voltage of 0.5 VCC2 at the SPLIT pin. A correct application of the SPLIT pin is shown in Figure 10. The split termination for the left and right node is realized with two 60 Ohm resistances and one 10nF capacitor. The center node in this example is a stub node and the recommended value for the split resistances is 1.5 kOhm. Data Sheet 19 Rev. 1.51, 2007-06-22 TLE 7263E Features CANH CANH SPLIT 10nF TLE 7263 R 60Ohm 60Ohm TLE 7263 R CAN Bus split termination split termination 60Ohm SPLIT 10nF 60Ohm CANL CANL 10nF split termination at stub 1,5 kOhm CANH 1,5 kOhm SPLIT CANL TLE 7263 R Figure 10 4.10 Application of the SPLIT pin for normal nodes and one stub node LIN Transceiver The TLE 7263E offers a transceiver, which is compatible to ISO 9141 and LIN specification 2.0. For fail safe reasons the transceiver already has a pull-up resistor of 30 kΩ implemented. In order to achieve the required timing for the dominant to recessive transition of the bus signal an additional external termination resistor of 1 kΩ is required, when the LIN node is used as a master. This termination resistor will automatically be turned off via the “Master Termination Switch” pin (MTS) once the LIN module enters LIN Sleep Mode or when the SBC enters Sleep Mode. The transceiver is protected against short to battery and short to GND. For LIN automotive applications in the United States a dedicated mode by the name “Low Slope Mode” can be used. This mode limits the maximum data transmission rate to 10.4 kBaud by switching to a different slew rate. Operating with the default slew rate at up to 20 kBaud may cause interferences with the AM radio band. A bus wake-up via a LIN message (minimum dominant time t > twake) from low power mode sets the RxD pin and the WKO pin to low. in addition the MTS is switched ON. The LIN transceiver has to be enabled to reset the wake-up capability after a bus wake event and after power-up. In case of a “TxD dominant time out failure” or a “transmitter thermal shutdown” the SPI bit 9 is set. After a SPI read-out this bit will be reset unless one of the failure conditions is still present. Note: In case of a short to GND on the LIN bus a RxD dominant signal is generated by the SBC. In the case that RxD is dominant the device can not go into low power mode from normal mode. Data Sheet 20 Rev. 1.51, 2007-06-22 TLE 7263E Features 4.11 SPI (Serial Peripheral Interface) The 16-bit wide Programming or Input Word (see Table 3) is read in via the data input DI, which is synchronized with the clock input CLK supplied by the µC. The Diagnosis or Output Word appears synchronously at the data output DO (see Figure 10). The transmission cycle begins when the chip is selected by the Chip Select Not input CSN (“low” active). After the CSN input returns from L to H, the word that has been read in becomes the new control word. The DO output switches to tristate status at this point, thereby releasing the DO bus for other usage. The state of DI is shifted into the input register with every falling edge on CLK. The state of DO is shifted out of the output register after every rising edge on CLK. The number of received input clocks is supervised by a modulo-16 operation and the Input / Control Word is discarded in case of a mismatch. This error is flagged by the WKO set to “low” and in the following SPI output by a “high” at the data output (DO pin) before the first rising edge of the clock is received. MSB Input Data LSB 15 14 13 12 11 10 WD VCC2 On/Off On/off 9 8 7 6 5 SI MON4 MON3 MON2 MON1 LIN Reset Reset On/Off On/Off On/Off On/Off On/Off 10.4k Delay Thres. OUTHS On/Off Reserved CTM On/Off Select OUTHS „off“ Reserved OUTHS On-Time 0 Cyclic Sense / Wake 3 2 CS1 CS0 MS2 Configuration Select Configuration Registers Res. 4 Cyclic Sense / Wake Timing Bit Position: 9 .. 5 Window Watchdog Timing Bit Position: 10 .. 5 00 1 MS1 0 MS0 Mode Selection Bits not valid 000 01 Active CAN Sleep 001 10 Active LIN Sleep 010 11 Active (Watchdog Trigger Register) Sleep CAN RxD Only LIN RxD Only Stop SPI_Bit_Settings Figure 11 Data Sheet 011 100 101 110 111 16-Bit SPI Input Data / Control Word 21 Rev. 1.51, 2007-06-22 TLE 7263E Features Table 3 SPI Input Data Bits IBIT Input Data 0…2 Mode Selection 3…4 Configuration Selection (determine meaning of “Configuration Setting Bits”) 5 … 13 Configuration Settings (meaning based on “Configuration Selection Bits”) 14 VCC2 Activation (power saving modes only) 15 Window Watchdog “on”/“off” (power saving modes only) Table 4 Mode Selection Bits MS2 MS1 MS0 Mode Selection: SBC Mode 0 0 0 “reserved” / not valid 0 0 1 SBC Active Mode: “CAN Sleep” 0 1 0 SBC Active Mode: “LIN Sleep” 0 1 1 SBC Active Mode (CAN & LIN “on”) 1 0 0 SBC Sleep (CAN, LIN & VReg “off”) 1 0 1 SBC Active mode : CAN Transceiver: RxD-Only 1 1 0 SBC Active mode : LIN Transceiver: RxD-Only 1 1 1 SBC Stop Mode (CAN & LIN “off”) Table 5 Configuration Selection Bits CS1 CS0 Configuration Selection 0 0 General Configuration 0 1 Integrated Switch Configuration 1 0 Cyclic Sense / Wake Configuration 1 1 Window Watchdog Configuration Data Sheet 22 Rev. 1.51, 2007-06-22 TLE 7263E Features Table 6 General & Integrated Switch Configuration Pos. General Configuration1) Integrated Switch Configuration2) 5 Reset Threshold (see Table : “Reset Generator”, “0” = VRT1 / “1” = VRT2) OUTHS “on” / “off” 6 Reset Delay (“0” = 5 ms / “1” = 0.5 ms) “reserved” / not used 7 LIN “Low Slope Mode” (10.4 kBaud) “reserved” / not used 8 MON1 Input Wake-Up Capability “reserved” / not used 9 MON2 Input Wake-Up Capability “reserved” / not used 10 MON3 Input Wake-Up Capability “reserved” / not used 11 MON4 Input Wake-Up Capability “reserved” / not used 12 Sense Input (SI) “on” / “off” “reserved” / not used 13 “reserved” / not used “reserved” / not used 1) “1” = ON (enable), “0” = OFF (disable) 2) “1” = ON, “0” = OFF Cyclic Sense / Wake & Window Watchdog Period Settings1) Table 7 Pos. Cyclic Sense / Wake Configuration Window Watchdog Configuration 5 Cyclic Period Bit 0 (T0) Watchdog Period Bit 0 (T0) 6 Cyclic Period Bit 1 (T1) Watchdog Period Bit 1 (T1) 7 Cyclic Period Bit 2 (T2) Watchdog Period Bit 2 (T2) 8 Cyclic Period Bit 3 (T3) Watchdog Period Bit 3 (T3) 9 Cyclic Period Bit 4 (T4) Watchdog Period Bit 4 (T4) 10 Cyclic Sense / Wake Selection Watchdog Period Bit 5 (T5) (“0” = Cyclic Sense / “1” = Cyclic Wake) 11 OUTHS On-Time Selection (“0” = 500 µs / “1” = 100 µs) 12 Cyclic Wake Mode only: “reserved” / not used Select OUTHS “off” via STS / On-Time (“0” = via STS / “1” = via HS On-Time) 13 Continuous Timer Mode (incl. WKO) (“0” = “off” / “1” = “on” ) “0” [mandatory] “reserved” / not used 1) “1” = ON, “0” = OFF Data Sheet 23 Rev. 1.51, 2007-06-22 TLE 7263E Features Table 8 Cyclic Sense / Wake Period Settings T4 T3 T2 T1 T0 Cyclic Sense or Cyclic Wake Period 0 0 0 0 0 Cyclic Sense / Wake “off” 0 0 0 0 1 16 ms 0 0 0 1 0 32 ms 0 0 0 1 1 48 ms 0 0 1 0 0 64 ms 0 0 1 0 1 80 ms 0 0 1 1 0 96 ms … … … … … … ms 1 1 1 1 1 496 ms Table 9 Window Watchdog Reset Period Settings T5 T4 T3 T2 T1 T0 Window Watchdog Reset Period 0 0 0 0 0 0 “not a valid selection” 0 0 0 0 0 1 16 ms 0 0 0 0 1 0 32 ms 0 0 0 0 1 1 48 ms 0 0 0 1 0 0 64 ms 0 0 0 1 0 1 80 ms 0 0 0 1 1 0 96 ms 0 … … … … … … ms 1 1 1 1 1 1 1008 ms Data Sheet 24 Rev. 1.51, 2007-06-22 TLE 7263E Features Table 10 SPI Output Data Pos. Output Data “active”1) Output Data “after wake-up”2) 0 VCC1 Temperature Prewarning VCC1 Temperature Prewarning 1 HS Overcurrent HS Overcurrent 2 OUTHS UV / Temp. Shut-Down OUTHS UV / Temp. Shut-Down 3 Window Watchdog Reset Window Watchdog Reset 4 MON1 Logic Input Level Wake-Up via MON1 5 MON2 Logic Input Level Wake-Up via MON2 6 MON3 Logic Input Level Wake-Up via MON3 7 MON4 Logic Input Level Wake-Up via MON4 8 MONx Initialization Failure MONx Initialization Failure 9 LIN Failure Bus Wake-Up via LIN Msg. 10 CAN Local Failure Bus Wake-Up via CAN Msg. 11 CAN Bus Failure End of Cyclic Wake Period 12 14 VCC1 Fail (active low) VCC2 Fail (active low) VINT Fail (active low) VCC1 Fail (active low) VCC2 Fail (active low) VINT Fail (active low) 15 “reserved” / not used “reserved” / not used 13 1) “1” = ON (enable), “0” = OFF (disable) 2) “1” = ON, “0” = OFF Data Sheet 25 Rev. 1.51, 2007-06-22 TLE 7263E Features 4.12 Window Watchdog, Reset When the output voltage Vcc1 exceeds the reset threshold voltage the reset output RO is switched HIGH after a delay time of typ. 5 ms. This is necessary for a defined start of the microcontroller when the application is switched on. As soon as an undervoltage condition of the output voltage (VCC1 < VRT) appears, the reset output RO is switched LOW again. The LOW signal is guaranteed down to an output voltage VCC1 ≥ 1 V. Please refer to Figure 19, Reset Timing Diagram. After the above described delayed reset (LOW to HIGH transition of RO) the window watchdog circuit is started by opening a long open window of typ. 64 ms. The long open window allows the microcontroller to run its initialization sequences and then to trigger the watchdog via the SPI. A watchdog trigger is detected as a write access to the “window watchdog period bit field” within the SPI control word. In order to distinguish the watchdog from the cyclic sense/wake timing register the “Configuration Select Bits” needs to be set accordingly (see “SPI (Serial Peripheral Interface)” on Page 21). The trigger is accepted when the CSN input becomes HIGH after the transmission of the SPI word. A correct watchdog trigger results in starting the window watchdog by opening a closed window with a width of 50% of the selected window watchdog reset period. This period, selected via the window watchdog timing bit field, is in the range between 16 ms and 1008 ms. This closed window is followed by a open window, with a width of 50% of the selected period. From now on the microcontroller has to service the watchdog by periodically writing to the window watchdog timing bit field. This write access has to meet the open window. A correct watchdog service immediately results in starting the next closed window (see Figure 17 "Watchdog Time-Out Definitions" on Page 54, safe trigger area). Should the trigger signal not meet the open window a watchdog reset is created by setting the reset output RO low (see Reset delay time tRD). Then the watchdog again starts by opening a long open window. In addition, a “window watchdog reset flag” is set within the SPI until the next successful watchdog trigger to monitor a watchdog reset. For fail safe reasons the TLE 7263E is automatically switched in SBC Standby mode if a watchdog trigger failure occurs. This minimizes the power consumption in case of a permanent faulty microcontroller. In case of a watchdog reset the watchdog immediately starts with a long open window in SBC Standby Mode. When entering a low power mode the watchdog can be requested to be disabled via an SPI bit (see “SPI (Serial Peripheral Interface)” on Page 21). Upon this request the watchdog is only turned off once the current consumption at VCC1 falls below the “watchdog current threshold”. Data Sheet 26 Rev. 1.51, 2007-06-22 TLE 7263E Features 4.13 Sense Comparator using Sense Input SI and Interrupt Output INT The sense comparator (early warning function) compares a voltage defined by the user to an internal reference voltage. Therefore the voltage to be supervised has to be scaled down by a voltage divider in order to compare it to the internal sense threshold VSIth. This feature can be used e.g. to supervise the battery voltage in front of the reverse protection diode. The microcontroller is given a prewarning before an undervoltage reset due to low input voltage occurs. The prewarning is flagged by setting the interrupt output INT low in SBC Active, Standby, and Stop, as well as in CAN Receive - Only Mode, when activated by SPI. In SBC Sleep Mode the sense function is inactive. Calculation of the voltage divider can be easily done since the sense input current can be neglected. An internal blanking time prevents from false triggering due to line transients. Further improvement is possible by the use of an external ceramic capacitor at the SI pin (see Figure 22, Application Circuit). 4.14 VINT/VCC Fail Detection via SPI Bit Should the internal supply voltage become lower than the internal threshold VINT, th (typ. 2.5 V) the VINT-Fail, threshold SPI bit will be reset in order to indicate the low voltage condition. All other SPI settings are also reset by this condition. The VINT Fail feature can also be used to give an indication when the ECU has been changed and therefore a presetting routine of the microcontroller has to be started. Further there is also a VCC monitor implemented, where the VCCx is compared to the threshold voltage VCCx-Fail, threshold and the VCC SPI bit is reset accordingly. This monitoring is only available during voltage-regulator operation. 4.15 Monitoring / Wake-Up Inputs MON1/2/3/4 and Wake-Up Output WKO In addition to a wake-up from SBC Sleep mode via the CAN or LIN bus lines it is also possible to wake-up the TLE 7263E from low power mode via the monitoring/wake-up inputs. These inputs are sensitive to a transition of the voltage level, either from high to low or vice versa. Monitoring is available in Active Mode and indicates the voltage level of the inputs. A positive or negative voltage edge at MONx in SBC Sleep or Stop Mode results in setting the output WKO low to signal a wake-up. After a wake-up via MONx the first transmission of the SPI diagnosis word in SBC Standby mode indicates the wake-up source. Further SPI status word transmissions show the logic level of the monitoring inputs. When switching the TLE 7263E into SBC Sleep mode (cyclic sense feature activated) the voltage level at the wake-up inputs is sensed 2 times to initialize the reference voltage. Should this initialization fail (2 samples are unequal) the device is automatically Data Sheet 27 Rev. 1.51, 2007-06-22 TLE 7263E Features set in SBC Standby mode and the initialization error is shown indicated in the SPI status word. To have a defined level at a floating MONx pin a hold current is implemented. For high level at MONx a pull up current IPU,MON is driven out of the MONx pin, for low level at MONx a pull down current IPD,MON is drawn into the MONx pin. 4.16 High Side Switch The high side output OUTHS is able to switch loads up to 150 mA. Its on-resistance is 2.5 Ω typ. @ 25 °C. In SBC Active, Standby, as well as in CAN and LIN Receive-Only mode the high side output is switched on and off, respectively via an SPI input bit. To supply external wake-up circuits in SBC Sleep Mode the output OUTHS can be periodically switched on by the TLE 7263E itself. How Cyclic Sense works and how it is activated is described in detail in “Operation Modes” on Page 9. Beside the cyclic sense period can the on-time of the OUTHS be programmed to either 500 µs (default setting) or 100 µs via SPI input bit. OUTHS undervoltage, temperature shutdown, overcurrent as well as a temperature pre-warning is indicated by the SPI status word. The OUTHS is protected against short circuit and overload. As soon as the undervoltage condition of the supply voltage is met (VS < VUVOFF), the switch is automatically disabled by the undervoltage lockout circuit. Moreover the switch is automatically disabled when a reset or watchdog reset occurs. 4.17 Fail Safe Feature The output FSO becomes HIGH when the watchdog is correctly serviced by the microcontroller for the fourth time. As soon as either an undervoltage reset or watchdog reset occurs, it is set LOW again. This feature is very useful to control critical applications independent of the microcontroller e.g. to disable the power supply in case of a microcontroller failure. 4.18 Send to Sleep Input STS During Cyclic Wake the STS input is used to switch the SBC back to a low current mode (High-Side switch “off”) when the microcontroller has completed its tasks during the periodic wake-up phase, and before it enters its power saving mode (“Stop”) again. 4.19 Flash Program Mode For flash programming it is useful to disable the window watchdog function. This can be done by applying a voltage of VINT > 7.0 V at pin INT. This is useful e.g. if the flashmemory of the micro has to be programmed and therefore a regular watchdog triggering is not possible. Data Sheet 28 Rev. 1.51, 2007-06-22 TLE 7263E Features Additionally, the transmission rate of the integrated LIN transceiver will be changed to maximal 150 kBaud. The Sense Comparator using Sense Input and Interrupt Output INT can not be used with Flash Program Mode. The Sense Input feature must be switched off via SPI. Hints for Unused Pins • • • • • SI: connect to GND OUTHS: leave open MON1/2/3/4: connect to GND INT / WKO: leave open RO / FSO: leave open Data Sheet 29 Rev. 1.51, 2007-06-22 TLE 7263E General Product Characteristics 5 General Product Characteristics 5.1 Maximum Ratings Table 11 Absolute Maximum Ratings Parameter Symbol Limit Values Unit Remarks Min. Max. VS VCC1, VCC2 VCANH/L -0.3 40 V – -0.3 5.5 V – -27 40 V – VSPLIT VWK/SI VO -27 40 V – -27 40 V – -27 VS + 0.3 V – Logic input voltages (DI, CLK, CSN, STS, TxD) VI -0.3 VCC + 0.3 V 0 V<VS<24V 0 V<VCC<5.5V Logic output voltage (DO, RO, INT, RxD, FSO, WKO) VDRI,RD -0.3 VCC + 0.3 V 0 V<VS<24V 0 V<VCC<5.5V Input voltage at Pin INT VINT Vbus -27 40 V Sense Input off -27 40 V – 1.5 kV HBM1) 2 kV HBM1) 6 kV HBM1) -40 150 °C – -50 150 °C – Voltages Supply voltage Regulator output voltage CAN bus voltage (CANH, CANL) Input voltage at SPLIT Input voltage at MONx and SI Output voltage at OUTHS and MTS LIN line bus input voltages ESD resistivity VESD,RxD -2 ESD all other pins. versus GND VESD1 -2 ESD at pin CANH, CANL, VESD1 -6 ESD at RxD pin versus GND SPLIT, LIN, MONx versus GND Temperatures Junction temperature Storage temperature Tj Tstg 1) ESD susceptibility HBM according to EIA/JESD 22-A 114B. Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. Data Sheet 30 Rev. 1.51, 2007-06-22 TLE 7263E General Product Characteristics 5.2 Table 12 Operating Range Operating Range Parameter Symbol Limit Values Min. Unit Remarks Max. Supply voltage VS VUV OFF 27 V After VS rising above VUV ON Supply voltage VS dVS/dt VI VUV OFF 40 V 40 V load dump -0.5 5 V/µs – -0.3 VCC1 V – Output capacitor CCC1/2 100 – nF ESR < 6 Ω @ f = 10 kHz SPI clock frequency fclk Tj – 4 MHz – -40 150 °C – Supply voltage slew rate Logic input voltage (DI, CLK, CSN, TxD, STS) Junction temperature 5.3 Thermal Resistance Parameter Symbol Limit Values Min. Junction to Case1) Junction to Ambient1) RthjC RthjA Typ. Max. 1 5 25 Unit Remarks K/W K/W 2) 1) Not subject to production test, specified by design. 2) According to Jedec JESD51-2,-5,-7 at natural convection on 2s2p board for 1W. Board: 76.2x114.3x1.5mm³ with 2 inner copper layers (70µm thick)., with thermal via array under the exposed pad contacted the first inner copper layer Data Sheet 31 Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics 6 Table 13 Electrical Characteristics Electrical Characteristics VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Unit Test Condition Min. Typ. Max. – 6 8 mA SBC Active Mode 1.2 2 mA Active [CAN Sleep] 1.7 3 mA => LIN dominant; without RL 4 6 mA Active [LIN Sleep] Quiescent Current; Pin VS Current consumption IQ IQ – 68 80 µA stand-by mode; Tj = 25 °C; VCC2 “off” IQ – 580 900 µA stand-by mode; Tj = 25 °C; VCC2 “off”; after LIN wake-up / power-up Current consumption IQ – 68 80 µA stop mode; Tj = 25 °C; VCC2 “off”; without cyclic sense Current consumption IQ – 76 88 µA stop mode; Tj = 85 °C; VCC2 “off”; without cyclic sense Current consumption IQ – 49 60 µA sleep mode; Tj = 25 °C; VCC2 “off”; without cyclic sense Current consumption IQ – 53 65 µA sleep mode; Tj = 85°C; VCC2 “off”; without cyclic sense Current consumption IQ – 220 300 µA sleep mode, during HS-On phase; Tj = 25 °C; VCC2 “off” Current consumption Data Sheet 32 Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics Table 13 Electrical Characteristics (cont’d) VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Current consumption Symbol IQ Limit Values Unit Test Condition Min. Typ. Max. – 240 330 µA sleep mode, during HS-On phase; Tj = 85°C; VCC2 “off” Voltage Regulator; Pin VCC1/2 Output voltage VCC1/2 4.9 5.0 5.1 V 1 mA<ICC1/2<100 mA; 6 V < VS < 20 V Line regulation ∆VCC1/2 – – 20 mV 6 V < VS < 16 V; ICC = 1 mA Load regulation ∆VCC1/2 – – 50 mV 5 mA<ICC1/2<100 mA; VS = 6 V Power supply ripple rejection PSRR – 40 – dB Vr = 1 Vpp; fr = 100 Hz; specified by design; not subject to production test Output current limit Drop voltage Data Sheet ICC1/2max 200 – VDR – – 500 mA VCC1/2 = 4.5 V; power transistor thermally monitored; 150 mA for external load 0.5 V ICC1/2 = 150 mA; internal modules not supplied; 4.5V < VS < 5.4V 33 Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics Table 13 Electrical Characteristics (cont’d) VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Unit Test Condition Min. Typ. Max. – 256 – kHz – 400 500 600 µs – 4.5 4.65 4.8 V default SPI setting VRT2 VRT,hys 3.2 3.35 3.5 V SPI option; VS ≥ 4 V – 100 – mV – Reset low output voltage VRO – 0.2 0.4 V IRESET = 1 mA for VCC1 = VRT1/2 ; IRESET = 200 µA for VRT1/2> VCC1 ≥ 1 V Reset high output voltage VRO 0.7 x – VCC1 V – Reset pull-up current IRO tRR 20 150 500 µA 4 10 26 µs VRO = 0 V VCC1 < VRT1/2 tRD1 4.0 5.0 6.0 ms default SPI setting; after Power-On-Reset tRD2 0.4 0.5 0.6 ms SPI setting option Oscillator Oscillating frequency Internal cycling time (1/128 × fOSC) fOSC tCYL Reset Generator; Pin RO Reset threshold voltage VRT1 Reset threshold hysteresis Reset reaction time Reset delay time VCC1 + 0.1 to RO = L Fail Safe Output; Pin FSO Watchdog edge count difference to set HIGH nFS – 4 – – – Fail Safe low output voltage VFS – 0.2 0.4 V Fail Safe high output voltage VFS VCC- – VCC + V IFSO = 1 mA for VCC1 = VRT1/2 or IFSO = 200 µA for VCC1 ≥ 1 V IFSO = -1 mA for VCC1 ≥ VRT1/2 Data Sheet 0.6 0.1 34 Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics Table 13 Electrical Characteristics (cont’d) VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Min. Typ. Unit Test Condition Max. Sense Input (Early Warning) SI, VCCx-Fail, Interrupt Output INT Sense In threshold voltage VSI,th 1.8 2.3 2.8 V VSI decreasing Sense In threshold hysteresis VSI,hys 100 200 300 mV – Sense reaction time tS,r 5 10 20 µs VSI < VSI,th to Interrupt Out high voltage VINThigh 0.7 × – VCC1 V I0 = -20 µA Interrupt Out low voltage VINTlow 0 – 1.2 V I0 = 1.25 mA 20 150 500 µA VINT = 0 V Interrupt pull-up current IINT INT = low VCC1 Input voltage for Flash Programming Mode at pin INT VINT 7 – – V VCC1-Fail threshold VVCC1,th 2.1 2.6 3.1 V – VCC1-Fail reaction time tVCC1,r 10 20 30 µs – Long open window (128 cyl.) tLW 51 64 77 ms – Watchdog reset-pulse tWDR1 tWDR2 IWD,th 3.6 5.0 6.0 ms default SPI setting 0.012 0.5 0.6 ms SPI setting option 0.5 – 8 mA – – voltage Watchdog Generator Watchdog current threshold Monitoring Inputs MONx MONx input threshold voltage VMONxth 2 3 4 V Input hysteresis VI, hys. 0.1 – 0.7 V Data Sheet 35 Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics Table 13 Electrical Characteristics (cont’d) VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Pull up current Pull down current MONx filter time Input current Symbol IPU,MON IPD,MON tMONx, f IMONx Limit Values Unit Test Condition Min. Typ. Max. -30 -10 -3 µA VMON = 3.8V 3 10 30 µA VMON = 2V 10 – 20 µs – -2 – 2 µA VMONx = 0 V; VMONx > 5V High Side Output OUTHS 2.5 3.5 Ω Tj = 25 °C – – 6.0 Ω – – VS-45 – V -10 – – µA IOUTHS = -0.15 A VOUTHS = 0 V – – 20 µs CSN high to OUTHS – – 20 µs CSN high to OUTHS -0.8 -0.4 -0.2 A – 10 25 40 µs – – 5.35 6.00 V 4.50 4.85 – V 0.1 0.2 – V VS increasing VS decreasing VUV ON - VUV OFF – 16 to 512 – ms selectable via SPI bits; tolerance depending on internal oscillator 0.4 0.5 0.6 ms default SPI setting 0.08 0.1 0.12 ms SPI option Static Drain-Source ON-Resistance; IOUTH = -150 mA RDSON HS – Active Zener voltage VOUTHS IQLHS tdONHS tdOFFHS ISDHS Leakage current Switch ON delay time Switch OFF delay time Overcurrent shutdown threshold tdSDHS UV-Switch-ON voltage VUV ON UV-Switch-OFF voltage VUV OFF UV-ON/OFF-Hysteresis VUV HY Cyclic sense period tP CS Shutdown filter time Cyclic sense ON time Data Sheet tCS on1 tCS on2 36 Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics Table 13 Electrical Characteristics (cont’d) VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Unit Test Condition Min. Typ. Max. – 0.7 × V – Send to Sleep Input (STS) H-input voltage threshold VIH – L-input voltage threshold VIL 0.3 × – – V – Hysteresis of input voltage VIHY 0.8 – 1.5 V – 20 40 80 kΩ VSTS = 0.2 × VCC1 10 – – µs one oscillator period Pull-down resistance at RISTS pin STS STS pulse width tSTS VCC1 VCC1 Wake Event Output WKO HIGH level output voltage VWKO,H 0.8 × – – V IWKO = -1.6 mA LOW level output voltage VWKO,L – – 0.2 × V IWKO = 1.6 mA VRD = 0.8 × VCC1; Vdiff < 0.4 V1) VRD = 0.2 × VCC1; Vdiff > 1 V1) VCC1 VCC1 CAN Transceiver Characteristics Receiver Output RxD HIGH level output current IRD,H – -4 -2 mA LOW level output current IRD,L 2 4 – mA HIGH level input voltage VTD,H threshold – 0.5 × 0.7 × V recessive state VTD,hys LOW level input voltage VTD,L – 0.4 – V – 0.3 × 0.5 × – V dominant state 10 20 40 kΩ – Transmission Input TxD TxD input hysteresis threshold TxD pull-up resistance Data Sheet RTD VCC1 VCC1 VCC1 VCC1 37 Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics Table 13 Electrical Characteristics (cont’d) VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Min. Typ. Max. 0.80 0.90 Unit Test Condition CAN Bus Receiver Differential receiver threshold voltage, recessive to dominant edge Vdiff,d – Differential receiver threshold voltage, dominant to recessive edge Vdiff,r 0.50 Common Mode Range CMR -12 – 12 V – Differential receiver hysteresis Vdiff,hys – 110 – mV “active mode” CANH, CANL input resistance Ri 10 20 30 kΩ recessive state Differential input resistance Rdiff 20 40 60 kΩ recessive state Wake-up Receiver threshold voltage, recessive to dominant edge Vdiff, d – 0.8 1.15 V “sleep/stop mode” Wake-up Receiver threshold voltage, dominant to recessive edge Vdiff, r 0.4 0.7 – V “sleep/stop mode” Wake-up Receiver differential receiver hysteresis Vdiff, hys. – 120 – mV “sleep/stop mode” Data Sheet V Vdiff = VCANH - VCANL “active mode” 0.60 – V Vdiff = VCANH - VCANL “active mode” 38 Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics Table 13 Electrical Characteristics (cont’d) VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Unit Test Condition Min. Typ. Max. CANL/CANH recessive VCANL/H output voltage 2.0 – 3.0 V no load CANH, CANL recessive Vdiff output voltage difference Vdiff = VCANH - VCANL -500 – 50 mV VTxD = VCC1; CAN Bus Transmitter CANL dominant output voltage VCANL no load 0.5 – 2.25 V CANH dominant output VCANH voltage 2.75 – 4.5 V CANH, CANL dominant Vdiff output voltage difference Vdiff = VCANH - VCANL 1.5 – 3.0 V VTxD = 0 V; VCC2 = 5 V VTxD = 0 V; VCC2 = 5 V VTxD = 0 V; VCC2 = 5 V CANH short circuit current ICANHsc -200 -80 -50 mA VCANHshort = 0 V CANL short circuit current ICANLsc 50 80 200 mA VCANLshort = 18 V Leakage current ICANH,lk ICANL,lk – 25 – µA VS = VCC2 = 0 V; 0 V < VCANH,L< 5 V Split Termination Output; Pin SPLIT Split output voltage Leakage current VSPLIT 0.3 × 0.5 × 0.7 × V normal mode; -500 µA < ISPLIT < 500 µA ISPLIT -5 0 5 µA standby mode; -22 V < VSPLIT < 35 V – 600 – Ω – SPLIT output resistance RSPLIT Data Sheet VCC2 VCC2 39 VCC2 Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics Table 13 Electrical Characteristics (cont’d) VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Min. Typ. Unit Test Condition Max. Dynamic CAN-Transceiver Characteristics Propagation delay td(L),TR TxD-to-RxD LOW (recessive to dominant) – 150 255 ns Propagation delay td(H),TR TxD-to-RxD HIGH (dominant to recessive) – 150 255 ns CL = 47 pF; RL = 60 Ω; VCC1/2 = 5 V; CRxD = 20 pF CL = 47 pF; RL = 60 Ω; VCC1/2 = 5 V; CRxD = 20 pF CL = 47 pF; RL = 60 Ω; VCC1/2 = 5 V CL = 47 pF; RL = 60 Ω; VCC1/2 = 5 V CL = 47 pF; RL = 60 Ω; VCC1/2 = 5 V; CRxD = 20 pF CL = 47 pF; RL = 60 Ω; VCC1/2 = 5 V; CRxD = 20 pF Propagation delay TxD LOW to bus dominant td(L),T – 50 120 ns Propagation delay TxD HIGH to bus recessive td(H),T – 50 120 ns Propagation delay bus dominant to RxD LOW td(L),R – 100 135 ns Propagation delay bus recessive to RxD HIGH td(H),R – 100 135 ns Min. dominant time for bus wake-up tWU 1 3 5 µs – TxD permanent dominant disable time tTxD 0.3 – 1.0 ms – Data Sheet 40 Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics Table 13 Electrical Characteristics (cont’d) VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Min. Typ. Max. Unit Test Condition LIN Transceiver Characteristics Receive Output RxD HIGH level output voltage VRxD,H 0.8 × – – V LOW level output voltage VRxD,L – – 0.2 × V 0.7 × V recessive state 1.5 V – VCC1 VCC1 IRxD(LIN) = -1.6 mA; Vbus = VS IRxD(LIN) = 1.6 mA; Vbus = 0 V Transmission Input TxD HIGH level input voltage VTxD,H threshold – VTxD,hys LOW level input voltage VTxD,L 0.8 TxD input hysteresis – VCC1 0.3 × – – V dominant state RTxD 20 40 80 kΩ VTxD = 0 V Receiver threshold voltage, recessive to dominant edge Vbus,rd 0.42 × VS 0.48 × – V – Receiver dominant state Vbusdom – – 0.40 × VS V (LIN Spec 1.3 (2.0); Line 10.1.9 (3.1.9)) Receiver threshold voltage, dominant to recessive edge Vbus,dr – 0.52 × 0.58 × VS VS V Vbus,rec < Vbus < 27 V Receiver recessive state Vbusrec 0.6 × – – (LIN Spec 1.3 (2.0); Line 10.1.10 (3.1.10)) 0.525 V × VS (LIN Spec 1.3 (2.0); Line 10.1.11 (3.1.11)) threshold TxD pull-up Resistor VCC1 Bus Receiver Receiver center voltage Vbuscent Receiver hysteresis Data Sheet Vbus,hys VS – VS 0.475 0.5 × × VS VS 0.02 × VS 0.04 × 0.1 × VS 41 VS V Vbus,hys = Vbus,rec - Vbus,dom (LIN Spec 1.3 (2.0); Line 10.1.12 (3.1.12)) Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics Table 13 Electrical Characteristics (cont’d) VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Wake-up threshold voltage Symbol Vwake Limit Values Unit Test Condition Min. Typ. Max. 0.40 × VS 0.5 × 0.6 × V – 0.4 0.7 1.0 V VTxD = high Level – – 1.2 V VTxD = 0 V; VS = 7 V; RL = 500 Ω; VS VS Bus Transmitter Bus serial diode voltage Vserdiode drop Bus dominant output voltage Vbus,dom (LIN Spec 1.3; Line 10.1.13) – – 2.0 V VS = 18 V; RL = 500 Ω; (LIN Spec 1.3; Line 10.1.14) Bus dominant output voltage Vbus,dom 0.6 – – V VTxD = 0 V; VS = 7 V; RL = 1 kΩ; (LIN Spec 1.3; Line 10.1.15) 0.8 – – V VS = 18 V; RL = 1 kΩ; (LIN Spec 1.3; Line 10.1.16) Bus short circuit current Ibus,sc Data Sheet 40 100 150 mA Vbus,short = 18 V (LIN Spec 1.3 (2.0); Line 10.1.4 (3.1.4)) 42 Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics Table 13 Electrical Characteristics (cont’d) VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Leakage current Symbol Ibus,lk Limit Values Min. Typ. Max. -500 -140 – Unit Test Condition µA VS = 0 V; Vbus = -8 V (LIN Spec 1.3 (2.0); Line 10.1.7 (3.1.7)) – 10 25 µA VS = 0 V; Vbus = 18 V (LIN Spec 1.3 (2.0); Line 10.1.8 (3.1.8)) -1 – – mA VS = 18 V; Vbus = 0 V (LIN Spec 1.3 (2.0); Line 10.1.5(3.1.5)) – – 20 µA VBUS =18V VS = 8V (LIN Spec 1.3 (2.0); Line 10.1.6 (3.1.6)) Bus pull-up resistance Rbus 20 30 60 kΩ Active/Standby mode (LIN Spec 1.3 (2.0); Line 10.2.2 (3.2.2)) LIN output current Ilin 5 20 60 µA Sleep mode;Vbus = 0V Data Sheet 43 Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics Table 13 Electrical Characteristics (cont’d) VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Min. Typ. Max. Unit Test Condition Dynamic Transceiver Characteristics Slew rate falling edge Sfslope -3 – -1 V/µs 60% > Vbus > 40% 1 µs < (τ = Rl × Cbus) < 5 µs; VS = 13.5 V; Active mode (LIN Spec 1.3; Line 10.3.1) Slew rate rising edge Srslope 1 – 3 V/µs 40% < Vbus < 60% 1 µs < (τ = Rl × Cbus) < 5 µs; VS = 13.5 V; Active mode. (LIN Spec 1.3; Line 10.3.1) Slope symmetry tslopesym -5 – 5 µs tfslope - trslope; VS = 13.5 V (LIN Spec 1.3; Line 10.3.3) Propagation delay TxD LOW to bus td(L),T – 1 4 µs (LIN Spec 1.3; Line 10.3.6) Propagation delay TxD HIGH to bus td(H),T – 1 4 µs (LIN Spec 1.3; Line 10.3.6) Propagation delay bus dominant to RxD LOW td(L),R – 1 6 µs CRxD = 20 pF; Propagation delay bus recessive to RxD HIGH td(H),R – Receiver delay symmetry tsym,R -2 Data Sheet (LIN Spec 1.3; Line 10.3.7) 1 6 µs CRxD = 20 pF; (LIN Spec 1.3; Line 10.3.7) – 2 µs tsym,R = td(L),R - td(H),R (LIN Spec 1.3; Line 10.3.8) 44 Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics Table 13 Electrical Characteristics (cont’d) VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Min. Typ. Max. – 2 Unit Test Condition µs Transmitter delay symmetry tsym,T -2 Wake-up delay time twake 30 100 150 µs – – 170 µs 6 12 20 ms – 10 – µs TxD dominant time out TxD dominant time out recovery time ttimeout ttorec tsym,T = td(L),T - td(H),T (LIN Spec 1.3; Line 10.3.9) Tj ≤ 125 °C Tj ≤ 150 °C VTxD = 0 V VTxD = 5 V Not subject to production test. Specified by design Transfer Rate 20 kBit/s; 1 µs < τ = RL × Cbus < 5 µs Duty cycle D1 D1 0.396 – – duty cycle 1: THRec(max) = 0.744 × VS; THDom(max) = 0.581 × VS; VS = 7.0 … 18 V; tbit = 50 µs; D1 = tbus_rec(min)/[2 tbit] (LIN Spec 2.0; line 3.3.1) Duty cycle D2 D2 – 0.581 duty cycle 2: THRec(min) = 0.422 × VS; THDom(min) = 0.284 × VS; VS = 7.6 … 18 V; tbit = 50 µs; D2 = tbus_rec(max)/[2 tbit] (LIN Spec 2.0; line 3.3.2) Data Sheet – 45 Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics Table 13 Electrical Characteristics (cont’d) VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Min. Typ. Unit Test Condition Max. Transfer Rate 10.4 kBit/s; 1 µs < τ = RL × Cbus < 5 µs Slew Rate falling edge “Low Slope/US Mode” Sfslope -1.5 – -0.5 V/µs 60% > Vbus > 40%; τ = RI × Cbus; 1 µs < τ < 5 µs; VS = 7 … 18 V Slew Rate rising edge “Low Slope/US Mode” Srslope 0.5 – 1.5 V/µs 40% < Vbus < 60%; τ = RI × Cbus; 1 µs < τ < 5 µs; VS = 7 … 18 V Duty cycle D3 D3 0.417 – – duty cycle 3 THRec(max) = 0.778 × VS; THDom(max) = 0.616 × VS; VS = 7.0 … 18 V; tbit = 96 µs; D3 = tbus_rec(min)/[2 tbit] (LIN Spec 2.0; line 3.4.1) Duty cycle D4 D4 – 0.590 duty cycle 4 THRec(min) = 0.389 × VS; THDom(min) = 0.251 × VS; VS = 7.6 … 18 V; tbit = 96 µs; D4 = tbus_rec(max)/[2 tbit] (LIN Spec 2.0; line 3.4.2) – Master Termination Switch Output; Pin MTS Ron resistance Maximum output current Data Sheet RonMTS IMTS – 33 60 Ω 40 – 150 mA 46 IMTS = -15 mA VMTS = 0 V Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics Table 13 Electrical Characteristics (cont’d) VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Leakage current Data Sheet Symbol IMTS,lk Limit Values Min. Typ. Max. -5.0 – 5.0 47 Unit Test Condition µA sleep mode; VMTS = 0 V Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics Table 13 Electrical Characteristics (cont’d) VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Unit Test Condition Min. Typ. Max. – 0.7 × V – – V – 1.5 V – SPI-Interface Logic Inputs DI, CLK and CSN H-input voltage threshold VIH – L-input voltage threshold VIL 0.3 × Hysteresis of input voltage VIHY 0.8 VCC1 – VCC1 Pull-up resistance at pin RICSN CSN 20 40 80 kΩ VCSN = 0.7 × VCC1 Pull-down resistance at RICLK/DI pin DI and CLK 20 40 80 kΩ VDI/CLK = 0.2 × VCC1 CI – 10 15 pF Not subject to production test. Specified by design VDOH VCC1 V -0.4 VCC1 - – 0.2 IDOH = -1 mA VDOL IDOLK – 0.2 0.4 V -10 – 10 µA IDOL = 1.6 mA VCSN = VCC1; 0 V < VDO < VCC1 CDO – 10 15 pF Input capacitance at pin CSN, DI or CLK Logic Output DO H-output voltage level L-output voltage level Tri-state leakage current Tri-state input capacitance Not subject to production test. Specified by design Data Input Timing Not subject to production test. Specified by design Clock period Clock high time Clock low time Clock low before CSN low CSN setup time Data Sheet tpCLK tCLKH tCLKL tbef 250 – – ns – 125 – – ns – 125 – – ns – 125 – – ns – tlead 250 – – ns – 48 Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics Table 13 Electrical Characteristics (cont’d) VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Unit Test Condition Min. Typ. Max. tlag tbeh 250 – – ns – 125 – – ns – tDISU tDIHO trIN 50 – – ns – 50 – – ns – – – 50 ns – tfIN Input signal fall time at pin DI, CLK and CSN – – 50 ns – Delay time for mode change from Normal Mode to Sleep Mode tfIN – – 10 µs – CSN high time tCSN(high) 15 – – µs two oscillator periods CLK setup time Clock low after CSN high DI setup time DI hold time Input signal rise time at pin DI, CLK and CSN Data Output Timing Not subject to production test. Specified by design DO rise time DO fall time DO enable time DO disable time trDO tfDO tENDO tDISDO – 30 80 ns – 30 80 ns CL = 100 pF CL = 100 pF – – 50 ns low impedance – – 50 ns high impedance Thermal Prewarning and Shutdown (junction temperatures) (Not subject to production test. Specified by design) VCC1 thermal TjPW 120 145 170 °C bit 0 of SPI diagnosis word VCC1 thermal ∆T – 25 – K – VCC1/2 thermal TjSD 155 185 200 °C hysteresis 35 K (typ.) VCC1 ratio of SD to PW TjSD/ TjPW – 1.20 – – – prewarning ON temperature prewarning hyst. shutdown temp. temp. Data Sheet 49 Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics Table 13 Electrical Characteristics (cont’d) VS = 13.5 V; ICC1 = 1 mA; 4.9 V < VCC1/2 < 5.1 V; SBC Active Mode; all outputs open; -40 °C < Tj < 150 °C (max. 125 °C for CAN circuit characteristics); all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified. Parameter Symbol Limit Values Min. Typ. Max. Unit Test Condition OUTHS thermal shutdown temp. TjSD 150 175 200 °C – OUTHS thermal shutdown hyst. ∆T – 10 – K – TjSD CAN Transmitter thermal shutdown temp. 150 – 190 °C – CAN Transmitter ∆T thermal shutdown hyst. – 10 – K – LIN Transmitter thermal TjSD shutdown temp. 150 – 190 °C – LIN Transmitter thermal ∆T shutdown hyst. – 10 – K – 1) Vdiff = VCANH - VCANL Data Sheet 50 Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics Timing Diagrams CSN high to low: DO is enabled. Status information transferred to output shift register CSN time CSN low to high: data from shift register is transferred to output functions CLK time Actual data DI FI - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 New data FI 0 1 + + time DI: will accept data on the falling edge of CLK signal Actual status DO FO - 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 New status FO 0 + 1 + time DO: will change state on the rising edge of CLK signal e.g. HS switch Old data Actual data SPI_data_transfer_timing Figure 12 Data Sheet time SPI-Data Transfer Timing 51 Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics Figure 13 SPI-Input Timing Figure 14 Turn OFF/ON Time Data Sheet 52 Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics Figure 15 DO Valid Data Delay Time and Valid Time Figure 16 DO Enable and Disable Time Data Sheet 53 Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics tWD tCWmax tOWmax t CWmin tOWmin closed window open window t / [tWDPER] safe trigger area 0.4 0.6 0.8 1.0 1.2 tWWRP tWWRP : Window Watchdog Reset Period set via SPI, see table 9 Figure 17 Watchdog Time-Out Definitions tCW WD Trigger tCW tCW tOW tOW tCW +tOW tLW tLW tOW tLW tCW tCW tOW tWDR Reset Out t Watchdog timer reset t normal operation Figure 18 Data Sheet timeout (too long) normal operation timeout (too short) normal operation Watchdog Timing Diagram 54 Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics VCC VRTx t < tRR VCC1-Fail tRD1 WD Trigger tLW tLW tCW tOW tLW tCW t Watchdog timer reset start up VCC1 fail flag t t tRR tWDRx Reset Out tRDx normal operation tVCC, r undervoltage start up HIGH LOW t activation by µC [first SPI transmission] Figure 19 Data Sheet Reset Timing Diagram 55 Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics VTxD VCC GND VDIFF td(L), T td(H), T t VDIFF(d) VDIFF(r) VRxD td(L), R t td(H), R VCC 0.7VCC 0.3VCC GND td(L), TR td(H), TR t AET02926 Figure 20 Data Sheet CAN Dynamic Characteristics Timing Diagram 56 Rev. 1.51, 2007-06-22 TLE 7263E Electrical Characteristics VCC VTxD GND td(L),T t td(H),T VS Vbus Vbus,rd Vbus,dr GND t td(H),R td(L),R VCC 0.7*VCC VRxD 0.3*VCC GND td(L),TR Figure 21 Data Sheet td(H),TR t LIN Dynamic Characteristics Timing Diagram 57 Rev. 1.51, 2007-06-22 TLE 7263E Application Information 7 Application Information 7.1 ESD Tests Tests for ESD robustness according to IEC61000-4-2 “gun test” (150pF, 330Ω) have been performed. The results and test condition are available in a test report. Table 14 ESD “GUN test” Performed Test Result Unit Remarks ESD at pin CANH, CANL, LIN, Vs ≥ +8 versus GND kV 1) Positive pulse ESD at pin CANH, CANL, LIN, Vs ≤ -8 versus GND kV 1) Negative pulse 1) ESD susceptibility “ESD GUN” according LIN EMC 1.3 Test Specification, Section 4.3. (IEC 61000-4-2) Tested by external test house (IBEE Zwickau, EMC Test report Nr. 11-11-06). Data Sheet 58 Rev. 1.51, 2007-06-22 TLE 7263E Application Information 7.2 Application Example Vbat 60Ohms 4.7nF CAN bus 60Ohms SPLIT FSO CANH RxDCAN CANL TxDCAN CSN OUTHS CLK MON4 DO 1kOhm DI MON3 INT MON2 RO 10 kOhm MON1 WKO STS MTS VS 100 nF 68 µF VCC1 TLE 7263 1 kOhm LIN Bus VCC2 TxDLIN VCC2 10 µF 100 nF µC 10 µF e.g. XC164CM RxDLIN 0.1 µF LIN SI GND GND 1 nF 160 kOhm 100 kOhm 4.7 nF Appl_7263 Figure 22 Data Sheet Application Circuit 59 Rev. 1.51, 2007-06-22 TLE 7263E Package Outlines 8˚ MAX. 7.6 -0.2 1) 0.65 0.7 ±0.2 C 17 x 0.65 = 11.05 0.33 ±0.08 2) 0.23 +0.09 0.35 x 45˚ 1.1 12˚ 2.65 MAX. Package Outlines 0...0.15 STAND OFF 2.45 -0.2 8 0.1 C 36x SEATING PLANE 10.3 ±0.3 0.17 M A-B C D 36x D Bottom View A 19 19 36 Exposed Diepad 5.1 36 18 1 18 B 7 1 Index Marking 12.8 -0.21) Index Marking 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion of 0.05 max. per side GPS01153 Figure 23 PG-DSO-36-24 (Plastic Dual Small Outline with Exposed Pad) Green Product (RoHS Compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020) You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/products. Data Sheet 60 Dimensions in mm Rev. 1.51, 2007-06-22 TLE 7263E Revision History 9 Revision History TLE 7263E Revision History: 2007-06-22 Previous Version: Revision 1.50 Rev. 1.51 Page Subjects (major changes since last revision) 40 Propagation Delay valus (td(L),T; td(H),T; td(L),R ; td(H,)R) changed. Previous Version: Preliminary Data Sheet 1.41 Page Subjects (major changes since last revision) 2 New package picture 32/33 Typical values added and update quiescent current; pin VS 60 Latest package drawing Data Sheet 61 Rev. 1.51, 2007-06-22 Edition 2007-06-22 Published by Infineon Technologies AG 81726 München, Germany © Infineon Technologies AG 2007. All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of noninfringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.infineon.com Published by Infineon Technologies AG