Features • • • • • • • • • Low Current Consumption: IDD < 100 µA RC Oscillator Internal Reset During Power-up and Supply Voltage Drops (POR) “Short” Trigger Window for Active Mode, “Long” Trigger Window for Sleep Mode Cyclical Wake-up of the Microcontroller in Sleep Mode Trigger Input Single Wake-up Input Reset Output Enable Output Digital Window Watchdog Timer U5021M 1. Description The digital window watchdog timer, U5021M, is a CMOS integrated circuit. In applications where safety is critical, it is especially important to monitor the microcontroller. Normal microcontroller operation is indicated by a cyclically transmitted trigger signal, which is received by a window watchdog timer within a defined time window. A missing or a wrong trigger signal causes the watchdog timer to reset the microcontroller. The IC is tailored for microcontrollers which can work in both full-power and sleep mode. With an additional voltage monitoring (power-on reset and supply voltage drop reset), the U5021M offers a complete monitoring solution for microsystems in automotive and industrial applications. Rev. 4756D–AUTO–11/05 Figure 1-1. Block Diagram with External Ciruit C VDD R1 VDD 10 nF 6 OSC 8 C1 RC Oscillator OSC Reset 5 Microcontroller State machine OSC Trigger 2 Mode 3 Wake-up 4 Input signal conditioning Enable Power-on reset POR 1 POR External switching circuitry Test logic 7 GND 2. Pin Configuration Figure 2-1. 2 Pinning SO8 WAKE-UP 1 8 OSC TRIG 2 7 GND MODE 3 6 VDD ENA 4 5 RESET U5021M 4756D–AUTO–11/05 U5021M 3. Pin Description Pin Symbol Function 1 WAKE-UP 2 TRIG 3 MODE 4 ENA Enable output (push-pull) It is used for the control of peripheral components. It is activated after the processor triggers three times correctly. 5 RESET Reset output (open drain) Resets the processor in the case of a trigger error or if a wake-up pulse occurs during the long watchdog period. Wake-up input (pull-down resistor) There is one digitally debounced wake-up input. During the long watchdog window, each signal slope at the input initiates a reset pulse at pin 5. Trigger input (pull-up resistor) It is connected to the microprocessor’s trigger signal. Mode input (pull-up resistor) The processor’s mode signal initiates the switchover between the long and the short watchdog time. 6 VDD Supply voltage 7 GND Ground, reference voltage 8 OSC RC oscillator 4. Functional Description 4.1 Supply Voltage, Pin 6 The U5021M requires a stabilized supply voltage VDD = 5 V ±5% to comply with its electrical characteristics. An external buffer capacitor of C = 10 nF may be connected between pin 6 and GND. 4.2 RC Oscillator, Pin 8 The clock frequency, f, can be adjusted by the components R1 and C1 according to the formula: f = 1 --t where t = 1.35 + 1.57 R1 (C1 + 0.01) R1 in kΩ, C1 in nF and t in µs The clock frequency determines all time periods of the logic part as shown in the table “Electrical Characteristics” under the subheading “Timing” on page 9. With an appropriate component selection, the clock frequency, f, is nearly independent of the supply voltage as shown in Figure 4-1 on page 4. Frequency tolerance ∆fmax = 10% with R1 ±1%, C1 = ±5% 3 4756D–AUTO–11/05 Figure 4-1. Period t versus R1, at C1 = 500 pF 1000.00 100.00 t (µs) 4.5 V 10.00 5.0 V 5.5 V C1 = 500 pF 1.00 1 10 100 1000 R1 (kΩ) Figure 4-2. Power-on Reset and Switch-over Mode Pin 6 VDD t0 t6 Pin 5 Reset Out t1 Mode 4.3 Pin 3 Supply Voltage Monitoring, Pin 5 During ramp-up of the supply voltage and in the case of supply-voltage drops the integrated power-on reset (POR) circuitry sets the internal logic to a defined basic status and generates a reset pulse at the reset output, pin 5. A hysteresis in the POR threshold prevents the circuit from oscillating. During ramp-up of the supply voltage, the reset output stays active for a specified period of time (t0) in order to bring the microcontroller into its defined reset status (see Figure 4-2). Pin 5 has an open-drain output. 4.4 Switch-over Mode Time, Pin 3 The switch-over mode time enables the synchronous operation of microcontroller and watchdog. When the power-on reset time has elapsed, the watchdog has to be switched to monitoring mode by the microcontroller by a “low” signal transmitted to the mode pin (pin 3) within the time-out period, t1. If the low signal does not occur within t1 (see Figure 4-2), the watchdog generates a reset pulse, t6, and t1 starts again. Microcontroller and watchdog are synchronized with the switch-over mode time, t1, each time a reset pulse is generated. 4 U5021M 4756D–AUTO–11/05 U5021M 4.5 4.5.1 Microcontroller in Active Mode Monitoring with the “Short” Trigger Window After the switch-over mode the watchdog operates in short watchdog mode and expects a trigger pulse from the microcontroller within the defined time window, t 3 , (enable time). The watchdog generates a reset pulse which resets the microcontroller if • the trigger pulse duration is too long • the trigger pulse is within the disable time, t2 • there is no trigger pulse Figure 4-3 shows the pulse diagram with a missing trigger pulse. Figure 4-3. Pulse Diagram with no Trigger Pulse During the Short Watchdog Time Pin 6 VDD t0 t1 Pin 5 Reset out t3 t2 Mode Pin 3 Pin 2 Trigger Figure 4-4 on page 6 shows a correct trigger sequence. The positive edge of the trigger signal starts a new monitoring cycle with the disable time, t2. To ensure correct operation of the microcontroller, the watchdog needs to be triggered three times correctly before it sets its enable output. This feature is used to activate or deactivate safety-critical components which have to be switched to a certain condition (emergency status) in the case of a microcontroller malfunction. As soon as there is an incorrect trigger sequence, the enable signal is reset and it takes a sequence of three correct triggers before enable is active. 4.6 4.6.1 Microcontroller in Sleep Mode Monitoring with the “Long” Trigger Window The long watchdog mode allows cyclical wake-up of the microcontroller during sleep mode. As in short watchdog mode, there is a disable time, t4, and an enable time, t5, in which a trigger signal is accepted. The watchdog can be switched from the short trigger window to the long trigger window with a “high” potential at the mode pin (pin 3). In contrast to the short watchdog mode, the time periods are now much longer and the enable output remains inactive so that other components can be switched off to effect a further decrease in current consumption. As soon as a wake-up signal at the wake-up input (pins 1) is detected, the long watchdog mode ends, a reset pulse wakes-up the sleeping microcontroller and the normal monitoring cycle starts with the mode switch-over time. 5 4756D–AUTO–11/05 Figure 4-4. Pulse Diagram of a Correct Trigger Sequence During the Short Watchdog Time Pin 6 VDD t0 t1 Pin 5 Reset out t3 t2 t2 Mode Pin 3 Pin 2 Trigger ttrig Pin 4 Enable Figure 4-5 shows the switch-over from the short to the long watchdog mode. The wake-up signal during the enable time, t5, activates a reset pulse, t6. The watchdog can be switched back from the long to the short watchdog mode with a low potential at the mode pin (pin 3). Figure 4-5. Pulse Diagram of the Long Watchdog Time t6 t1 Pin 5 Reset out Wake-up Pins 1 t4 t5 Pin 3 Mode t2 Pin 2 Trigger Enable Pin 4 5. State Diagram The kernel of the watchdog is a finite state machine. Figure 5-1 shows the state diagram with all possible states and transmissions. Many transmissions are controlled by an internal timer. The numbers for the time-outs are the same as on the pulse diagrams. 6 U5021M 4756D–AUTO–11/05 U5021M Figure 5-1. State Diagram Reset state time out t 0 mode = 1 mode = 0 Mode switch state Short window disable state mode = 0 time out t 4 time out t 2 time out t 1 trg_ok = 1 trg_ok = 1 mode = 1 time out t 6 mode = 0 Short window enable state trg = 0 Long window disable state Long window enable state time out t 3 trg_err = 1 trg_err = 1 Reset out state time out t 5 or wedge = 1 trg = 0 or wedge = 1 Notes: • "mode" and "trg" are the debounced input signals from the pins MODE and TRG • trg_ok = 1 after the rising edge of the trg signal • trg_err = 1 when the trg signal low period is too long • wedge = 1 after detecting the debounced changing of a signal level from the WUP pin • Every state change restarts the internal timer • If a state change is generated from an external debounced pin signal exactly one clock cycle before the internal timer initiates a state change itself, the state machine changes its state twice. The first state change is created by the signal change, and the second by the timeout of the internal timer. This occurs due to the timer getting its reset one clock cycle after a state change. 7 4756D–AUTO–11/05 6. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Symbol Value Unit Supply voltage VDD 6.5 V Output current IOUT ±2 mA Input voltage VIN -0.4 V to VDD +0.4 V V Ambient temperature range Tamb -40 to +125 °C Storage temperature range Tstg -55 to +150 °C Symbol Value Unit RthJA 180 K/W 7. Thermal Resistance Parameters Junction ambient 8. Electrical Characteristics VDD = 5 V; Tamb = -40°C to +85°C; reference point is pin 7, unless otherwise specified Parameters Test Conditions Supply voltage Pin Symbol Min. 6 VDD 4.5 Typ. Max. Unit 5.5 V 60 µA Current consumption R1 = 66 kΩ 6 IDD Power-on reset Release reset state with rising voltage 6 VPOR1 3.9 4.5 V Get reset state with falling voltage 6 VPOR2 3.8 4.4 V VPOR_hys 40 200 mV 0.1 VDD Power-on reset hysteresis Reset level for low VDD VDD = 1 V to VPOR1 IRST = -300 µA Inputs VRST 1, 2, 3 Logical “high” VIH Logical “low” 3.4 1.6 V VIN_hys 0.6 1.4 V VIN -0.3 VDD + 0.3 V VIL Hysteresis Input voltage range V Input current 2, 3 I IN1 5 20 µA Input current 1 I IN2 -20 -5 µA -2 2 mA 0.2 V Outputs Maximum output current 4, 5 IOUT Logical output “low” IOUT = -1 mA 4, 5 VOL Logical output “high” IOUT = -1 mA 4 VOH Leakage current VOUT = 5 V 5 Ileak 8 VDD 0.2 V 2 µA U5021M 4756D–AUTO–11/05 U5021M 8. Electrical Characteristics (Continued) VDD = 5 V; Tamb = -40°C to +85°C; reference point is pin 7, unless otherwise specified Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit 5 % 4 Cycle Timing R1 = 66 kΩ, C1 = 470 pF, VDD = 4.5 V to 5.5 V Frequency deviation(1) ∆f Debounce time 2, 3 Debounce time 1 3 96 128 Cycle ttrgmax 45 Cycle Power-up reset time to 201 Cycle Switch over mode time t1 1,112 Cycle Maximum trigger pulse length Disable time Short watchdog window t2 130 Cycle Enable time Short watchdog window t3 124 Cycle Disable time Long watchdog window t4 71,970 Cycle Enable time Long watchdog window t5 30,002 Cycle t6 40 Cycle Reset-out time Note: 1. Frequency deviation also depends on the tolerances of the external components 9. Ordering Information Extended Type Number Package Remarks U5021M-NFPY SO8 Tubed, Pb-free U5021M-NFPG3Y SO8 Taped and reeled, Pb-free 10. Package Information Package SO8 Dimensions in mm 5.2 4.8 5.00 4.85 3.7 1.4 0.25 0.10 0.4 1.27 6.15 5.85 3.81 8 0.2 3.8 5 technical drawings according to DIN specifications 1 4 9 4756D–AUTO–11/05 11. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. 10 Revision No. History 4756D-AUTO-11/05 • • • • 4756C-AUTO-09/04 • Electrical Characteristics Table, page 8, row “Reset capability” changed in “Reset level for low VDD“ 4756B-AUTO-07/04 • Electrical Characteristics Table, page 8, row “Reset capability” added Put datasheet in a new template First page: Pb-free logo added Page 7: figure 5-1 changed Page 9: Ordering Information changed U5021M 4756D–AUTO–11/05 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60 ASIC/ASSP/Smart Cards 1150 East Cheyenne Mtn. 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