Quad Parametric Measurement Unit with Integrated 16-Bit Level Setting DACs AD5522 Data Sheet FEATURES APPLICATIONS Quad parametric measurement unit (PMU) FV, FI, FN (high-Z), MV, MI functions 4 programmable current ranges (internal RSENSE) ±5 μA, ±20 μA, ±200 μA, and ±2 mA 1 programmable current range up to ±80 mA (external RSENSE) 22.5 V FV range with asymmetrical operation Integrated 16-bit DACs provide programmable levels Gain and offset correction on chip Low capacitance outputs suited to relayless systems On-chip comparators per channel FI voltage clamps and FV current clamps Guard drive amplifier System PMU connections Programmable temperature shutdown SPI- and LVDS-compatible interfaces Compact 80-lead TQFP with exposed pad (top or bottom) Automated test equipment (ATE) Per-pin parametric measurement unit Continuity and leakage testing Device power supply Instrumentation Source measure unit (SMU) Precision measurement FUNCTIONAL BLOCK DIAGRAM AVSS AGND VREF REFGND 16 16 16 X1 REG M REG C REG 16 16 16 DVCC AVDD DGND CCOMP[0:3] ×4 16-BIT CLH DAC 16 X2 REG SYS_FORCE SYS_SENSE EN CLH OFFSET DAC ×6 – 16-BIT 16 FIN DAC FIN INTERNAL RANGE SELECT (±5µA, ±20µA, ±200µA, ±2mA) SW1 + AGND X2 REG FOH[0:3] SW5 – SW2 X2 REG RSENSE SW4 16-BIT CLL DAC ×2 EXTMEASIH[0:3] + – SW12 AGND 16 16 16 MEASOUT MUX AND GAIN ×1/×0.2 2kΩ X1 REG M REG C REG ×6 16 X2 REG EXTMEASIL[0:3] MEASVH[0:3] + – 16-BIT CPH DAC AGND GUARD[0:3] SW13 + ×1 16 16 16 CPH ×6 X1 REG M REG C REG ×6 16 16-BIT CPL DAC X2 REG SW9 4kΩ MEASURE CURRENT IN-AMP SW11 ×6 SW7 + – – TEMP SENSOR – + – GUARD AMP DUTGND + – – CPL COMPARATOR SW16 SW14 GUARDIN[0:3]/ DUTGND[0:3] DUT DUTGND MEASURE VOLTAGE IN-AMP + EXTERNA L RSENSE (CURRENTS UP TO ±80mA) SW8 + ×5 or ×10 MEASOUT[0:3] 4kΩ SW6 CLL VMID TO CENTER I RANGE SW10 ×2 1kΩ FORCE AMPLIFIER MEASVH (Hi-Z) 16 60Ω + ×6 X1 REG M REG C REG CFF[0:3] ×2 ×2 X1 REG M REG C REG 16 16 16 EXTFOH[0:3] SW3 SW15 10kΩ AGND 16-BIT OFFSET DAC 16 TO ALL DAC OUTPUT AMPLIFIERS TO MEASOUT MUX TEMP SENSOR TMPALM 16 RESET SDO SCLK SDI SYNC BUSY CLAMP AND GUARD ALARM LOAD SPI/ CPOL0/ LVDS SCLK CPOH0/ SDI CPOL1/ SYNC CPOH1/ SDO CPOL2/ CPOH2/ CPO0 CPO1 CPOL3/ CPO2 CPOH3/ CPO3 CGALM 06197-001 POWER-ON RESET SERIAL INTERFACE Figure 1. Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008–2012 Analog Devices, Inc. All rights reserved. AD5522 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Calibration................................................................................... 38 Applications ....................................................................................... 1 Additional Calibration ............................................................... 39 Functional Block Diagram .............................................................. 1 System Level Calibration ........................................................... 39 Revision History ............................................................................... 3 Circuit Operation ........................................................................... 40 General Description ......................................................................... 4 Force Voltage (FV) Mode .......................................................... 40 Specifications..................................................................................... 6 Force Current (FI) Mode ........................................................... 41 Timing Characteristics .............................................................. 11 Serial Interface ................................................................................ 42 Absolute Maximum Ratings .......................................................... 15 SPI Interface ................................................................................ 42 Thermal Resistance .................................................................... 15 LVDS Interface............................................................................ 42 ESD Caution ................................................................................ 15 Serial Interface Write Mode ...................................................... 42 Pin Configurations and Function Descriptions ......................... 16 RESET Function ......................................................................... 42 Typical Performance Characteristics ........................................... 22 BUSY and LOAD Functions ..................................................... 42 Terminology .................................................................................... 29 Register Update Rates ................................................................ 44 Theory of Operation ...................................................................... 30 Register Selection ....................................................................... 44 Force Amplifier ........................................................................... 30 Write System Control Register ................................................. 46 Comparators................................................................................ 30 Write PMU Register ................................................................... 48 Clamps ......................................................................................... 30 Write DAC Register ................................................................... 50 Current Range Selection ............................................................ 31 Read Registers ............................................................................. 53 High Current Ranges ................................................................. 31 Readback of System Control Register...................................... 54 Measure Current Gains.............................................................. 32 Readback of PMU Register ....................................................... 55 VMID Voltage ............................................................................. 32 Readback of Comparator Status Register ................................ 56 Choosing Power Supply Rails ................................................... 33 Readback of Alarm Status Register .......................................... 56 Measure Output (MEASOUTx Pins)....................................... 33 Readback of DAC Register ........................................................ 57 Device Under Test Ground (DUTGND)................................. 33 Applications Information .............................................................. 58 Guard Amplifier ......................................................................... 34 Power-On Default ...................................................................... 58 Compensation Capacitors ......................................................... 34 Setting Up the Device on Power-On ....................................... 58 System Force and Sense Switches ............................................. 35 Changing Modes ........................................................................ 59 Temperature Sensor ................................................................... 35 Required External Components ............................................... 59 DAC Levels ...................................................................................... 36 Power Supply Decoupling ......................................................... 60 Offset DAC .................................................................................. 36 Power Supply Sequencing ......................................................... 60 Gain and Offset Registers .......................................................... 36 Typical Application for the AD5522 ........................................ 60 Cached X2 Registers................................................................... 37 Outline Dimensions ....................................................................... 62 Reference Voltage (VREF)......................................................... 37 Ordering Guide .......................................................................... 63 Reference Selection .................................................................... 37 Rev. E | Page 2 of 64 Data Sheet AD5522 REVISION HISTORY 5/12—Rev. D to Rev. E Change to MV Transfer Function, Table 11 ................................33 2/11—Rev. C to Rev. D Changes to Measure Current, Gain Error Tempco Parameter.... 6 Changes to Force Current, Common Mode Error (Gain = 5) and Common Mode Error (Gain = 10) Parameters ..................... 7 Changes to Figure 5.........................................................................13 Changes to Figure 6.........................................................................14 Changes to Figure 15 ......................................................................22 Changes to High Current Ranges Section ...................................31 Changes to Gain and Offset Registers Section ............................36 Changes to Endnote 1 in Table 17 and Figure 56........................43 Changes to Register Update Rates and Figure 57 .......................44 Changes to Bit 15 to Bit 0 Description in Table 28 .....................50 5/10—Rev. B to Rev. C Changes to Compensation Capacitors Section ...........................34 Changes to Gain and Offset Registers Section ............................36 Changes to Table 14 and Reducing Zero-Scale Error Section...38 Changes to Serial Interface Write Mode Section and BUSY and LOAD Functions Section ...............................................................42 Changes to Table 17 ........................................................................43 Added Table 18; Renumbered Sequentially .................................43 Changes to Register Update Rates Section ..................................44 Changes to Table 23 ........................................................................46 Changes to Table 31 ........................................................................54 10/08—Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 6 Change to 4 DAC X1 Parameter, Table 2 ..................................... 11 Changes to Table 3 .......................................................................... 12 Change to Reflow Soldering Parameter, Table 4 ......................... 15 Changes to Figure 18, Figure 19, Figure 20, and Figure 21 ....... 23 Changes to Figure 25 ...................................................................... 24 Changes to Force Amplifier Section ............................................. 29 Changes to Clamps Section ........................................................... 29 Changes to High Current Ranges Section ................................... 30 Changes to Choosing Power Supply Rails Section ..................... 32 Changes to Compensation Capacitors Section ........................... 33 Added Table 14, Renumbered Tables Sequentially ..................... 36 Changes to Reference Selection Example .................................... 36 Changes to Table 15 and BUSY and LOAD Functions Section .............................................................................................. 40 Changes to Table 17 and Register Update Rates Section ........... 41 Added Table 38 ................................................................................ 57 Changes to Ordering Guide ........................................................... 60 7/08—Revision 0: Initial Version 10/09—Rev. A to Rev. B Changes to Table 1 ............................................................................ 6 Changes to Table 2 ..........................................................................11 Added Figure 13 and Figure 15; Renumbered Sequentially ......22 Added Figure 16 ..............................................................................23 Changes to Figure 21 ......................................................................23 Changes to Clamps Section ...........................................................30 Changes to Table 22, Bit 21 to Bit 18 Description ......................44 Changes to Table 25, Bit 9 Description ........................................47 Changes to Table 28 ........................................................................49 Changes to Figure 59 ......................................................................59 Rev. E | Page 3 of 64 AD5522 Data Sheet GENERAL DESCRIPTION The AD5522 is a high performance, highly integrated parametric measurement unit consisting of four independent channels. Each per-pin parametric measurement unit (PPMU) channel includes five 16-bit, voltage output DACs that set the programmable input levels for the force voltage inputs, clamp inputs, and comparator inputs (high and low). Five programmable force and measure current ranges are available, ranging from ±5 µA to ±80 mA. Four of these ranges use on-chip sense resistors; one high current range up to ±80 mA is available per channel using off-chip sense resistors. Currents in excess of ±80 mA require an external amplifier. Low capacitance DUT connections (FOHx and EXTFOHx) ensure that the device is suited to relayless test systems. The PMU functions are controlled via a simple 3-wire serial interface compatible with SPI, QSPI™, MICROWIRE™, and DSP interface standards. Interface clocks of 50 MHz allow fast updating of modes. The low voltage differential signaling (LVDS) interface protocol at 83 MHz is also supported. Comparator outputs are provided per channel for device go-no-go testing and characterization. Control registers allow the user to easily change force or measure conditions, DAC levels, and selected current ranges. The SDO (serial data output) pin allows the user to read back information for diagnostic purposes. Rev. E | Page 4 of 64 Data Sheet AD5522 AVSS AGND VREF REFGND 16 16 16 X1 REG M REG C REG 16 16 16 CCOMP0 DGND DVCC AVDD CH0 16-BIT CLH DAC 16 X2 REG EN CLH ×2 OFFSET DAC X1 REG M REG C REG – 16-BIT 16 FIN DAC FIN INTERNAL RANGE SELECT (±5µA, ±20µA, ±200µA, ±2mA) SW1 + + AGND X2 REG FOH0 FORCE AMPLIFIER MEASVH (Hi-Z) ×6 SW5 – RSENSE SW2 X1 REG M REG C REG CFF0 SW3 ×2 ×6 16 16 16 EXTFOH0 16 X2 REG 16-BIT CLL DAC ×2 VMID TO CENTER I RANGE SW10 ×2 EXTMEASIH0 + – SW12 AGND 16 16 16 MEASOUT MUX AND GAIN ×1/×0.2 2kΩ TEMP SENSOR 16 X2 REG AGND MEASVH0 ×6 ×6 16-BIT CPL CPL DAC 16 X2 REG – – + SW16 SW13 + CPH X1 REG M REG C REG 4kΩ + – 16-BIT CPH DAC + – – + DUTGND SW14 GUARDIN0/ DUTGND0 MEASURE VOLTAGE IN-AMP COMPARATOR DUT GUARD0 GUARD AMP DUTGND ×1 16 16 16 SW9 MEASURE CURRENT IN-AMP ×6 X1 REG M REG C REG SW7 EXTMEASIL0 + – – SW11 ×6 EXTERNAL RSENSE (CURRENTS UP TO ±80mA) SW8 + ×5 OR ×10 MEASOUT0 4kΩ SW6 SW4 CLL SW15 10kΩ CPOL0/SCLK AGND CPOH0/SDI EXTFOH1 CFF1 FOH1 CCOMP1 CH1 MEASOUT1 CPOL1/SYNC EXTMEASIH1 EXTMEASIL1 CPOH1/SDO AGND MEASVH1 GUARD1 GUARDIN1/DUTGND1 MUX MUX SYS_SENSE SYS_FORCE EXTFOH2 CCOMP2 CFF2 MEASOUT2 FOH2 EXTMEASIH2 CH2 CPOL2/CPO0 CPOH2/CPO1 AGND EXTMEASIL2 MEASVH2 GUARD2 GUARDIN2/DUTGND2 EN CCOMP3 X1 REG M REG C REG 16 16 16 16-BIT CLH DAC 16 X2 REG CLH CH3 ×2 ×2 OFFSET DAC ×6 X1 REG M REG C REG – 16-BIT 16 FIN DAC FIN + AGND FOH3 FORCE AMPLIFIER MEASVH (Hi-Z) ×6 SW5 – RSENSE SW2 16 16 16 X1 REG M REG C REG 16 X2 REG 16-BIT CLL DAC ×2 VMID TO CENTER I RANGE EXTMEASIH3 CLL + – SW12 AGND 16 16 16 MEASOUT MUX AND GAIN x1/x0.2 2kΩ X1 REG M REG C REG ×6 16 X2 REG AGND CPH ×6 X1 REG M REG C REG ×6 16 X2 REG MEASVH3 + – 16-BIT CPH DAC + – GUARD AMP DUTGND + – – 16-BIT CPL CPL DAC – SW13 + x1 16 16 16 SW9 4kΩ MEASURE CURRENT IN-AMP SW11 ×6 SW7 EXTMEASIL3 + – – TEMP SENSOR SW16 SW14 16 10kΩ SW15a TO MEASOUT MUX DUTGND TEMP SENSOR TMPALM CLAMP AND GUARD ALARM CGALM 16 POWER-ON RESET 10kΩ SERIAL INTERFACE CPOL3/ RESET SDO SCLK SDI SYNC BUSY LOAD SPI/ LVDS CPO2 AGND CPOH3/ CPO3 Figure 2. Detailed Block Diagram Rev. E | Page 5 of 64 DUT SW15 AGND TO ALL DAC OUTPUT AMPLIFIERS GUARD3 GUARDIN3/ DUTGND3 MEASURE VOLTAGE IN-AMP + COMPARATOR 16-BIT OFFSET DAC EXTERNAL RSENSE (CURRENTS UP TO ±80mA) SW8 + x5 or x10 MEASOUT3 4kΩ SW6 SW4 SW10 ×2 CFF3 INTERNAL RANGE SELECT (±5µA, ±20µA, ±200µA, ±2mA) SW1 + X2 REG EXTFOH3 SW3 06197-002 16 16 16 AD5522 Data Sheet SPECIFICATIONS AVDD ≥ 10 V; AVSS ≤ −5 V; |AVDD − AVSS| ≥ 20 V and ≤ 33 V; DVCC = 2.3 V to 5.25 V; VREF = 5 V; REFGND = DUTGND = AGND = 0 V; gain (M), offset (C), and DAC offset registers at default values; TJ = 25°C to 90°C, unless otherwise noted. (FV = force voltage, FI = force current, MV = measure voltage, MI = measure current, FS = full scale, FSR = full-scale range, FSVR = full-scale voltage range, FSCR = full-scale current range.) Table 1. Parameter FORCE VOLTAGE FOHx Output Voltage Range 2 EXTFOHx Output Voltage Range2 Output Voltage Span Offset Error Offset Error Tempco2 Gain Error Gain Error Tempco2 Linearity Error Short-Circuit Current Limit2 Min Max Unit Test Conditions/Comments AVSS + 4 AVDD − 4 V AVSS + 3 AVDD − 3 V All current ranges from FOHx at full-scale current; includes ±1 V dropped across sense resistor External high current range at full-scale current; does not include ±1 V dropped across sense resistor 22.5 −50 +50 −10 −0.5 +0.5 0.5 V mV µV/°C % FSR ppm/°C % FSR −0.01 +0.01 −150 −10 +150 +10 mA mA nV/√Hz +1.125 V V +0.5 % FSCR µV/°C % FSCR % FSCR ppm/°C Noise Spectral Density (NSD)2 MEASURE CURRENT 320 Differential Input Voltage Range2 Output Voltage Span −1.125 Offset Error Offset Error Tempco2 Gain Error −0.5 22.5 1 −1 −0.5 Gain Error Tempco2 Linearity Error (MEASOUTx Gain = 1) Typ 1 +1 +0.5 −2 −0.015 −0.01 −0.06 +0.015 +0.01 +0.06 % FSR % FSR % FSR −0.11 +0.11 % FSR −0.015 +0.015 % FSR −0.06 +0.06 % FSR −0.01 +0.01 % FSR −0.01 +0.01 % FSR Common-Mode Voltage Range2 Common-Mode Error (Gain = 5) AVSS + 4 −0.01 AVDD − 4 +0.01 V % FSCR/V Common-Mode Error (Gain = 10) −0.005 +0.005 % FSCR/V Linearity Error (MEASOUTx Gain = 0.2) Sense Resistors 200 50 5 0.5 kΩ kΩ kΩ kΩ Rev. E | Page 6 of 64 Measured at midscale code; prior to calibration Standard deviation = 20 μV/°C Prior to calibration Standard deviation = 0.5 ppm/°C FSR = full-scale range (±10 V), gain and offset errors calibrated out ±80 mA range All other ranges 1 kHz, at FOHx in FV mode Measure current = (IDUT × RSENSE × gain); amplifier gain = 5 or 10, unless otherwise noted Voltage across RSENSE; gain = 5 or 10 Measure current block with VREF = 5 V, MEASOUT scaling happens after V(RSENSE) = ±1 V, measured with zero current flowing Referred to MI input; standard deviation = 4 µV/°C Using internal current ranges Measure current amplifier alone Standard deviation = 2 ppm/°C Measure current amplifier alone; internal sense resistor 25 ppm/°C MI gain = 10 MI gain = 5 MI gain = 10, AVDD = 28 V, AVSS = −5 V, offset DAC = 0x0 MI gain = 10, AVDD = 10 V, AVSS = −23 V, offset DAC = 0x0EDB7 MI gain = 10, AVDD = 15.25 V, AVSS = −15.25 V, offset DAC = 0xA492 MI gain = 5, AVDD = 28 V, AVSS = −5 V, offset DAC = 0x0 MI gain = 5, AVDD = 10 V, AVSS = −23 V, offset DAC = 0xEDB7 MI gain = 5, AVDD = 15.25 V, AVSS = −15.25 V, offset DAC = 0xA492 % of full-scale change at force output per V change in DUT voltage % of full-scale change at force output per V change in DUT voltage Sense resistors are trimmed to within 1% ±5 µA range ±20 µA range ±200 µA range ±2 mA range Data Sheet Parameter Measure Current Ranges2 AD5522 Min Typ 1 Max Unit ±80 µA µA µA mA mA ±5 ±20 ±200 ±2 Noise Spectral Density (NSD)2 FORCE CURRENT Voltage Compliance, FOHx2 Voltage Compliance, EXTFOHx2 Offset Error Offset Error Tempco2 Gain Error Gain Error Tempco2 Linearity Error Common-Mode Error (Gain = 5) Common-Mode Error (Gain = 10) Force Current Ranges 400 AVSS + 4 AVSS + 3 −0.5 nV/√Hz AVDD − 4 AVDD − 3 +0.5 +0.02 +0.01 +0.006 V V % FSCR ppm FS/°C % FSCR ppm/°C % FSCR % FSCR/V % FSCR/V ±80 µA µA µA mA mA 5 −1.5 +1.5 −6 −0.02 −0.01 −0.006 ±5 ±20 ±200 ±2 MEASURE VOLTAGE Measure Voltage Range2 Offset Error Offset Error Tempco2 Gain Error Gain Error Tempco2 Linearity Error (MEASOUTx Gain = 1) Linearity Error (MEASOUTx Gain = 0.2) Noise Spectral Density (NSD)2 OFFSET DAC Span Error COMPARATOR Comparator Span Offset Error Offset Error Tempco2 Propagation Delay2 VOLTAGE CLAMPS Clamp Span Positive Clamp Accuracy Negative Clamp Accuracy CLL to CLH2 Recovery Time2 Activation Time2 AVSS + 4 −10 −25 AVDD − 4 +10 +25 100 V mV mV µV/°C % FSR % FSR ppm/°C % FSR % FSR % FSR % FSR nV/√Hz ±30 mV −1 −0.25 −0.5 +0.25 +0.5 1 −0.01 −0.01 −0.06 −0.1 −2 +0.01 +0.01 +0.06 +0.1 22.5 +1 +2 1 0.25 µV/°C μs 22.5 155 −155 500 0.5 1.5 V mV 1.5 3 Rev. E | Page 7 of 64 V mV mV mV μs μs Test Conditions/Comments Specified current ranges are achieved with VREF = 5 V and MI gain = 10, or with VREF = 2.5 V and MI gain = 5 Set using internal sense resistor Set using internal sense resistor Set using internal sense resistor Set using internal sense resistor Set using external sense resistor; internal amplifier can drive up to ±80 mA 1 kHz, MI amplifier only, inputs grounded Measured at midscale code, 0 V, prior to calibration Standard deviation = 5 ppm/°C Prior to calibration Standard deviation = 5 ppm/°C % of full-scale change per V change in DUT voltage % of full-scale change per V change in DUT voltage Specified current ranges achieved with VREF = 5 V and MI gain = 10, or with VREF = 2.5 V and MI gain = 5 V Set using internal sense resistor, 200 kΩ Set using internal sense resistor, 50 kΩ Set using internal sense resistor, 5 kΩ Set using internal sense resistor, 500 Ω Set using external sense resistor; internal amplifier can drive up to ±80 mA Gain = 1, measured at 0 V Gain = 0.2, measured at 0 V Standard deviation = 6 µV/°C MEASOUTx gain = 1 MEASOUTx gain = 0.2 Standard deviation = 4 ppm/°C AVDD = 15.25 V, AVSS = −15.25 V, offset DAC = 0xA492 AVDD = 28 V, AVSS = −5 V, offset DAC = 0x0 AVDD = −10 V, AVSS = −23 V, offset DAC = 0x3640 1 kHz; measure voltage amplifier only, inputs grounded Measured directly at comparator; does not include measure block errors Standard deviation = 2 µV/°C CLL < CLH and minimum voltage apart AD5522 Parameter CURRENT CLAMPS Clamp Accuracy CLL to CLH2 Data Sheet Min Typ 1 Programmed clamp value Programmed clamp value 5 Max Unit Test Conditions/Comments Programmed clamp value ± 10 Programmed clamp value ± 20 % FSC MI gain = 10, clamp current scales with selected range MI gain = 5, clamp current scales with selected range 1.5 3 % of IRANGE % of IRANGE μs μs +3 pF nA 10 Recovery Time2 Activation Time2 FOHx, EXTFOHx, EXTMEASILx, EXTMEASIHx, CFFx PINS Pin Capacitance2 Leakage Current Leakage Current Tempco2 MEASVHx PIN Pin Capacitance2 Leakage Current Leakage Current Tempco2 SYS_SENSE PIN Pin Capacitance2 Switch Impedance Leakage Current Leakage Current Tempco2 SYS_FORCE PIN Pin Capacitance2 Switch Impedance Leakage Current Leakage Current Tempco2 COMBINED LEAKAGE AT DUT Leakage Current Leakage Current Tempco2 DUTGNDx PIN Voltage Range Leakage Current MEASOUTx PIN Output Voltage Span Output Impedance Output Leakage Current Output Capacitance2 Maximum Load Capacitance2 Output Current Drive2 Short-Circuit Current Slew Rate2 Enable Time2 Disable Time2 MI to MV Switching Time2 0.5 1.5 10 −3 ±0.01 CLL < CLH and minimum setting apart, MI gain = 10 CLL < CLH and minimum setting apart, MI gain = 5 Individual pin on or off switch leakage, measured with ±11 V stress applied to pin, channel enabled, but tristate nA/°C 3 −3 % FSC +3 pF nA ±0.01 nA/°C 3 1 1.3 +3 pF kΩ nA nA/°C 80 +3 pF Ω nA nA/°C Measured with ±11 V stress applied to pin, channel enabled, but tristate SYS_SENSE connected, force amplifier inhibited −3 ±0.01 Measured with ±11 V stress applied to pin, switch off SYS_FORCE connected, force amplifier inhibited 6 60 −3 ±0.01 −15 −25 +15 +25 nA nA nA/°C +500 +30 mV nA ±0.1 −500 −30 22.5 60 −3 80 +3 15 0.5 2 −10 +10 2 150 400 320 1100 200 V Ω nA pF μF mA mA V/μs ns ns ns Rev. E | Page 8 of 64 Measured with ±11 V stress applied to pin, switch off Includes FOHx, MEASVHx, SYS_SENSE, SYS_FORCE, EXTMEASILx, EXTMEASIHx, EXTFOHx, and CFFx; calculation of all the individual leakage contributors TJ = 25°C to 70°C TJ = 25°C to 90°C With respect to AGND Software programmable output range With SW12 off Closing SW12, measured from BUSY rising edge Opening SW12, measured from BUSY rising edge Measured from BUSY rising edge; does not include slewing or settling Data Sheet Parameter GUARDx PIN Output Voltage Span Output Offset Short-Circuit Current Maximum Load Capacitance2 Output Impedance Tristate Leakage Current2 Slew Rate2 Alarm Activation Time2 FORCE AMPLIFIER2 Slew Rate Gain Bandwidth Max Stable Load Capacitance AD5522 Min Typ 1 Max 22.5 −10 −15 +10 +15 100 85 −30 +30 5 200 0.4 1.3 Unit Test Conditions/Comments V mV mA nF Ω nA V/μs μs When guard amplifier is disabled CLOAD = 10 pF Alarm delayed to eliminate false alarms 10,000 V/μs MHz pF ±80 mA Range ±2 mA Range ±200 µA Range ±20 µA Range ±5 µA Range MI SETTLING TIME TO 0.05% OF FS2 22 24 40 300 1400 40 40 80 µs µs µs µs µs ±80 mA Range ±2 mA Range ±200 µA Range ±20 µA Range ±5 µA Range FI SETTLING TIME TO 0.05% OF FS2 22 24 60 462 1902 40 40 100 µs µs µs µs µs ±80 mA Range ±2 mA Range ±200 µA Range ±20 µA Range ±5 µA Range MV SETTLING TIME TO 0.05% OF FS2 24 24 50 450 2700 55 60 120 µs µs µs µs µs ±80 mA Range ±2 mA Range ±200 µA Range ±20 µA Range ±5 µA Range DAC SPECIFICATIONS Resolution Output Voltage Span2 Differential Nonlinearity2 COMPARATOR DAC DYNAMIC SPECIFICATIONS2 Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Energy Glitch Impulse Peak Amplitude REFERENCE INPUT VREF DC Input Impedance VREF Input Current VREF Range2 24 24 50 450 2700 55 60 120 µs µs µs µs µs CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF CCOMPx = 100 pF, larger CLOAD requires larger CCOMP capacitor CCOMPx = 1 nF, larger CLOAD requires larger CCOMP capacitor Midscale to full-scale change; measured from SYNC rising edge, clamps on CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF Midscale to full-scale change; driven from force amplifier in FV mode, so includes FV settling time; measured from SYNC rising edge, clamps on CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF CCOMPx = 100 pF, CFFx = 220 pF, CLOAD = 200 pF Midscale to full-scale change; measured from SYNC rising edge, clamps on CCOMPx = 100 pF, CLOAD = 200 pF CCOMPx = 100 pF, CLOAD = 200 pF CCOMPx = 100 pF, CLOAD = 200 pF CCOMPx = 100 pF, CLOAD = 200 pF CCOMPx = 100 pF, CLOAD = 200 pF Midscale to full-scale change; driven from force amplifier in FV mode, so includes FV settling time; measured from SYNC rising edge, clamps on CCOMPx = 100 pF, CLOAD = 200 pF CCOMPx = 100 pF, CLOAD = 200 pF CCOMPx = 100 pF, CLOAD = 200 pF CCOMPx = 100 pF, CLOAD = 200 pF CCOMPx = 100 pF, CLOAD = 200 pF 100 nF 16 Bits V LSB VREF = 5 V, within a range of −16.25 V to +22.5 V Guaranteed monotonic by design over temperature FV SETTLING TIME TO 0.05% OF FS2 22.5 −1 +1 1 5.5 20 10 1 −10 2 100 +0.03 µs V/µs nV-sec mV +10 5 Rev. E | Page 9 of 64 MΩ µA V 500 mV change to ±½ LSB AD5522 Parameter DIE TEMPERATURE SENSOR Accuracy2 Output Voltage at 25°C Output Scale Factor2 Output Voltage Range2 INTERACTION AND CROSSTALK2 DC Crosstalk (FOHx) Data Sheet Typ 1 Max Unit 3 °C V mV/°C V 0.05 0.65 mV DC Crosstalk (MEASOUTx) 0.05 0.65 mV DC Crosstalk Within a Channel 0.05 SPI INTERFACE LOGIC INPUTS Input High Voltage, VIH Min ±7 1.5 4.6 0 1.7/2.0 V Input Low Voltage, VIL Input Current, IINH, IINL Input Capacitance, CIN2 CMOS LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Tristate Leakage Current −1 AISS AIDD AISS DICC Maximum Power Dissipation2 V +1 10 µA pF 0.4 +2 +1 10 V V µA µA pF 0.4 10 V pF 1575 +100 120 mV mV Ω mV DC change resulting from a dc change in any DAC in the device, FV and FI modes, ±2 mA range, CLOAD = 200 pF, RLOAD = 5.6 kΩ DC change resulting from a dc change in any DAC in the device, MV and MI modes, ±2 mA range, CLOAD = 200 pF, RLOAD = 5.6 kΩ All channels in FVMI mode, one channel at midscale; measure the current for one channel in the lowest current range for a change in comparator or clamp DAC levels for that PMU (2.3 V to 2.7 V)/(2.7 V to 5.25 V), JEDEC-compliant input levels (2.3 V to 2.7 V)/(2.7 V to 5.25 V), JEDEC-compliant input levels SDO, CPOx −2 −1 875 −100 80 100 100 1200 400 10 −23 2.3 IOL = 500 µA SDO, CPOH1/SDO All other output pins BUSY, TMPALM, CGALM IOL = 500 µA, CLOAD = 50 pF, RPULLUP = 1 kΩ mV mV 28 −5 5.25 26 −26 AIDD AISS 0.7/0.8 DVCC − 0.4 Output Capacitance2 OPEN-DRAIN LOGIC OUTPUTS Output Low Voltage, VOL Output Capacitance2 LVDS INTERFACE LOGIC INPUTS REDUCED RANGE LINK2 Input Voltage Range Input Differential Threshold External Termination Resistance Differential Input Voltage LVDS INTERFACE LOGIC OUTPUTS REDUCED RANGE LINK Output Offset Voltage Output Differential Voltage POWER SUPPLIES AVDD AVSS DVCC AIDD mV Test Conditions/Comments V V V mA mA 28 −28 mA mA 36 −36 1.5 7 Rev. E | Page 10 of 64 mA mA mA W |AVDD − AVSS| ≤ 33 V Internal ranges (±5 μA to ±2 mA), excluding load conditions; comparators and guard disabled Internal ranges (±5 μA to ±2 mA), excluding load conditions; comparators and guard disabled Internal ranges (±5 μA to ±2 mA), excluding load conditions; comparators and guard enabled Internal ranges (±5 μA to ±2 mA), excluding load conditions; comparators and guard enabled External range, excluding load conditions External range, excluding load conditions Maximum power that should be dissipated in this package under worst-case load conditions; careful consideration should be given to supply selection and thermal design Data Sheet AD5522 Parameter Power Supply Sensitivity2 ΔForced Voltage/ΔAVDD ΔForced Voltage/ΔAVSS ΔMeasured Current/ΔAVDD ΔMeasured Current/ΔAVSS ΔForced Current/ΔAVDD ΔForced Current/ΔAVSS ΔMeasured Voltage/ΔAVDD ΔMeasured Voltage/ΔAVSS ΔForced Voltage/ΔDVCC ΔMeasured Current/ΔDVCC ΔForced Current/ΔDVCC ΔMeasured Voltage/ΔDVCC 1 2 Min Typ 1 Max Unit −80 −80 −85 −75 −75 −75 −85 −80 −90 −90 −90 −90 Test Conditions/Comments From dc to 1 kHz dB dB dB dB dB dB dB dB dB dB dB dB Typical specifications are at 25°C and nominal supply, ±15.25 V, unless otherwise noted. Guaranteed by design and characterization; not production tested. Tempco values are mean and standard deviation, unless otherwise noted. TIMING CHARACTERISTICS AVDD ≥ 10 V, AVSS ≤ −5 V, |AVDD − AVSS| ≥ 20 V and ≤ 33 V, DVCC = 2.3 V to 5.25 V, VREF = 5 V, TJ = 25°C to 90°C, unless otherwise noted. Table 2. SPI Interface Parameter 1, 2, 3 tWRITE 4 t1 t2 t3 t4 t5 4 t6 t7 t8 t9 t10 1 DAC X1 2 DAC X1 3 DAC X1 4 DAC X1 Other Registers t11 t12 t13 t14 t15 DVCC, Limit at TMIN, TMAX 2.3 V to 2.7 V 2.7 V to 3.6 V 4.5 V to 5.25 V 1030 735 735 950 655 655 30 20 20 8 8 8 8 8 8 10 10 10 150 150 150 Unit ns min ns min ns min ns min ns min ns min ns min 70 70 70 ns min 10 5 9 120 5 5 7 75 5 5 4.5 55 ns min ns min ns min ns max 1.65 2.3 2.95 3.6 270 20 20 150 0 100 1.65 2.3 2.95 3.6 270 20 20 150 0 100 1.65 2.3 2.95 3.6 270 20 20 150 0 100 µs max µs max µs max µs max ns max ns min ns min ns min ns min ns max Rev. E | Page 11 of 64 Description Single channel update cycle time (X1 register write) Single channel update cycle time (any other register write) SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time Minimum SYNC high time in write mode after X1 register write (one channel) Minimum SYNC high time in write mode after any other register write 29th SCLK falling edge to SYNC rising edge Data setup time Data hold time SYNC rising edge to BUSY falling edge BUSY pulse width low for X1 and some PMU register writes; see Table 17 and Table 18 System control register/PMU registers 29th SCLK falling edge to LOAD falling edge LOAD pulse width low BUSY rising edge to FOHx output response time BUSY rising edge to LOAD falling edge LOAD falling edge to FOHx output response time AD5522 Parameter 1, 2, 3 t16 t17 t18 t19 5, 6 Data Sheet DVCC, Limit at TMIN, TMAX 2.3 V to 2.7 V 2.7 V to 3.6 V 4.5 V to 5.25 V 1.8 1.2 0.9 670 700 750 400 400 400 60 45 25 Unit µs min µs max ns min ns max Description RESET pulse width low RESET time indicated by BUSY low Minimum SYNC high time in readback mode SCLK rising edge to SDO valid; DVCC = 5 V to 5.25 V Guaranteed by design and characterization; not production tested. All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 5 and Figure 6. 4 Writes to more than one X1 register engages the calibration engine for longer times, shown by the BUSY low time, t10. Subsequent writes to one or more X1 registers should either be timed or should wait until BUSY returns high (see Figure 56). This is required to ensure that data is not lost or overwritten. 5 t19 is measured with the load circuit shown in Figure 4. 6 SDO output slows with lower DVCC supply and may require use of a slower SCLK. 1 2 Table 3. LVDS Interface Parameter 1, 2, 3 t1 t2 t3 t4 t5 t6 t7 4 t8 DVCC, Limit at TMIN, TMAX 2.7 V to 3.6 V 4.5 V to 5.25 V 20 12 8 5 3 3 3 3 5 3 3 3 45 25 150 150 Unit ns min ns min ns min ns min ns min ns min ns min ns min 70 70 ns min 400 400 ns min Description SCLK cycle time SCLK pulse width high and low time SYNC to SCLK setup time Data setup time Data hold time SCLK to SYNC hold time SCLK rising edge to SDO valid Minimum SYNC high time in write mode after X1 register write Minimum SYNC high time in write mode after any other register write Minimum SYNC high time in readback mode Guaranteed by design and characterization; not production tested. All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. 3 See Figure 7. 4 SDO output slows with lower DVCC supply and may require use of slower SCLK. 1 2 Rev. E | Page 12 of 64 Data Sheet AD5522 Circuit and Timing Diagrams DVCC 200µA 2.2kΩ 50pF VOH(MIN) – VOL(MAX) 2 200µA 06197-004 VOL CLOAD TO OUTPUT PIN CLOAD 50pF 06197-003 RLOAD TO OUTPUT PIN IOL IOH Figure 4. Load Circuit for SDO, BUSY Timing Diagram Figure 3. Load Circuit for CGALM, TMPALM t1 SCLK 1 29 2 1 29 t2 t3 t4 t6 SYNC t5 t7 t8 SDI DB28 (N) DB0 (N) DB28 (N+1) DB0 (N + 1) t9 t10 BUSY t11 t12 LOAD1 t13 FOHx1 t14 t12 LOAD2 t15 FOHx2 t16 RESET 06197-005 t17 BUSY 1LOAD ACTIVE DURING BUSY. 2LOAD ACTIVE AFTER BUSY. Figure 5. SPI Write Timing (Write Word Contains 29 Bits) Rev. E | Page 13 of 64 AD5522 Data Sheet SCLK 58 29 t19 t18 SYNC DB28 (N) DB0 (N + 1) DB23/ DB28 (N + 1) DB0 (N) INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION DB23/ DB28 (N + 1) SDO DB0 (N + 1) 06197-006 SDI SELECTED REGISTER DATA CLOCKED OUT UNDEFINED Figure 6. SPI Read Timing (Readback Word Contains 24 Bits and Can Be Clocked Out with a Minimum of 24 Clock Edges) t8 SYNC SYNC t3 t1 t6 SCLK SCLK SDI MSB D28 t4 t2 MSB D23/D28 LSB D0 LSB D0 t5 t7 SDO MSB DB23/ DB28 SDO UNDEFINED LSB DB0 SELECTED REGISTER DATA CLOCKED OUT Figure 7. LVDS Read and Write Timing (Readback Word Contains 24 Bits and Can Be Clocked Out with a Minimum of 24 Clock Edges) Rev. E | Page 14 of 64 06197-007 SDI Data Sheet AD5522 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Supply Voltage, AVDD to AVSS AVDD to AGND AVSS to AGND VREF to AGND DUTGND to AGND REFGND to AGND DVCC to DGND AGND to DGND Digital Inputs to DGND Analog Inputs to AGND Storage Temperature Range Operating Junction Temperature Range (J Version) Reflow Soldering Junction Temperature Rating 34 V −0.3 V to +34 V +0.3 V to −34 V −0.3 V to +7 V AVDD + 0.3 V to AVSS − 0.3 V AVDD + 0.3 V to AVSS − 0.3 V −0.3 V to +7 V −0.3 V to +0.3 V −0.3 V to DVCC + 0.3 V AVSS − 0.3 V to AVDD + 0.3 V −65°C to +125°C 25°C to 90°C Thermal resistance values are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. Thermal Resistance1 (JEDEC 4-Layer (1S2P) Board) Package Type TQFP Exposed Pad on Bottom No Heat Sink2 With Cooling Plate at 45°C3 TQFP Exposed Pad on Top No Heat Sink2 JEDEC Standard (J-STD-020) 150°C max With Cooling Plate at 45°C3 θJA 0 200 500 N/A4 22.3 17.2 15.1 5.4 0 200 500 N/A4 42.4 37.2 35.7 3.0 θJC 4.8 4.8 2 2 Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W The information in this section is based on simulated thermal information. These values apply to the package with no heat sink attached. The actual thermal performance of the package depends on the attached heat sink and environmental conditions. 3 Natural convection at 55°C ambient. Assumes perfect thermal contact between the cooling plate and the exposed paddle. 4 N/A means not applicable. 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Airflow (LFPM) 2 ESD CAUTION Rev. E | Page 15 of 64 AD5522 Data Sheet EXTFOH1 AVSS MEASOUT3 MEASOUT2 MEASOUT1 MEASOUT0 AVSS SYS_FORCE AGND SYS_SENSE VREF REFGND AVDD 80 79 78 77 76 75 74 DUTGND CGALM SPI/LVDS RESET TMPALM AVSS EXTFOH0 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 73 72 71 70 69 68 67 66 65 64 63 62 61 60 AVDD 1 CFF0 2 PIN 1 CCOMP0 3 AVDD 59 CFF1 58 CCOMP1 EXTMEASIH0 4 57 EXTMEASIH1 EXTMEASIL0 5 56 EXTMEASIL1 FOH1 FOH0 6 55 GUARD0 7 54 GUARD1 GUARDIN0/DUTGND0 8 53 GUARDIN1/DUTGND1 52 MEASVH1 51 AGND AD5522 MEASVH0 9 TOP VIEW EXPOSED PAD ON BOTTOM (Not to Scale) AGND 10 50 AGND MEASVH2 12 49 MEASVH3 GUARDIN2/DUTGND2 13 48 GUARDIN3/DUTGND3 GUARD2 14 47 GUARD3 FOH2 15 46 FOH3 AGND 11 EXTMEASIL2 16 45 EXTMEASIL3 EXTMEASIH2 17 44 EXTMEASIH3 CCOMP2 18 43 CCOMP3 CFF2 19 42 CFF3 AVDD 20 41 AVDD 06197-008 EXTFOH3 AVSS CPOH3/CPO3 CPOL3/CPO2 CPOH2/CPO1 CPOL2/CPO0 DVCC LOAD SDO CPOH1/SDO DGND CPOL1/SYNC SDI SYNC CPOH0/SDI CPOL0/SCLK SCLK BUSY AVSS EXTFOH2 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NOTES 1. THE EXPOSED PAD IS INTERNALLY ELECTRICALLY CONNECTED TO AVSS. FOR ENHANCED THERMAL, ELECTRICAL, AND BOARD LEVEL PERFORMANCE, THE EXPOSED PADDLE ON THE BOTTOM OF THE PACKAGE SHOULD BE SOLDERED TO A CORRESPONDING THERMAL LAND PADDLE ON THE PCB. Figure 8. Pin Configuration, Exposed Pad on Bottom Table 6. Pin Function Descriptions Pin No. Mnemonic Exposed pad 1, 20, 41, 60, 74 2 AVDD 3 4 5 6 7 8 CCOMP0 EXTMEASIH0 EXTMEASIL0 FOH0 GUARD0 GUARDIN0/ DUTGND0 9 10, 11, 50, 51, 69 12 MEASVH0 AGND External Capacitor for Channel 0. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section. Compensation Capacitor Input for Channel 0. See the Compensation Capacitors section. Sense Input (High Sense) for High Current Range (Channel 0). Sense Input (Low Sense) for High Current Range (Channel 0). Force Output for Internal Current Ranges (Channel 0). Guard Output Drive for Channel 0. Guard Amplifier Input for Channel 0/DUTGND Input for Channel 0. This dual function pin is configured via the serial interface. The default function at power-on is GUARDIN0. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH0. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. DUT Voltage Sense Input (High Sense) for Channel 0. Analog Ground. These pins are the reference points for the analog supplies and the measure circuitry. MEASVH2 DUT Voltage Sense Input (High Sense) for Channel 2. CFF0 Description The exposed pad is internally electrically connected to AVSS. For enhanced thermal, electrical, and board level performance, the exposed paddle on the bottom of the package should be soldered to a corresponding thermal land paddle on the PCB. Positive Analog Supply Voltage. Rev. E | Page 16 of 64 Data Sheet Pin No. 13 Mnemonic GUARDIN2/ DUTGND2 14 15 16 17 18 19 GUARD2 FOH2 EXTMEASIL2 EXTMEASIH2 CCOMP2 CFF2 21 EXTFOH2 22, 39, 62, 67, 79 23 AVSS BUSY 24 SCLK 25 CPOL0/SCLK 26 CPOH0/SDI 27 28 29 30 31 SDI SYNC CPOL1/SYNC DGND CPOH1/SDO 32 33 SDO LOAD 34 35 DVCC CPOL2/CPO0 36 CPOH2/CPO1 37 CPOL3/CPO2 38 CPOH3/CPO3 40 EXTFOH3 42 CFF3 43 44 45 46 47 48 CCOMP3 EXTMEASIH3 EXTMEASIL3 FOH3 GUARD3 GUARDIN3/ DUTGND3 AD5522 Description Guard Amplifier Input for Channel 2/DUTGND Input for Channel 2. This dual function pin is configured via the serial interface. The default function at power-on is GUARDIN2. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH2. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. Guard Output Drive for Channel 2. Force Output for Internal Current Ranges (Channel 2). Sense Input (Low Sense) for High Current Range (Channel 2). Sense Input (High Sense) for High Current Range (Channel 2). Compensation Capacitor Input for Channel 2. See the Compensation Capacitors section. External Capacitor for Channel 2. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section. Force Output for High Current Range (Channel 2). Use an external resistor at this pin for current ranges up to ±80 mA. For more information, see the Current Range Selection section. Negative Analog Supply Voltage. Digital Input/Open-Drain Output. This pin indicates the status of the interface. See the BUSY and LOAD Functions section for more information. Serial Clock Input, Active Falling Edge. Data is clocked into the shift register on the falling edge of SCLK. This pin operates at clock speeds up to 50 MHz. Comparator Output Low (Channel 0) for SPI Interface/Differential Serial Clock Input (Complement) for LVDS Interface. Comparator Output High (Channel 0) for SPI Interface/Differential Serial Data Input (Complement) for LVDS Interface. Serial Data Input for SPI or LVDS Interface. Active Low Frame Synchronization Input for SPI or LVDS Interface. Comparator Output Low (Channel 1) for SPI Interface/Differential SYNC Input for LVDS Interface. Digital Ground Reference Point. Comparator Output High (Channel 1) for SPI Interface/Differential Serial Data Output (Complement) for LVDS Interface. Serial Data Output for SPI or LVDS Interface. This pin can be used for data readback and diagnostic purposes. Logic Input (Active Low). This pin synchronizes updates within one device or across a group of devices. If synchronization is not required, LOAD can be tied low; in this case, DAC channels and PMU modes are updated immediately after BUSY goes high. See the BUSY and LOAD Functions section for more information. Digital Supply Voltage. Comparator Output Low (Channel 2) for SPI Interface/Comparator Output Window (Channel 0) for LVDS Interface. Comparator Output High (Channel 2) for SPI Interface/Comparator Output Window (Channel 1) for LVDS Interface. Comparator Output Low (Channel 3) for SPI Interface/Comparator Output Window (Channel 2) for LVDS Interface. Comparator Output High (Channel 3) for SPI Interface/Comparator Output Window (Channel 3) for LVDS Interface. Force Output for High Current Range (Channel 3). Use an external resistor at this pin for current ranges up to ±80 mA. For more information, see the Current Range Selection section. External Capacitor for Channel 3. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section. Compensation Capacitor Input for Channel 3. See the Compensation Capacitors section. Sense Input (High Sense) for High Current Range (Channel 3). Sense Input (Low Sense) for High Current Range (Channel 3). Force Output for Internal Current Ranges (Channel 3). Guard Output Drive for Channel 3. Guard Amplifier Input for Channel 3/DUTGND Input for Channel 3. This dual function pin is configured via the serial interface. The default function at power-on is GUARDIN3. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH3. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. Rev. E | Page 17 of 64 AD5522 Data Sheet Pin No. 49 52 53 Mnemonic MEASVH3 MEASVH1 GUARDIN1/ DUTGND1 54 55 56 57 58 59 GUARD1 FOH1 EXTMEASIL1 EXTMEASIH1 CCOMP1 CFF1 61 EXTFOH1 63 MEASOUT3 64 MEASOUT2 65 MEASOUT1 66 MEASOUT0 68 70 71 72 73 SYS_FORCE SYS_SENSE REFGND VREF DUTGND 75 SPI/LVDS 76 CGALM 77 TMPALM 78 RESET 80 EXTFOH0 Description DUT Voltage Sense Input (High Sense) for Channel 3. DUT Voltage Sense Input (High Sense) for Channel 1. Guard Amplifier Input for Channel 1/DUTGND Input for Channel 1. This dual function pin is configured via the serial interface. The default function at power-on is GUARDIN1. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH1. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. Guard Output Drive for Channel 1. Force Output for Internal Current Ranges (Channel 1). Sense Input (Low Sense) for High Current Range (Channel 1). Sense Input (High Sense) for High Current Range (Channel 1). Compensation Capacitor Input for Channel 1. See the Compensation Capacitors section. External Capacitor for Channel 1. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section. Force Output for High Current Range (Channel 1). Use an external resistor at this pin for current ranges up to ±80 mA. For more information, see the Current Range Selection section. Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 3. This pin is referenced to AGND. Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 2. This pin is referenced to AGND. Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 1. This pin is referenced to AGND. Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 0. This pin is referenced to AGND. External Force Signal Input. This pin enables the connection of the system PMU. External Sense Signal Output. This pin enables the connection of the system PMU. Accurate Analog Reference Input Ground. Reference Input for DAC Channels (5 V for specified performance). DUT Voltage Sense Input (Low Sense). By default, this input is shared among all four PMU channels. If a DUTGND input is required for each channel, the user can configure the GUARDINx/DUTGNDx pins as DUTGND inputs for each PMU channel. Interface Select Pin. Logic low selects SPI-compatible interface mode; logic high selects LVDS interface mode. This pin has a pull-down current source (~350 μA). In LVDS interface mode, the CPOHx and CPOLx pins default to differential interface pins. Open-Drain Output for Guard and Clamp Alarms. This open-drain pin provides shared alarm information about the guard amplifier and clamp circuitry. By default, this output pin is disabled. The system control register allows the user to enable this function and to set the open-drain output as a latched output. The user can also choose to enable alarms for the guard amplifier, the clamp circuitry, or both. When this pin flags an alarm, the origins of the alarm can be determined by reading back the alarm status register. Two flags per channel in this word (one latched, one unlatched) indicate which function caused the alarm and whether the alarm is still present. Open-Drain Output for Temperature Alarm. This latched, active low, open-drain output flags a temperature alarm to indicate that the junction temperature has exceeded the default temperature setting (130°C) or the user programmed temperature setting. Two flags in the alarm status register (one latched, one unlatched) indicate whether the temperature has dropped below 130°C or remains above 130°C. User action is required to clear this latched alarm flag by writing to the clear bit (Bit 6) in any of the PMU registers. Digital Reset Input. This active low, level sensitive input resets all internal nodes on the device to their poweron reset values. Force Output for High Current Range (Channel 0). Use an external resistor at this pin for current ranges up to ±80 mA. For more information, see the Current Range Selection section. Rev. E | Page 18 of 64 80 79 78 77 76 75 74 AVDD CCOMP2 CFF2 EXTMEASIL2 EXTMEASIH2 GUARD2 FOH2 MEASVH2 GUARDIN2/DUTGND2 AGND AGND GUARDIN0/DUTGND0 MEASVH0 FOH0 GUARD0 EXTMEASIL0 CCOMP0 EXTMEASIH0 CFF0 AD5522 AVDD Data Sheet 73 72 71 70 69 68 67 66 65 64 63 62 61 EXTFOH0 1 PIN 1 AVSS 2 60 EXTFOH2 59 AVSS RESET 3 58 BUSY TMPALM 4 57 SCLK CGALM 5 56 CPOL0/SCLK SPI/LVDS 6 55 CPOH0/SDI 54 SDI AVDD 7 AD5522 DUTGND 8 53 SYNC TOP VIEW EXPOSED PAD ON TOP VREF 9 REFGND 10 52 CPOL1/SYNC 51 DGND (Not to Scale) SYS_SENSE 11 50 CPOH1/SDO AGND 12 49 SDO SYS_FORCE 13 48 LOAD AVSS 14 47 DVCC MEASOUT0 15 46 CPOL2/CPO0 MEASOUT1 16 45 CPOH2/CPO1 MEASOUT2 17 44 CPOL3/CPO2 MEASOUT3 18 43 CPOH3/CPO3 AVSS 19 42 AVSS EXTFOH1 20 41 EXTFOH3 AVDD 06197-009 NOTES 1. THE EXPOSED PAD IS ELECTRICALLY CONNECTED TO AVSS. CFF3 CCOMP3 EXTMEASIL3 EXTMEASIH3 FOH3 GUARD3 MEASVH3 GUARDIN3/DUTGND3 AGND AGND MEASVH1 GUARDIN1/DUTGND1 GUARD1 FOH1 EXTMEASIL1 EXTMEASIH1 CCOMP1 CFF1 AVDD 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Figure 9. Pin Configuration, Exposed Pad on Top Table 7. Pin Function Descriptions Pin No. 1 Mnemonic Exposed pad EXTFOH0 2, 14, 19, 42, 59 3 AVSS 4 TMPALM 5 CGALM RESET Description The exposed pad is electrically connected to AVSS. Force Output for High Current Range (Channel 0). Use an external resistor at this pin for current ranges up to ±80 mA. For more information, see the Current Range Selection section. Negative Analog Supply Voltage. Digital Reset Input. This active low, level sensitive input resets all internal nodes on the device to their poweron reset values. Open-Drain Output for Temperature Alarm. This latched, active low, open-drain output flags a temperature alarm to indicate that the junction temperature has exceeded the default temperature setting (130°C) or the user programmed temperature setting. Two flags in the alarm status register (one latched, one unlatched) indicate whether the temperature has dropped below 130°C or remains above 130°C. User action is required to clear this latched alarm flag by writing to the clear bit (Bit 6) in any of the PMU registers. Open-Drain Output for Guard and Clamp Alarms. This open-drain pin provides shared alarm information about the guard amplifier and clamp circuitry. By default, this output pin is disabled. The system control register allows the user to enable this function and to set the open-drain output as a latched output. The user can also choose to enable alarms for the guard amplifier, the clamp circuitry, or both. When this pin flags an alarm, the origins of the alarm can be determined by reading back the alarm status register. Two flags per channel in this word (one latched, one unlatched) indicate which function caused the alarm and whether the alarm is still present. Rev. E | Page 19 of 64 AD5522 Data Sheet Pin No. 6 Mnemonic SPI/LVDS 7, 21, 40, 61, 80 8 AVDD 9 10 11 12, 30, 31, 70, 71 13 15 VREF REFGND SYS_SENSE AGND 16 MEASOUT1 17 MEASOUT2 18 MEASOUT3 20 EXTFOH1 22 CFF1 23 24 25 26 27 28 CCOMP1 EXTMEASIH1 EXTMEASIL1 FOH1 GUARD1 GUARDIN1/ DUTGND1 29 32 33 MEASVH1 MEASVH3 GUARDIN3/ DUTGND3 34 35 36 37 38 39 GUARD3 FOH3 EXTMEASIL3 EXTMEASIH3 CCOMP3 CFF3 41 EXTFOH3 43 CPOH3/CPO3 44 CPOL3/CPO2 45 CPOH2/CPO1 DUTGND SYS_FORCE MEASOUT0 Description Interface Select Pin. Logic low selects SPI-compatible interface mode; logic high selects LVDS interface mode. This pin has a pull-down current source (~350 μA). In LVDS interface mode, the CPOHx and CPOLx pins default to differential interface pins. Positive Analog Supply Voltage. DUT Voltage Sense Input (Low Sense). By default, this input is shared among all four PMU channels. If a DUTGND input is required for each channel, the user can configure the GUARDINx/DUTGNDx pins as DUTGND inputs for each PMU channel. Reference Input for DAC Channels. 5 V for specified performance. Accurate Analog Reference Input Ground. External Sense Signal Output. This pin enables the connection of the system PMU. Analog Ground. These pins are the reference points for the analog supplies and the measure circuitry. External Force Signal Input. This pin enables the connection of the system PMU. Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 0. This pin is referenced to AGND. Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 1. This pin is referenced to AGND. Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 2. This pin is referenced to AGND. Multiplexed DUT Voltage, Current Sense Output, Temperature Sensor Voltage for Channel 3. This pin is referenced to AGND. Force Output for High Current Range (Channel 1). Use an external resistor at this pin for current ranges up to ±80 mA. For more information, see the Current Range Selection section. External Capacitor for Channel 1. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section. Compensation Capacitor Input for Channel 1. See the Compensation Capacitors section. Sense Input (High Sense) for High Current Range (Channel 1). Sense Input (Low Sense) for High Current Range (Channel 1). Force Output for Internal Current Ranges (Channel 1). Guard Output Drive for Channel 1. Guard Amplifier Input for Channel 1/DUTGND Input for Channel 1. This dual function pin is configured via the serial interface. The default function at power-on is GUARDIN1. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH1. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. DUT Voltage Sense Input (High Sense) for Channel 1. DUT Voltage Sense Input (High Sense) for Channel 3. Guard Amplifier Input for Channel 3/DUTGND Input for Channel 3. This dual function pin is configured via the serial interface. The default function at power-on is GUARDIN3. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH3. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. Guard Output Drive for Channel 3. Force Output for Internal Current Ranges (Channel 3). Sense Input (Low Sense) for High Current Range (Channel 3). Sense Input (High Sense) for High Current Range (Channel 3). Compensation Capacitor Input for Channel 3. See the Compensation Capacitors section. External Capacitor for Channel 3. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section. Force Output for High Current Range (Channel 3). Use an external resistor at this pin for current ranges up to ±80 mA. For more information, see the Current Range Selection section. Comparator Output High (Channel 3) for SPI Interface/Comparator Output Window (Channel 3) for LVDS Interface. Comparator Output Low (Channel 3) for SPI Interface/Comparator Output Window (Channel 2) for LVDS Interface. Comparator Output High (Channel 2) for SPI Interface/Comparator Output Window (Channel 1) for LVDS Interface. Rev. E | Page 20 of 64 Data Sheet Pin No. 46 Mnemonic CPOL2/CPO0 47 48 DVCC LOAD 49 50 SDO CPOH1/SDO 51 52 53 54 55 DGND CPOL1/SYNC SYNC SDI CPOH0/SDI 56 CPOL0/SCLK 57 SCLK 58 BUSY 60 EXTFOH2 62 CFF2 63 64 65 66 67 68 CCOMP2 EXTMEASIH2 EXTMEASIL2 FOH2 GUARD2 GUARDIN2/ DUTGND2 69 72 73 MEASVH2 MEASVH0 GUARDIN0/ DUTGND0 74 75 76 77 78 79 GUARD0 FOH0 EXTMEASIL0 EXTMEASIH0 CCOMP0 CFF0 AD5522 Description Comparator Output Low (Channel 2) for SPI Interface/Comparator Output Window (Channel 0) for LVDS Interface. Digital Supply Voltage. Logic Input (Active Low). This pin synchronizes updates within one device or across a group of devices. If synchronization is not required, LOAD can be tied low; in this case, DAC channels and PMU modes are updated immediately after BUSY goes high. See the BUSY and LOAD Functions section for more information. Serial Data Output for SPI or LVDS Interface. This pin can be used for data readback and diagnostic purposes. Comparator Output High (Channel 1) for SPI Interface/Differential Serial Data Output (Complement) for LVDS Interface. Digital Ground Reference Point. Comparator Output Low (Channel 1) for SPI Interface/Differential SYNC Input for LVDS Interface. Active Low Frame Synchronization Input for SPI or LVDS Interface. Serial Data Input for SPI or LVDS Interface. Comparator Output High (Channel 0) for SPI Interface/Differential Serial Data Input (Complement) for LVDS Interface. Comparator Output Low (Channel 0) for SPI Interface/Differential Serial Clock Input (Complement) for LVDS Interface. Serial Clock Input, Active Falling Edge. Data is clocked into the shift register on the falling edge of SCLK. This pin operates at clock speeds up to 50 MHz. Digital Input/Open-Drain Output. This pin indicates the status of the interface. See the BUSY and LOAD Functions section for more information. Force Output for High Current Range (Channel 2). Use an external resistor at this pin for current ranges up to ±80 mA. For more information, see the Current Range Selection section. External Capacitor for Channel 2. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section. Compensation Capacitor Input for Channel 2. See the Compensation Capacitors section. Sense Input (High Sense) for High Current Range (Channel 2). Sense Input (Low Sense) for High Current Range (Channel 2). Force Output for Internal Current Ranges (Channel 2). Guard Output Drive for Channel 2. Guard Amplifier Input for Channel 2/DUTGND Input for Channel 2. This dual function pin is configured via the serial interface. The default function at power-on is GUARDIN2. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH2. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. DUT Voltage Sense Input (High Sense) for Channel 2. DUT Voltage Sense Input (High Sense) for Channel 0. Guard Amplifier Input for Channel 0/DUTGND Input for Channel 0. This dual function pin is configured via the serial interface. The default function at power-on is GUARDIN0. If this pin is configured as a DUTGND input for the channel, the input to the guard amplifier is internally connected to MEASVH0. For more information, see the Device Under Test Ground (DUTGND) section and the Guard Amplifier section. Guard Output Drive for Channel 0. Force Output for Internal Current Ranges (Channel 0). Sense Input (Low Sense) for High Current Range (Channel 0). Sense Input (High Sense) for High Current Range (Channel 0). Compensation Capacitor Input for Channel 0. See the Compensation Capacitors section. External Capacitor for Channel 0. This pin optimizes the stability and settling time performance of the force amplifier when in force voltage mode. See the Compensation Capacitors section. Rev. E | Page 21 of 64 AD5522 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.0020 TA = 25°C NOM: AVDD = +16.5V, AVSS = –16.6V, OFFSET DAC = 0XA492 HIGH: AVDD = +28V, AVSS = –5V, OFFSET DAC = 0X0 LOW: AVDD = +10V, AVSS = –23V, OFFSET DAC = 0xEDB7 0.8 0.0015 0.6 LINEARITY (% FSR) 0.2 0 –0.2 –0.4 0.0010 0.0005 –0.6 0 06197-010 DNL INL –0.8 –1.0 0 10,000 20,000 30,000 40,000 50,000 –0.0005 60,000 0 10,000 20,000 CODE 30,000 40,000 50,000 60,000 CODE Figure 10. Force Voltage Linearity vs. Code, All Ranges, 1 LSB = 0.0015% FSR (20 V FSR) Figure 13. Measure Voltage Linearity vs. Code, All Ranges, MEASOUTx Gain = 0.2 2.0 5 TA = 25°C TA = 25°C 4 1.5 DNL INL 3 1.0 2 LINEARITY (LSB) LINEARITY (LSB) 06197-140 LINEARITY (LSB) 0.4 0.5 0 –0.5 1 0 –1 –2 –1.0 06197-011 DNL INL –2.0 0 10,000 20,000 30,000 40,000 50,000 06197-013 –3 –1.5 –4 –5 60,000 0 10,000 20,000 CODE 40,000 50,000 60,000 CODE Figure 11. Force Current Linearity vs. Code, All Ranges, 1 LSB = 0.0015% FSR (20 V FSR) Figure 14. Measure Current Linearity vs. Code, All Ranges, 1 LSB = 0.0015% FSR (20 V FSR), MI Gain = 10, MEASOUTx Gain = 1 2.0 0.035 TA = 25°C 0.030 1.0 0.025 LINEARITY (% FSR) 1.5 0.5 0 –0.5 AVDD = +15.5V, AVSS = –15.5V, OFFSET DAC = 0xA492 AVDD = +28V, AVSS = –5V, OFFSET DAC = 0x0 AVDD = +10V, AVSS = –23V, OFFSET DAC = 0xEDB7 0.020 0.015 0.010 0.005 –1.0 0 DNL INL –2.0 0 10,000 20,000 30,000 40,000 50,000 –0.005 –0.001 60,000 0 CODE 10,000 20,000 30,000 40,000 50,000 60,000 CODE Figure 12. Measure Voltage Linearity vs. Code, All Ranges, 1 LSB = 0.0015% FSR (20 V FSR), MEASOUTx Gain = 1 Figure 15. Measure Current Linearity vs. Code, All Ranges, MEASOUTx Gain = 0.2, MI Gain = 10 Rev. E | Page 22 of 64 06197-141 –1.5 06197-012 LINEARITY (LSB) 30,000 Data Sheet AD5522 0.005 0.2 AVDD = +15.5V, AVSS = –15.5V, OFFSET DAC = 0xA492 AVDD = +28V, AVSS = –5V, OFFSET DAC = 0x0 AVDD = +10V, AVSS = –23V, OFFSET DAC = 0xED87 0.001 0 –0.001 –0.2 –0.4 EXTFOHx CFFx FOHx EXTMEASIHx EXTMEASILx MEASVHx GUARDINx/DUTGNDx COMBINED LEAKAGE –0.6 –0.8 –1.0 06197-142 –0.002 –0.003 10,000 20,000 30,000 40,000 50,000 60,000 –1.2 25 35 45 55 85 95 0.15 1.0 TA = 25°C V = 0V EXTFOHx CFFx FOHx EXTMEASIHx EXTMEASILx MEASVHx GUARDINx/DUTGNDx COMBINED LEAKAGE 0.6 0.4 0.10 LEAKAGE CURRENT (nA) 0.8 0.2 0 0.05 0 EXTFOHx CFFx FOHx EXTMEASIHx EXTMEASILx MEASVHx GUARDINx/DUTGNDx COMBINED LEAKAGE –0.05 –0.10 06197-014 –0.15 35 45 55 65 75 85 –0.20 –12 –10 95 –8 TEMPERATURE (°C) –6 –4 –2 0 2 4 STRESS VOLTAGE (V) 6 8 10 12 Figure 20. Leakage Current vs. Stress Voltage Figure 17. Leakage Current vs. Temperature (Stress Voltage = 0 V) 0 2.0 V = 12V EXTFOHx CFFx FOHx EXTMEASIHx EXTMEASILx MEASVHx GUARDINx/DUTGNDx COMBINED LEAKAGE 1.0 AVDD ACPSRR AVSS ACPSRR DVCC ACPSRR –40 ACPSRR (dB) 1.5 –20 0.5 –60 –80 0 06197-015 –0.5 25 –100 35 45 55 65 75 85 –120 10 95 TEMPERATURE (°C) 100 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 21. ACPSRR at FOHx in Force Voltage Mode vs. Frequency Figure 18. Leakage Current vs. Temperature (Stress Voltage = 12 V) Rev. E | Page 23 of 64 06197-018 LEAKAGE CURRENT (nA) 75 Figure 19. Leakage Current vs. Temperature (Stress Voltage = −12 V) Figure 16. Measure Current Linearity vs. Code, All Ranges, MEASOUTx Gain = 0.2, MI Gain = 5 –0.2 25 65 TEMPERATURE (°C) CODE 06197-017 0 V = –12V 06197-016 0.002 LEAKAGE CURRENT (nA) LINEARITY (% FSR) 0.003 0 LEAKAGE CURRENT (nA) 0.004 AD5522 Data Sheet 0 0 –10 –10 –20 –20 VSS VDD –40 –50 VCC –60 –40 ACPSRR (dB) –60 –100 100 1k 10k FREQUENCY (Hz) 1M 100k 06197-019 –90 –90 –110 10 1M 100k 0 0 –10 –10 VSS –20 –20 VSS –30 –30 VDD VDD ACPSRR (dB) –40 –40 –50 VCC –60 –70 –50 VCC –60 –70 –90 –90 –100 –100 –110 100 1k 10k FREQUENCY (Hz) 1M 100k –120 10 100 1k 10k FREQUENCY (Hz) 1M 100k 06197-021 –80 –80 06197-119 ACPSRR (dB) 1k 10k FREQUENCY (Hz) Figure 25. ACPSRR at MEASOUTx in Measure Voltage Mode vs. Frequency (MEASOUT Gain = 0.2) Figure 22. ACPSRR at FOHx in Force Current Mode vs. Frequency (MI Gain = 10) Figure 26. ACPSRR at MEASOUTx in Measure Current Mode vs. Frequency (MI Gain = 10, MEASOUT Gain = 1) Figure 23. ACPSRR at FOHx in Force Current Mode vs. Frequency (MI Gain = 5) 0 0 –10 –10 –20 VSS –20 VSS –30 –30 VDD ACPSRR (dB) –40 –40 ACPSRR (dB) 100 06197-120 –80 –80 VDD –50 VCC –60 –70 –50 VCC –60 –70 –80 –80 –90 –90 –100 –100 –110 –110 100 1k 10k FREQUENCY (Hz) 100k 1M –120 10 06197-020 –120 10 VCC –70 –70 –110 10 VDD –50 Figure 24. ACPSRR at MEASOUTx in Measure Voltage Mode vs. Frequency (MEASOUT Gain = 1) 100 1k 10k FREQUENCY (Hz) 100k 1M 06197-121 ACPSRR (dB) –30 –100 10 VSS –30 Figure 27. ACPSRR at MEASOUTx in Measure Current Mode vs. Frequency (MI Gain = 5, MEASOUT Gain = 1) Rev. E | Page 24 of 64 Data Sheet AD5522 0 TA = 25°C –10 –20 –30 1 ACPSRR (dB) –40 FOH0 VSS –50 –60 VCC –70 MEASOUT0 VDD 2 –80 –90 4 LOAD 06197-023 –100 –120 10 100 1k 10k FREQUENCY (Hz) 1M 100k 06197-122 –110 B B CH2 100mV W CH4 5.00V CH1 Pk-Pk 39.00mV CH2 Pk-Pk 325.8mV CH1 20.0mV Figure 28. APCSRR at MEASOUTx in Measure Current Mode vs. Frequency (MI Gain = 10, MEASOUT Gain = 0.2) W M4.00µs T 10.0000µs Figure 31. AC Crosstalk, FVMI Mode, PMU 0, Full-Scale Transition on One CPH DAC, MI Gain = 10, MEASOUT Gain = 1, ±2 mA Range, CLOAD = 200 pF 0 TA = 25°C –10 –20 –30 VDD 1 ACPSRR (dB) –40 FOH1 VSS –50 VCC –60 –70 MEASOUT1 2 –80 –90 –100 LOAD 06197-024 4 –120 10 100 1k 10k FREQUENCY (Hz) 100k 1M 06197-123 –110 B M4.00µs W CH4 5.00V T 10.0000µs CH1 Pk-Pk 18.80mV CH2 Pk-Pk 140.0mV Figure 29. APCSRR at MEASOUTx in Measure Current Mode vs. Frequency (MI Gain = 5, MEASOUT Gain = 0.2) W CH2 100mV Figure 32. AC Crosstalk, FVMI Mode, PMU 1, Full-Scale Transition on One CPH DAC, MI Gain = 10, MEASOUT Gain = 1, ±2 mA Range, CLOAD = 200 pF 900 T MEASURE CURRENT IN-AMP MEASURE VOLTAGE IN-AMP FORCE AMP 800 B CH1 20.0mV ATTACK FROM FIN1 16.70mV p-p 700 1 FOH0 NSD (nV/ Hz) 600 ATTACK FROM FIN2 10.35mV p-p FOH0 500 1 ATTACK FROM FIN3 11.75mV p-p 400 FOH0 300 1 06197-022 100 0 10 06197-025 200 100 1k 10k 100k CH1 10mV 1M FREQUENCY (Hz) Figure 30. NSD vs. Frequency (Measured in FVMV and FVMI Mode) B W M10µs T 30.0µs Figure 33. AC Crosstalk at FOH0 in FI Mode from FIN DAC of Each Other PMU (FullScale Transition), MI Gain = 10, MEASOUT Gain = 1, ±2 mA Range, CLOAD = 200 pF Rev. E | Page 25 of 64 AD5522 Data Sheet TA = 25°C SYNC 4 3 1 2 BUSY FOHx VICTIM MEASOUTx VICTIM FOH0 1 TRIGGER 4 B CH1 10.0mV W CH2 50.0mV CH3 5.00V CH4 5.00V CH2 Pk-Pk 14.38mV B W 06197-129 06197-026 MEASOUTx ATTACK 3 M100µs T 200.000µs CH1 50.0mV Figure 34. Shorted DUT AC Crosstalk, Victim PMU in FVMI Mode (±200 μA Range) B W CH3 5.00V BW CH4 5.00V BW M800ns CH4 T 2.40000µs 2.10V Figure 37. Range Change, PMU0, ±2 mA to ±5 μA, CLOAD = 1 nF, RLOAD = 620 kΩ, FV = 3 V MEASOUTx VOLTAGE (V) 1.80 SYNC 1.75 4 1.70 3 BUSY 1.65 1.60 FOH0 1.55 1 1.40 25 35 45 55 65 75 06197-127 NOMINAL SUPPLIES ±15.25V 5 DIFFERENT DEVICES 1.45 06197-130 1.50 CH1 20.0mV 85 B W FORCED TEMPERATURE (°C) M20.0µs CH4 T 60.0000µs 2.10V Figure 38. Range Change, PMU0, ±5 μA to ±2 mA, CLOAD = 100 nF, RLOAD = 620 kΩ, FV = 3 V Figure 35. Temperature Sensor Voltage on MEASOUTx vs. Forced Temperature SYNC SYNC 4 3 CH3 5.00V BW CH4 5.00V BW 4 BUSY BUSY 3 FOH0 FOH0 11 CH1 100mV B W CH3 5.00V BW CH4 5.00V BW M2.00µs CH4 T 6.0000µs 06197-131 06197-128 1 CH1 20.0mV 2.10V Figure 36. Range Change, PMU0, ±5 μA to ±2 mA, CLOAD = 1 nF, RLOAD = 620 kΩ, FV = 3 V B W CH3 5.00V BW CH4 5.00V BW M20.0µs CH4 T 60.0000µs 2.10V Figure 39. Range Change, PMU0, ±2 mA to ±5 μA, CLOAD = 100 nF, RLOAD = 620 kΩ, FV = 3 V Rev. E | Page 26 of 64 Data Sheet 4 AD5522 SYNC SYNC 4 BUSY 3 BUSY 3 MEASOUTx (MI) FOH0 2 1 FOHx CH1 100.0mV B W CH3 5.00V BW CH4 5.00V BW M2.00µs CH4 T 6.00000µs 06197-135 06197-132 1 2.10V CH1 2.00V CH3 5.00V CH2 2.00V CH4 5.00V M5.0µs CH1 3.84V Figure 43. FV Settling, 0 V to 5 V, ±2 mA Range, CLOAD = 220 pF, CCOMPx = 100 pF, RLOAD = 5.6 kΩ Figure 40. Range Change, PMU0, ±20 μA to ±2 mA, CLOAD = 1 nF, RLOAD = 150 kΩ, FV = 3 V SYNC SYNC 4 4 3 BUSY BUSY 3 MEASOUTx (MI) FOH0 2 FOHx 1 06197-133 06197-136 1 CH1 50.0mV B W CH3 5.00V BW CH4 5.00V BW M2.000µs CH4 T 6.00000µs CH1 2.00V CH3 5.00V 2.10V CH2 10.00V CH4 5.00V M100µs CH1 3.20V Figure 44. FV Settling, 0 V to 5 V, ±5 μA Range, CLOAD = 220 pF, CCOMPx = 100 pF, RLOAD = 1 MΩ Figure 41. Range Change, PMU0, ±2 mA to ±20 μA, CLOAD = 1 nF, RLOAD = 150 kΩ, FV = 3 V SYNC SYNC 4 4 BUSY BUSY 3 3 MEASOUTx (MI) MEASOUTx (MI) 2 2 FOHx FOHx 1 CH1 2.00V CH3 5.00V CH2 2.00V CH4 5.00V M10.0µs CH1 06197-137 06197-134 1 CH1 2.00V CH3 5.00V 3.84V CH2 10.0V CH4 5.00V M25.0µs CH1 3.20V Figure 45. FV Settling, 0 V to 5 V, ±20 μA Range, CLOAD = 220 pF, CCOMPx = 100 pF, RLOAD = 270 kΩ Figure 42. FV Settling, 0 V to 5 V, ±2 mA Range, CLOAD = 220 pF, CCOMPx = 1 nF, RLOAD = 5.6 kΩ Rev. E | Page 27 of 64 AD5522 Data Sheet SYNC 4 BUSY 3 MEASOUTx (MI) 2 FOHx 06197-138 1 CH1 2.00V CH3 5.00V CH2 10.0V CH4 5.00V M10.0µs CH1 3.20V Figure 46. FV Settling, 0 V to 5 V, ±200 μA Range, CLOAD = 220 pF, CCOMPx = 100 pF, RLOAD = 27 kΩ Rev. E | Page 28 of 64 Data Sheet AD5522 TERMINOLOGY Offset Error Offset error is a measure of the difference between the actual voltage and the ideal voltage at midscale or at zero current expressed in mV or % FSR. Gain Error Gain error is the difference between full-scale error and zeroscale error. It is expressed in % FSR. Gain Error = Full-Scale Error − Zero-Scale Error where: Full-Scale Error is the difference between the actual voltage and the ideal voltage at full scale. Zero-Scale Error is the difference between the actual voltage and the ideal voltage at zero scale. Linearity Error Linearity error, or relative accuracy, is a measure of the maximum deviation from a straight line passing through the endpoints of the full-scale range. It is measured after adjusting for gain error and offset error and is expressed in % FSR. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. Common-Mode (CM) Error Common-mode (CM) error is the error at the output of the amplifier due to the common-mode input voltage. It is expressed in % of FSVR/V. Leakage Current Leakage current is the current measured at an output pin when that function is off or high impedance. Pin Capacitance Pin capacitance is the capacitance measured at a pin when that function is off or high impedance. Slew Rate The slew rate is the rate of change of the output voltage expressed in V/μs. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a full-scale input change. Digital-to-Analog Glitch Energy Digital-to-analog glitch energy is the amount of energy that is injected into the analog output at the major code transition. It is specified as the area of the glitch in nV-sec. It is measured by toggling the DAC register data between 0x7FFF and 0x8000. Digital Crosstalk Digital crosstalk is defined as the glitch impulse transferred to the output of one converter due to a change in the DAC register code of another converter. It is specified in nV-sec. AC Crosstalk AC crosstalk is defined as the glitch impulse transferred to the output of one PMU due to a change in any of the DAC registers in the package. ACPSRR ACPSRR is a measure of the ability of the device to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.2 V p-p. The ratio of the amplitude of the signal on the output to the amplitude of the modulation is the ACPSRR. Rev. E | Page 29 of 64 AD5522 Data Sheet THEORY OF OPERATION The AD5522 is a highly integrated, quad per-pin parametric measurement unit (PPMU) for use in semiconductor automated test equipment. It provides programmable modes to force a pin voltage and measure the corresponding current (FVMI) and to force a pin current and measure the corresponding voltage (FIMV). The device is also capable of all other combinations, including force high-Z and measure high-Z. The PPMU can force or measure a voltage range of 22.5 V. It can force or measure currents up to ±80 mA per channel using the internal amplifier; the addition of an external amplifier enables higher current ranges. All the DAC levels required for each PMU channel are on chip. FORCE AMPLIFIER The force amplifier drives the analog output, FOHx, which drives a programmed current or voltage to the device under test (DUT). Headroom and footroom requirements for this amplifier are 3 V on either end. An additional ±1 V is dropped across the sense resistor when maximum (rated) current is flowing through it. The force amplifier is designed to drive DUT capacitances up to 10 nF, with a compensation value of 100 pF. Larger DUT capacitive loads require larger compensation capacitances. Local feedback ensures that the amplifiers are stable when disabled. A disabled channel reduces power consumption by 2.5 mA per channel. COMPARATORS Per channel, the DUT measured voltage or current is monitored by two comparators configured as window comparators. Internal DAC levels set the CPL (comparator low) and CPH (comparator high) threshold values. There are no restrictions on the voltage settings of the comparator highs and lows. CPL going higher than CPH is not a useful operation; however, it does not cause any problems with the device. CPOLx (comparator output low) and CPOHx (comparator output high) are continuous time comparator outputs. Table 8. Comparator Output Function Using SPI Interface Test Condition VDUT or IDUT > CPH VDUT or IDUT < CPH VDUT or IDUT > CPL VDUT or IDUT < CPL CPH > VDUT or IDUT > CPL CPOLx 1 0 1 window. Information on whether the measurement was high or low is available via the serial interface (comparator status register). Table 9. Comparator Output Function Using LVDS Interface Test Condition (CPL < (VDUT or IDUT)) and ((VDUT or IDUT) < CPH) (CPL > (VDUT or IDUT)) or ((VDUT or IDUT) > CPH) CPOx Output 1 0 CLAMPS Current and voltage clamps are included on chip, one clamp for each PMU channel. The clamps protect the DUT in the event of an open-circuit or short-circuit condition. Internal DAC levels set the CLL (clamp low) and CLH (clamp high) levels. The clamps work to limit the force amplifier if a voltage or current at the DUT exceeds the set levels. The clamps also protect the DUT if a transient voltage or current spike occurs when changing to a different operating mode or when programming the device to a different current range. The voltage clamps are available while forcing current, and the current clamps are available while forcing voltage. The user can set up the voltage or current clamp status (enabled or disabled) using the serial interface (system control register or PMU register). Each clamp has a smooth, finite transition region between normal (unclamped) operation and the final clamped level, and an internal flag is activated within this transition zone. The open-drain CGALM pin indicates whether one or more PMU channels has clamped. The clamp status of an individual PMU can be determined by polling the alarm status register using the SPI or LVDS interface. CLL should never be greater than CLH. For the voltage clamps, there should be 500 mV between the CLL and CLH levels to ensure that a region exists in the middle of the clamps where both are off. Similarly, set current clamps ±250 mV away from 0 A. The transfer function for voltage clamping in FI mode is VCLL or VCLH = 4.5 × VREF × (DAC_CODE/216) − (3.5 × VREF × (OFFSET_DAC_CODE/216)) + DUTGND CPOHx 0 1 See the DAC Levels section for more information. 1 where: RSENSE is the sense resistor of the selected current range. MI_Amplifier_Gain is the gain of the measure current instrumentation amplifier, either 5 or 10. When using the SPI interface, full comparator functionality is available. When using the LVDS interface, the comparator function is limited to one output per comparator, due to the large pin count requirement of the LVDS interface. When using the LVDS interface, the comparator output available pins, CPO0 to CPO3, provide information on whether the measured voltage or current is inside or outside the set CPH and CPL The transfer function for current clamping in FV mode is ICLL or ICLH = 4.5 × VREF × ((DAC_CODE − 32,768)/216)/(RSENSE × MI_Amplifier_Gain) Do not change clamp levels while the channel is in force mode because this can affect the forced voltage or current applied to the DUT. Similarly, the clamps should not be enabled or disabled during a force operation. Rev. E | Page 30 of 64 Data Sheet AD5522 where: FI is the forced current. RSENSE is the selected sense resistor. MI_Amplifier_Gain is the gain of the measure current instrumentation amplifier. This gain can be set to 5 or 10 via the serial interface. When the AD5522 is placed in high-Z mode, the clamp circuit is always configured to monitor the measure current signal (irrespective of which high-Z mode is selected, high-Z V or high-Z I). At this time, the clamp circuit is also comparing to the voltage clamp levels. Because the device is in high-Z mode, the measure current signal is at zero, but zero for the measure current is always the VMID voltage set by the offset DAC. For default offset DAC conditions, this causes no concern. For other settings of the offset DAC, the zero point follows the VMID, and as the clamp circuit is comparing the voltage clamp levels to the measure current signal, there may be instances where the voltage clamp levels cause the alarm to flag during high-Z mode. To avoid this, the clamps can be disabled when going into high-Z mode. In the ±200 μA range with the 5 kΩ sense resistor and an ISENSE gain of 10, the maximum current range possible is ±225 μA. Similarly, for the other current ranges, there is an overrange of 12.5% to allow for error correction. Also, the forced current range is the quoted full-scale range only with an applied reference of 5 V or 2.5 V (with ISENSE amplifier gain = 5). The ISENSE amplifier is biased by the VMID DAC voltage in such a way as to center the measure current output irrespective of the voltage span used. CURRENT RANGE SELECTION Integrated thin film resistors minimize the need for external components and allow easy selection of any of these current ranges: ±5 µA (200 kΩ), ±20 μA (50 kΩ), ±200 μA (5 kΩ), and ±2 mA (500 Ω). One current range up to ±80 mA can be accommodated per channel by connecting an external sense resistor. For current ranges in excess of ±80 mA, it is necessary that an external amplifier be used. When using the EXTFOHx outputs for current ranges up to ±80 mA, there is no switch in series with the EXTFOHx line, ensuring minimum capacitance present at the output of the force amplifier. This feature is important when using a pin electronics driver to provide high current ranges. HIGH CURRENT RANGES With the use of an external high current amplifier, one high current range in excess of ±80 mA is possible. The high current amplifier buffers the force output and provides the drive for the required current. For the suggested current ranges, the maximum voltage drop across the sense resistors is ±1 V. However, to allow for error correction, there is some overrange available in the current ranges (±12.5% or ±0.125 V across RSENSE). The full-scale voltage range that can be loaded to the FIN DAC is ±11.5 V; the forced current can be calculated as follows: To eliminate any timing concerns when switching between the internal ranges and the external high current range, there is a mode where the internal ±80 mA stage can be enabled at all times. See Table 26 for more information. FI = 4.5 × VREF × ((DAC_CODE − 32,768)/216)/(RSENSE × MI_Amplifier_Gain) HIGH CURRENT AMPLIFIER EN EXTFOHx CFFx INTERNAL RANGE SELECT (±5µA, ±20µA, ±200µA, ±2mA) DAC FIN + FOHx RSENSE – 4kΩ VMID TO CENTER I RANGE ×1 OR ×0.2 RSENSE 2kΩ + ×5 or ×10 – EXTMEASILx + – 4kΩ MEASVHx AGND + – DUT + DUTGND ×1 – + – Figure 47. Addition of High Current Amplifier for Wider Current Range (>±80 mA) Rev. E | Page 31 of 64 06197-028 MEASOUTx EXTMEASIHx + – AD5522 Data Sheet MEASURE CURRENT GAINS VREF = 3.5 V results in a ±7.87 V range. Using a gain setting of 10, there is ±0.785 V maximum across RSENSE, resulting in current ranges of ±3.92 μA, ±15.74 μA, and so on (including overrange of ±12.5% to allow for error correction). The measure current amplifier has two gain settings, 5 and 10. The two gain settings allow users to achieve the quoted/specified current ranges with large or small voltage swing. Use the 10 gain setting with a 5 V reference, and use the 5 gain setting with a 2.5 V reference. Both combinations ensure the specified current ranges. Using other VREF/gain setting combinations should achieve smaller current ranges only. Achieving greater current ranges than the specified ranges is outside the intended operation of the AD5522. The maximum guaranteed voltage across RSENSE = ±1.125 V. VMID VOLTAGE The midcode voltage (VMID) is used in the measure current amplifier block to center the current ranges about 0 A. This is required to ensure that the quoted current ranges can be achieved when using offset DAC settings other than the default. VMID corresponds to 0x8000 or the DAC midcode value, that is, the middle of the voltage range set by the offset DAC setting (see Table 13). See the block diagram in Figure 48. Following are examples of VREF/gain setting combinations. In these examples, the offset DAC is at its default value of 0xA492. • VREF = 5 V results in a ±11.25 V range. Using a gain setting of 10, there is ±1.125 V maximum across RSENSE, resulting in current ranges of ±5.625 μA, ±22.5 μA, and so on (including overrange of ±12.5% to allow for error correction). VREF = 2.5 V results in a ±5.625 V range. Using a gain setting of 5 results in current ranges of ±5.625 μA, ±22.5 μA, and so on (including overrange of ±12.5% to allow for error correction). or VMID = 3.5 × VREF × ((42,130 − OFFSET_DAC_CODE)/216) VMIN = −3.5 × VREF × (OFFSET_DAC_CODE/216) VREF VTOP VDAC_MID VMID DATA ADDRESS DAC DAC HV AMP VOFFSET 2R 7R VDAC_MIN VMIN REFGND DAC HV AMP VOFFSET 2R 10R 7R MEASURE CURRENT IN-AMP SEL×10 ATTB SEL×5 1R ATT 5R INAMP10 MEASOUTx 50Ω INT/EXTMEASIHx 1R 1R INT/EXTMEASILx 1R MI 5R 10R SEL×5 ATTB SEL×10 1R ATTB AGND 1R MEASVHx 5R INAMP1 ATT MV DUTGND 1R 1R R AGND ATT = ATTENUATION FOR MEASOUTx ×0.2 MI = MEASURE CURRENT MV = MEASURE VOLTAGE SEL×5 = MI GAIN = 5 SEL×10 = MI GAIN = 10 Figure 48. Measure Block and VMID Influence Rev. E | Page 32 of 64 MEASURE VOLTAGE IN-AMP 06197-043 • VMID = 4.5 × VREF × (32,768/216) − (3.5 × VREF × (OFFSET_DAC_CODE/216)) Data Sheet AD5522 CHOOSING POWER SUPPLY RAILS MEASURE OUTPUT (MEASOUTx PINS) As noted in the Specifications section, the minimum supply variation across the part |AVDD − AVSS| ≥ 20 V. For the AD5522 circuits to operate correctly, the supply rails must take into account not only the force voltage range, but also the internal DAC minimum voltage level, as well as headroom and so on. The DAC amplifier gains VREF by 4.5, and the offset DAC centers that range about some chosen point. The measured DUT voltage or current (voltage representation of DUT current) is available on the MEASOUTx pin with respect to AGND. The default MEASOUTx range is the forced voltage range for voltage measure and current measure (nominally ±11.25 V, depending on the reference voltage and offset DAC) and includes some overrange to allow for offset correction. The serial interface allows the user to select another MEASOUTx range of 0.9 × VREF to AGND, allowing an ADC with a 5 V input range to be used. The MEASOUTx line for each PMU channel can be made high impedance via the serial interface. The supplies need to cater to the DAC output voltage range to avoid impinging on other parts of the circuit (for example, if the measure current block for rated current ranges has a gain of 10/5, the supplies need to provide sufficient headroom and footroom to not clip the measure current circuit when full current range is required). The offset DAC directly offsets the measured output voltage level, but only when GAIN1 = 0. When the MEASOUT gain is 0.2, the minimum code from the DAC is used to center the MEASOUTx voltage and to ensure that the voltage is within the range of 0 to 0.9 × VREF (see Figure 48). Also, the MEASOUT gain = 0.2 setting uses the VMIN level for scaling purposes; if there is not enough footroom for this VMIN level, then the MV and MI output voltage range is affected. When using low supply voltages, ensure that there is sufficient headroom and footroom for the DAC output range (set by the VREF and offset DAC setting). For the MEASOUT gain = 0.2 setting, it is important to choose AVSS based on the following: DEVICE UNDER TEST GROUND (DUTGND) AVSS ≤ −3.5 × (VREF × (OFFSET_DAC_CODE/216)) − AVSS_footroom − VDUTGND − (RCABLE × ILOAD) By default, there is one DUTGND input available for all four PMU channels. However, in some PMU applications, it is necessary that each channel operate from its own DUTGND level. The dual function pin, GUARDINx/DUTGNDx, can be configured as an input to the guard amplifier (GUARDIN) or as a DUTGND input for each channel. where: AVSS_footroom = 4 V. VDUTGND is the voltage range anticipated at DUTGND. RCABLE is the cable/path resistance. ILOAD is the maximum load current. The pin function can be configured through the serial interface on power-on for the required operation. The default connection is SW13b (GUARDIN) and SW14b (shared DUTGND). Table 10. MEASOUTx Output Ranges for GAIN1 = 0, MEASOUT Gain = 1 MEASOUT Function MV MI GAIN0 = 0 GAIN0 = 1 1 Output Voltage Range for VREF = 5 V 1 Offset DAC = 0x0 Offset DAC = 0xA492 Offset DAC = 0xED67 0 V to 22.5 V ±11.25 V −16.26 V to +6.25 V Measure Current Gain 5 or 10 Transfer Function ±VDUT 10 5 (IDUT × RSENSE × 10) + VMID (IDUT × RSENSE × 5) + VMID 0 V to 22.5 V 0 V to 11.25 V (VREF = 2.5 V) ±11.25 V ±5.625 V (VREF = 2.5 V) −16.26 V to +6.25 V −8.13 V to +3.12 V (VREF = 2.5 V) VREF = 5 V unless otherwise noted. Table 11. MEASOUTx Output Ranges for GAIN1 = 1, MEASOUT Gain = 0.2 MEASOUT Function MV MI GAIN0 = 0 GAIN0 = 1 1 2 Measure Current Gain 5 or 10 Transfer Function 0.2 × (VDUT × VREF × OFFSET_DAC_CODE/216) Output Voltage Range for VREF = 5 V 1, 2 0 V to 4.5 V (±2.25 V centered around 2.25 V) 10 5 (IDUT × RSENSE × 10 × 0.2) + (0.45 × VREF) (IDUT × RSENSE × 5 × 0.2) + (0.45 × VREF) 0 V to 4.5 V (±2.25 V centered around 2.25 V) 1.125 V to 3.375 V (±1.125 V, centered around 2.25 V) 0 V to 2.25 V (±1.125 V, centered around 1.125 V) (VREF = 2.5 V) VREF = 5 V unless otherwise noted. The offset DAC setting has no effect on the output voltage range. Rev. E | Page 33 of 64 AD5522 Data Sheet When configured as DUTGND per channel, this dual function pin is no longer connected to the input of the guard amplifier. Instead, it is connected to the low end of the instrumentation amplifier (SW14a), and the input of the guard amplifier is connected internally to MEASVHx (SW13a). MEASVH[0:3] + – a SW13 AGND SW14 a b GUARD GUARD[0:3] AMP GUARDIN[0:3]/ DUTGND[0:3] + – b DUTGND MEASURE VOLTAGE IN-AMP 06197-029 + ×1 – DUT SW16 Figure 49. Using the DUTGND per Channel Feature GUARD AMPLIFIER A guard amplifier allows the user to bootstrap the shield of the cable to the voltage applied to the DUT, ensuring minimal drops across the cable. This is particularly important for measurements requiring a high degree of accuracy and in leakage current testing. If not required, all four guard amplifiers can be disabled via the serial interface (system control register). Disabling the guard amplifiers decreases power consumption by 400 μA per channel. As described in the Device Under Test Ground (DUTGND) section, GUARDINx/DUTGNDx are dual function pins. Each pin can function either as a guard amplifier input for one channel or as a DUTGND input for one channel, depending on the requirements of the end application (see Figure 49). A guard alarm event occurs when the guard output moves more than 100 mV away from the guard input voltage for more than 200 μs. In this case, the event is flagged via the open-drain output CGALM. Because the guard and clamp alarm functions share the same alarm output, CGALM, the alarm information (alarm trigger and alarm channel) is available via the serial interface in the alarm status register. COMPENSATION CAPACITORS Each channel requires an external compensation capacitor (CCOMP) to ensure stability into the maximum load capacitance while ensuring that settling time is optimized. In addition, one CFF pin per channel is provided to further optimize stability and settling time performance when in force voltage (FV) mode. When changing from force current (FI) mode to FV mode, the internal switch connecting the CFF capacitor is automatically closed. Although the force amplifier is designed to drive load capacitances up to 10 nF (with CCOMP capacitor = 100 pF), it is possible to use larger compensation capacitor values to drive larger loads, at the expense of an increase in settling time. If a wide range of load capacitances must be driven, an external multiplexer connected to the CCOMPx pin allows optimization of settling time vs. stability. The series resistance of a switch placed on CCOMPx should typically be <50 Ω. Suitable multiplexers for use are the ADG1404, ADG1408, or one of the multiplexers in the ADG4xx family, which typically have on resistances of less than 50 Ω. Similarly, connecting the CFF node to an external multiplexer accommodates a wide range of CDUT in FV mode. The ADG1204 or ADG1209 family of multiplexers meet these requirements. The series resistance of the multiplexer used should be such that 1/(2π × RON × CDUT) > 100 kHz The voltage range of the CFFx and CCOMPx pins is the same as the voltage range expected on the FOHx pin; therefore, choice of capacitor must take this into account. Table 12. Suggested Compensation Capacitor Selection CLOAD ≤1 nF ≤10 nF ≤100 nF Alternatively, the serial interface allows the user to set up the CGALM output to flag either the clamp status or the guard status. By default, this open-drain alarm pin is an unlatched output, but it can be configured as a latched output via the serial interface (system control register). Rev. E | Page 34 of 64 CCOMP Capacitor 100 pF 100 pF CLOAD/100 CFF Capacitor 220 pF 1 nF CLOAD/10 Data Sheet AD5522 TEMPERATURE SENSOR SYSTEM FORCE AND SENSE SWITCHES An on-board temperature sensor monitors die temperature. The temperature sensor is located at the center of the die. If the temperature exceeds the factory specified value (130°C) or a user programmable value, the device protects itself by shutting down all channels and flagging an alarm through the latched, open-drain TMPALM pin. Alarm status can be read back from the alarm status register or the PMU register, where latched and unlatched bits indicate whether an alarm has occurred and whether the temperature has dropped below the set alarm temperature. The shutdown temperature is set using the system control register. Each channel has switches to allow connection of the force (FOHx) and sense (MEASVHx) lines to a central PMU for calibration purposes. There is one set of SYS_FORCE and SYS_SENSE pins per device. It is recommended that these connections be made individually to each PMU channel. FOH0 FOH1 SYS_FORCE FOH2 FOH3 MEASVH0 MEASVH1 MEASVH3 06197-042 SYS_SENSE MEASVH2 Figure 50. SYS_FORCE and SYS_SENSE Connections to FOHx and MEASVHx Pins Rev. E | Page 35 of 64 AD5522 Data Sheet DAC LEVELS Each channel contains five dedicated DAC levels: one for the force amplifier, one each for the clamp high and clamp low levels, and one each for the comparator high and comparator low levels. The power supplies should be selected to support the required range and should take into account amplifier headroom and footroom and sense resistor voltage drop (±4 V). The architecture of a single DAC channel consists of a 16-bit resistor-string DAC followed by an output buffer amplifier. This resistor-string architecture guarantees DAC monotonicity. The 16-bit binary digital code loaded to the DAC register determines at which node on the string the voltage is tapped off before being fed into the output amplifier. Therefore, depending on the headroom available, the input to the force amplifier can be unipolar positive or bipolar, either symmetrical or asymmetrical about DUTGND, but always within a voltage span of 22.5 V. The transfer function for DAC outputs is as follows: VOUT = 4.5 × VREF × (X2/216) − (3.5 × VREF × (OFFSET_DAC_CODE/216)) + DUTGND where: VREF is the reference voltage and is in the range of 2 V to 5 V. X2 is the calculated DAC code value and is in the range of 0 to 65,535 (see the Gain and Offset Registers section). OFFSET_DAC_ CODE is the code loaded to the offset DAC. It is multiplied by 3.5 in the transfer function. On power-up, the default code loaded to the offset DAC is 0xA492; with a 5 V reference, this gives a span of ±11.25 V. OFFSET DAC The AD5522 is capable of forcing a 22.5 V (4.5 × VREF) voltage span. Included on chip is one 16-bit offset DAC (one for all four channels) that allows for adjustment of the voltage range. The usable range is −16.25 V to +22.5 V. Zero scale loaded to the offset DAC gives a full-scale range of 0 V to 22.5 V, midscale gives ±11.25 V, and the most useful negative range is −16.25 V to +6.25 V. Full scale loaded to the offset DAC does not give a useful output voltage range, because the output amplifiers are limited by the available footroom. Table 13 shows the effect of the offset DAC on the other DACs in the device. Table 13. Relationship of Offset DAC to Other DACs (VREF = 5 V) Offset DAC Code 0 32,768 42,130 60,855 65,535 DAC Code 0 32,768 65,535 0 32,768 65,535 0 32,768 65,535 0 32,768 65,535 DAC Output Voltage (V) 0 +11.25 +22.50 −8.75 +2.50 +13.75 −11.25 0 +11.25 −16.25 −5.00 +6.25 Footroom limitations The offset DAC offsets all DAC functions. It also centers the current range so that zero current always flows at midscale code, regardless of the offset DAC setting. Rearranging the transfer function for the DAC output gives the following equation to determine which offset DAC code is required for a given reference and output voltage range. OFFSET_DAC_CODE = (216 × (VOUT − DUTGND))/ (3.5 × VREF) − ((4.5 × DAC_CODE)/3.5) When the output range is adjusted by changing the default value of the offset DAC, an extra offset is introduced due to the gain error of the offset DAC channel. The amount of offset is dependent on the magnitude of the reference and how much the offset DAC channel deviates from its default value. See the Specifications section for this offset. The worst-case offset occurs when the offset DAC channel is at positive or negative full scale. This value can be added to the offset present in the main DAC channel to give an indication of the overall offset for that channel. In most cases, the offset can be removed by programming the C register of the channel with an appropriate value. The extra offset caused by the offset DAC needs to be taken into account only when the offset DAC is changed from its default value. GAIN AND OFFSET REGISTERS Each DAC level has an independent gain (M) register and an independent offset (C) register, which allow trimming out of the gain and offset errors of the entire signal chain, including the DAC. All registers in the AD5522 are volatile, so they must be loaded on power-on during a calibration cycle. Data from the X1 register is operated on by a digital multiplier and adder controlled by the contents of the M and C registers. The calibrated DAC data is then stored in the X2 register. The digital input transfer function for each DAC can be represented as follows: X2 = [(M + 1)/2n × X1] + (C − 2n − 1) where: X2 is the data-word loaded to the resistor-string DAC. X1 is the 16-bit data-word written to the DAC input register. M is the code in the gain register (default code = 216 − 1). The M register is 15 bits (D15 to D1, the LSB is a don’t care). C is the code in the offset register (default code = 215). n is the DAC resolution (n = 16). Rev. E | Page 36 of 64 Data Sheet AD5522 The calibration engine is engaged only when data is written to the X1 register and for some PMU writes (see Table 18). The calibration engine is not engaged when data is written to the M or C register. This has the advantage of minimizing the initial setup time of the device. To calculate a result that includes new M or C data, a write to X1 is required. CACHED X2 REGISTERS Gain and Offset Registers for the Clamp DACs The clamp DAC levels contain independent gain and offset control registers that allow the user to digitally trim gain and offset. There are two sets of X1, M, and C registers: one set for the force voltage mode and one set for all five current ranges. Two X2 registers store the calculated DAC values, ready to load to the DAC register upon a PMU mode change. Each DAC has a number of cached X2 registers. These registers store the result of a gain and offset calibration in advance of a mode change. This enables the user to preload registers, allowing the calibration engine to calculate the appropriate X2 value and store it until a change in mode occurs. Because the data is ready and held in the appropriate register, mode changing is as time efficient as possible. If an update occurs to a DAC register set that is currently part of the operating PMU mode, the DAC output is updated immediately (depending on the LOAD condition). VREF Gain and Offset Registers for the FIN DAC REFERENCE VOLTAGE (VREF) The force amplifier input (FIN) DAC level contains independent gain and offset control registers that allow the user to digitally trim gain and offset. There are six sets of X1, M, and C registers: one set for the force voltage range and one set for each force current range (four internal current ranges and one external current range). Six X2 registers store the calculated DAC values, ready to load to the DAC register upon a PMU mode change. One buffered analog input, VREF, supplies all 21 DACs with the necessary reference voltage to generate the required dc levels. OFFSET DAC 16 16 VREF X1 REG M REG C REG ×6 SERIAL I/F 16 X2 REG 16-BIT FIN DAC FIN 06197-030 16 Figure 51. FIN DAC Registers Gain and Offset Registers for the Comparator DACs The comparator DAC levels contain independent gain and offset control registers that allow the user to digitally trim gain and offset. There are six sets of X1, M, and C registers: one set for the force voltage mode and one set for each force current range (four internal current ranges and one external current range). In this way, X2 can be preprogrammed, which allows for efficient switching into the required compare mode. Six X2 registers store the calculated DAC values, ready to load to the DAC register upon a PMU mode change. 16 16 16 X2 REG X1 REG M REG C REG ×6 X2 REG CPH 16-BIT CPL DAC CPL 16 16 SERIAL I/F 16 CLH X1 REG M REG C REG X2 REG 16-BIT 16 CLL DAC CLL ×2 SERIAL I/F Figure 53. Clamp Registers REFERENCE SELECTION The voltage applied to the VREF pin determines the output voltage range and span applied to the force amplifier, clamp, and comparator inputs. The AD5522 can be used with a reference input ranging from 2 V to 5 V; however, for most applications, a reference input of 5 V or 2.5 V is sufficient to meet all voltage range requirements. The DAC amplifier gain is 4.5, which gives a DAC output span of 22.5 V. The DACs have gain and offset registers that can be used to trim out system errors. In addition, the gain register can be used to reduce the DAC output range to the desired force voltage range. The FIN DAC retains 16-bit resolution even with a gain register setting of quarter scale (0x4000). Therefore, from a single 5 V reference, it is possible to obtain a voltage span as high as 22.5 V or as low as 5.625 V. When using the gain and offset registers, the selected output range should take into account the system gain and offset errors that need to be trimmed out. Therefore, the selected output range should be larger than the actual required range. When using low supply voltages, ensure that there is sufficient headroom and footroom for the required force voltage range. Also, the forced current range is the quoted full-scale range only with an applied reference of 5 V (ISENSE amplifier gain = 10) or 2.5 V (ISENSE amplifier gain = 5). 16 16 16 X2 REG 16 16 16-BIT CLH DAC 16 X1 REG M REG C REG ×2 06197-032 16 06197-031 VREF X1 REG M REG C REG ×6 16-BIT 16 CPH DAC 16 Figure 52. Comparator Registers Rev. E | Page 37 of 64 AD5522 Data Sheet Table 14. References Suggested For Use with AD5522 1 Part No. ADR435 ADR445 ADR431 ADR441 1 Voltage (V) 5 5 2.5 2.5 Initial Accuracy % ±0.04 ±0.04 ±0.04 ±0.04 Ref Out TC (ppm/°C) 1 1 1 1 Ref Output Current (mA) 30 10 30 10 Supply Voltage Range (V) +7 to +18 +5.5 to +18 +4.5 to +18 +3 to +18 Package MSOP, SOIC MSOP, SOIC MSOP, SOIC MSOP, SOIC Subset of the possible references suitable for use with the AD5522. Visit www.analog.com for more options. For other voltage and current ranges, the required reference level can be calculated as follows: 1. 2. 3. 4. 5. Identify the nominal range required. Identify the maximum offset span and the maximum gain required on the full output signal range. Calculate the new maximum output range, including the expected maximum gain and offset errors. Choose the new required VOUTMAX and VOUTMIN, keeping the VOUT limits centered on the nominal values. Note that AVDD and AVSS must provide sufficient headroom. Calculate the value of VREF as follows: VREF = (VOUTMAX − VOUTMIN)/4.5 Calibration involves determining the gain and offset of each channel in each mode and overwriting the default values in the M and C registers of the individual DACs. In some cases (for example, FI mode), the calibration constants, particularly those for gains, may be range dependent. If, given the following conditions: Nominal output range = 10 V (−2 V to +8 V) Offset error = ±100 mV Gain error = ±0.5% REFGND = AGND = 0 V Reducing Zero-Scale Error Zero-scale error can be reduced as follows: Then, with gain error = ±0.5%, the maximum positive gain error = +0.5%, and the output range including gain error = 10 V + 0.005(10 V) = 10.05 V. 1. 2. With offset error = ±100 mV, the maximum offset error span = 2(100 mV) = 0.2 V, and the output range including gain error and offset error = 10.05 V + 0.2 V = 10.25 V. To calculate VREF with actual output range = 10.25 V, that is, −2.125 V to +8.125 V (centered), If the solution yields an inconvenient reference level, the user can adopt one of the following approaches: • 3. Set the output to the lowest possible value. Measure the actual output voltage and compare it to the required value. This gives the zero-scale error. Calculate the number of LSBs equivalent to the zero-scale error and add/subtract this number to the default value of the C register. Reducing Gain Error Gain error can be reduced as follows: VREF = (8.125 V + 2.125 V)/4.5 = 2.28 V • It is important to bear in mind when choosing a reference value that values other than 5 V (MI gain = 10) and 2.5 V (MI gain = 5) result in current ranges other than those specified. See the Measure Current Gains section for more details. CALIBRATION Reference Selection Example • In this case, the optimum reference is a 2.5 V reference; the user can use the M and C registers and the offset DAC to achieve the required −2 V to +8 V range. Change the ISENSE amplifier gain to 5 to ensure a full-scale current range of the specified values (see the Current Range Selection section). This gain also allows optimization of power supplies and minimizes power consumption within the device. Use a resistor divider to divide down a convenient, higher reference level to the required level. Select a convenient reference level above VREF and modify the gain and offset registers to digitally downsize the reference. In this way, the user can use almost any convenient reference level. Use a combination of these two approaches. 1. 2. 3. 4. Rev. E | Page 38 of 64 Measure the zero-scale error. Set the output to the highest possible value. Measure the actual output voltage and compare it to the required value. This is the gain error. Calculate the number of LSBs equivalent to the gain error and subtract this number from the default value of the M register. Note that only positive gain error can be reduced. Data Sheet AD5522 Calibration Example The calibration procedure for the force and measure circuitry is as follows: Nominal offset coefficient = 32,768 Nominal gain coefficient = 65,535 1. Calibrate the force voltage (2 points). In FV mode, write zero scale to the FIN DAC. Connect SYS_FORCE to FOHx and SYS_SENSE to MEASVHx, and close the internal force/sense switch (SW7). For example, the gain error = 0.5%, and the offset error = 100 mV. Gain error (0.5%) calibration: 65,535 × 0.995 = 65,207 Using the system PMU, measure the error between the voltage at FOHx/MEASVHx and the desired value. Therefore, load Code 1111 1110 1011 0111 to the M register. Offset error (100 mV) calibration: Similarly, load full scale to the FIN DAC and measure the error between the voltage at FOHx/MEASVHx and the desired value. Calculate the M and C values. Load these values to the appropriate M and C registers of the FIN DAC. LSB size = 10.25/65,535 = 156 µV Offset coefficient for 100 mV offset = 100/0.156 = 641 LSBs Therefore, load Code 0111 1101 0111 1111 to the C register. 2. ADDITIONAL CALIBRATION The techniques described in the Calibration section are usually sufficient to reduce the zero-scale and gain errors. However, there are limitations whereby the errors may not be sufficiently reduced. For example, the offset (C) register can only be used to reduce the offset caused by negative zero-scale error. A positive offset cannot be reduced. Likewise, if the maximum voltage is below the ideal value, that is, a negative gain error, the gain (M) register cannot be used to increase the gain to compensate for the error. These limitations can be overcome by increasing the reference value. SYSTEM LEVEL CALIBRATION There are many ways to calibrate the device on power-on. Following is an example of how to calibrate the FIN DAC of the device without a DUT or DUT board connected. Calibrate the measure voltage (2 points). Connect SYS_FORCE to FOHx and SYS_SENSE to MEASVHx, and close the internal force/sense switch (SW7). Force voltage on FOHx via SYS_FORCE and measure the voltage at MEASOUTx. The difference is the error between the actual forced voltage and the voltage at MEASOUTx. 3. Calibrate the force current (2 points). In FI mode, write zero scale to the FIN DAC. Connect SYS_FORCE to an external ammeter and to the FOHx pin. Measure the error between the ammeter reading and the MEASOUTx reading. Repeat this step with full scale loaded to the FIN DAC. Calculate the M and C values. 4. Calibrate the measure current (2 points). In FI mode, write zero scale to the FIN DAC. Connect SYS_FORCE to an external ammeter and to the FOHx pin. Measure the error between the ammeter reading and the MEASOUTx reading. Repeat this step with full scale loaded to the FIN DAC. 5. Repeat this procedure for all four channels. Similarly, calibrate the comparator and clamp DACs, and load the appropriate gain and offset registers. Calibrating these DACs requires some successive approximation to find where the comparator trips or the clamps engage. Rev. E | Page 39 of 64 AD5522 Data Sheet CIRCUIT OPERATION The forced voltage can be calculated as follows: FORCE VOLTAGE (FV) MODE Forced Voltage at DUT = VOUT Most PMU measurements are performed in force voltage/measure current (FVMI) mode, for example, when the device is used as a device power supply, or in continuity or leakage testing. In force voltage (FV) mode, the voltage forced is mapped directly to the DUT. The measure voltage amplifier completes the loop, giving negative feedback to the forcing amplifier (see Figure 54). VOUT = 4.5 × VREF × (DAC_CODE/216) − (3.5 × VREF × (OFFSET_DAC_CODE/216)) + DUTGND where: VOUT is the voltage of the FIN DAC (see the DAC Levels section). EXTFOHx CFFx FORCE AMPLIFIER DAC FIN INTERNAL RANGE SELECT (±5µA, ±20µA, ±200µA, ±2mA) + FOHx RSENSE – 4kΩ VMID TO CENTER I RANGE 2kΩ + ×1 OR ×0.2 ×5 OR ×10 – RSENSE (UP TO ±80mA) EXTMEASILx + – 4kΩ MEASVHx AGND + – + ×1 – DUT DUTGND + – MEASURE VOLTAGE AMPLIFIER Figure 54. Forcing Voltage, Measuring Current Rev. E | Page 40 of 64 06197-033 MEASOUTx EXTMEASIHx + – Data Sheet AD5522 FORCE CURRENT (FI) MODE In force current (FI) mode, the voltage at the FIN DAC is converted to a current and is applied to the DUT. The feedback path is the measure current amplifier, feeding back the voltage measured across the sense resistor. MEASOUTx reflects the voltage measured across the DUT (see Figure 55). where: FI is the forced current. RSENSE is the selected sense resistor. MI_Amplifier_Gain is the gain of the measure current instrumentation amplifier. This gain can be set to 5 or 10 via the serial interface. For the suggested current ranges, the maximum voltage drop across the sense resistors is ±1 V. However, to allow for error correction, there is some overrange available in the current ranges. The maximum full-scale voltage range that can be loaded to the FIN DAC is ±11.5 V. The forced current can be calculated as follows: The ISENSE amplifier is biased by the offset DAC output voltage in such a way as to center the measure current output regardless of the voltage span used. In the ±200 μA range with the 5 kΩ sense resistor and an ISENSE gain of 10, the maximum current range possible is ±225 μA. Similarly, for the other current ranges, there is an overrange of 12.5% to allow for error correction. FI = 4.5 × VREF × ((DAC_CODE − 32,768)/216)/(RSENSE × MI_Amplifier_Gain) EXTFOHx CFFx FORCE AMPLIFIER DAC FIN INTERNAL RANGE SELECT (±5µA, ±20µA, ±200µA, ±2mA) + FOHx RSENSE – MEASURE CURRENT AMPLIFIER VMID TO CENTER I RANGE ×5 OR ×10 – RSENSE (UP TO ±80mA) EXTMEASILx + – 4kΩ MEASVHx AGND + – + ×1 – DUT DUTGND + – Figure 55. Forcing Current, Measuring Voltage Rev. E | Page 41 of 64 06197-034 ×1 OR ×0.2 EXTMEASIHx 2kΩ + MEASOUTx 4kΩ + – AD5522 Data Sheet SERIAL INTERFACE The AD5522 provides two high speed serial interfaces: an SPIcompatible interface operating at clock frequencies up to 50 MHz and an EIA-644-compliant LVDS interface. To minimize both the power consumption of the device and the on-chip digital noise, the serial interface powers up fully only when the device is being written to, that is, on the falling edge of SYNC. SPI INTERFACE The serial interface operates from a 2.3 V to 5.25 V DVCC supply range. The SPI interface is selected when the SPI/LVDS pin is held low. It is controlled by four pins, as described in Table 15. Table 15. Pins That Control the SPI Interface Pin SYNC SDI SCLK SDO Description Frame synchronization input Serial data input pin Clocks data in and out of the device Serial data output pin for data readback (weak SDO output driver, may require reduction in SCLK frequency to correctly read back, see Table 2) LVDS INTERFACE The LVDS interface uses the same input pins, with the same designations, as the SPI interface. In addition, four other pins are provided for the complementary signals needed for differential operation, as described in Table 16. Table 16. Pins That Control the LVDS Interface Pin SYNC SYNC SDI SDI SCLK SCLK SDO SDO Description Differential frame synchronization signal Differential frame synchronization signal (complement) Differential serial data input Differential serial data input (complement) Differential serial clock input Differential serial clock input (complement) Differential serial data output for data readback Differential serial data output for data readback (complement) SERIAL INTERFACE WRITE MODE The AD5522 allows writing of data via the serial interface to every register directly accessible to the serial interface, that is, all registers except the DAC registers. The serial word is 29 bits long. The serial interface works with both a continuous and a burst (gated) serial clock. Serial data applied to SDI is clocked into the AD5522 by clock pulses applied to SCLK. The first falling edge of SYNC starts the write cycle. At least 29 falling clock edges must be applied to SCLK to clock in 29 bits of data before SYNC is taken high again. The input register addressed is updated on the rising edge of SYNC. For another serial transfer to take place, SYNC must be taken low again. The shift register can accept longer words (for example, 32-bit words), framed by SYNC, but the data should always be in the 29th LSB positions. RESET FUNCTION Bringing the level-sensitive RESET line low resets the contents of all internal registers to their power-on reset state (see the Power-On Default section). This sequence takes approximately 600 µs. BUSY goes low for the duration, returning high when RESET is brought high again and the initialization is complete. While BUSY is low, all interfaces are disabled. When BUSY returns high, normal operation resumes, and the status of the RESET pin is ignored until it goes low again. The SDO output is high impedance during a power-on reset or a RESET. A poweron reset functions the same way as RESET. BUSY AND LOAD FUNCTIONS The BUSY pin is an open-drain output that indicates the status of the AD5522 interface. When writing to any register, BUSY goes low and stays low until the command completes. A write operation to a DAC X1 register and some PMU register bits (see Table 18) drives the BUSY signal low for longer than a write M, C, or system control register. For DACs, the value of the internal cached (X2) data is calculated and stored each time that the user writes new data to the corresponding X1 register. During the calculation and writing of X2, the BUSY output is driven low. While BUSY is low, the user can continue writing new data to the any register, but this write should not be completed with SYNC going high until BUSY returns high (see Figure 56 and Figure 57). X2 values are stored and held until a PMU word is written that calls the appropriate cached X2 register. Only then is a DAC output updated. The DAC outputs and PMU modes are updated by taking the LOAD input low. If LOAD goes low while BUSY is active, the LOAD event is stored and the DAC outputs or PMU modes are updated immediately after BUSY goes high. A user can also hold the LOAD input permanently low. In this case, the DAC outputs or PMU modes are updated immediately after BUSY goes high. The BUSY pin is bidirectional and has a 50 kΩ internal pull-up resistor. When multiple AD5522 devices are used in one system, the BUSY pins can be tied together. This is useful when it is required that no DAC or PMU in any device be updated until all others are ready to be updated. When each device finishes updating its X2 registers, it releases the BUSY pin. If another device has not finished updating its X2 registers, it holds BUSY low, thus delaying the effect of LOAD going low. Rev. E | Page 42 of 64 Data Sheet AD5522 BUSY also goes low during a power-on reset and when a falling edge is detected on the RESET pin. CALIBRATION ENGINE TIME ~650ns 650ns 650ns 350ns WRITE 1 FIRST STAGE SECOND STAGE THIRD STAGE FIRST STAGE SECOND STAGE THIRD STAGE FIRST STAGE SECOND STAGE THIRD STAGE WRITE 2 FIRST STAGE SECOND STAGE Table 17. BUSY Pulse Widths Action Loading Data to System Control Register, or Readback2 Loading X1 to 1 PMU DAC Channel Loading X1 to 2 PMU DAC Channels Loading X1 to 3 PMU DAC Channels Loading X1 to 4 PMU DAC Channels 1 2 BUSY Pulse Width1 0.27 µs maximum 1.65 µs maximum 2.3 µs maximum 2.95 µs maximum 3.6 µs maximum FOR EXAMPLE, WRITE TO 3 FIN DAC REGISTERS THIRD STAGE Figure 56. Multiple Writes to DAC X1 Registers Writing data to the system control register, some PMU control bits (see Table 18), the M register, and the C register do not involve the digital calibration engine, thus speeding up configuration of the device on power-on. However, care should be taken not to issue these commands while BUSY is low, as previously described. BUSY pulse width = ((number of channels + 1) × 650 ns) + 350 ns. Refer to Table 18 for details of PMU register effect on BUSY pulse width. Table 18. BUSY Pulse Widths for PMU Register Updates PMU Register Update (See Table 26) Bit 21 20, 19 17, 16, 15 14, 13 12 11 10 9 8 7 6 Bit Name CH EN FORCE1, FORCE0 (depends on mode change) Transition From Transition To High-Z FOHx current (11) Force current (01) High-Z FOHx current (11) Force voltage (00) High-Z FOHx current (11) High-Z FOHx voltage (10) Force current (01) High-Z FOHx current (11) Force current (01) High-Z FOHx voltage (10) Force current (01) Force voltage (00) High-Z FOHx voltage (10) Force voltage (00) High-Z FOHx voltage (10) Force current (01) High-Z FOHx voltage (10) High-Z FOHx current (11) Force voltage (00) High-Z FOHx voltage (10) Force voltage (00) High-Z FOHx current (11) Force voltage (00) Force current (01) C2 to C0; current range selection (any range change) MEASx (measure mode selection) FIN SFO SS0 CL CPOLH Compare V/I Clear Rev. E | Page 43 of 64 Maximum BUSY Low Time per Channel Update One Channel Two Three Channels Channels 270 ns 1.65 µs 1.65 µs 2.3 µs 2.3 us 1.65 µs 1.65 µs 2.3 µs 2.3 µs 1.65 µs 1.65 µs 2.3 µs 2.3 µs 1.65 µs 1.65 µs 1.65 µs 2.3 µs 2.3 µs 2.3 µs 1.65 µs 2.3 µs 270 ns 2.95 µs 2.95 us 270 ns 2.95 µs 2.95 µs 270 ns 2.95 µs 2.95 µs 270 ns 2.95 µs 2.95 µs 2.95 µs 270 ns 270 ns 270 ns 270 ns 270 ns 270 ns 2.95 µs 270 ns Four Channels 3.6 µs 3.6 µs 3.6 µs 3.6 µs 3.6 µs 3.6 µs 3.6 µs 3.6 µs 3.6 µs 3.6 µs 06197-035 Because there is only one calibration engine shared among four channels, the task of calculating X2 values must be done sequentially, so that the length of the BUSY pulse varies according to the number of channels being updated. Following any register update, including multiple channel updates, subsequent writes should either be timed or should wait until BUSY returns high (see Figure 56). If subsequent writes are presented before the calibration engine completes the first stage of the last Channel X2 calculation, data may be lost. AD5522 Data Sheet REGISTER UPDATE RATES Table 19. Mode Bits The value of the X2 register is calculated each time the user writes new data to the corresponding X1 register and for some PMU register updates. The calculation is performed in a three-stage process. The first two stages take approximately 650 ns each, and the third stage takes approximately 350 ns. When the write to the X1 register is complete, the calculation process begins. If the write operation involves the update of a single DAC channel, the user is free to write to another X1 register, provided that the write operation does not finish (SYNC returns high) until after the first-stage calculation is complete, that is, 650 ns after the completion of the first write operation. B23 MODE1 0 B22 MODE0 0 0 1 1 1 0 1 CALIBRATION ENGINE TIME Action Write to the system control register or the PMU register Write to the DAC gain (M) register Write to the DAC offset (C) register Write to the DAC input data (X1) register Readback Control, RD/WR Setting the RD/WR bit (Bit 28) high initiates a readback sequence of the PMU, alarm status, comparator status, system control, or DAC register, as determined by the address bits. 650ns 650ns 350ns WRITE 1 FIRST STAGE SECOND STAGE THIRD STAGE WRITE 2 FIRST STAGE SECOND STAGE THIRD STAGE WRITE 3 FIRST STAGE SECOND STAGE THIRD STAGE 06197-036 PMU Address Bits: PMU3, PMU2, PMU1, PMU0 ~650ns Figure 57. Multiple Single-Channel Writes Engaging the Calibration Engine REGISTER SELECTION The serial word assignment consists of 29 bits. Bit 28 to Bit 22 are common to all registers, whether writing to or reading from the device. The PMU3 to PMU0 data bits (Bit 27 to Bit 24) address each PMU channel (or associated DAC register). When the PMU3 to PMU0 bits are all 0s, the system control register is addressed. The mode bits, MODE0 and MODE1, address the different sets of DAC registers and the PMU register. The PMU3 to PMU0 data bits (Bit 27 to Bit 24) address each PMU channel on chip. These bits allow individual control of each PMU channel or any combination of channels, in addition to multichannel programming. PMU bits also allow access to write registers such as the system control register and the DAC registers, in addition to reading from all the registers (see Table 20). NOP (No Operation) If an NOP (no operation) command is loaded, no change is made to the DAC or PMU registers. This code is useful when performing a readback of a register within the device (via the SDO pin) where a change of DAC code or PMU function may not be required. Reserved Commands Any bit combination that is not described in the register address tables for the PMU, DAC, and system control registers indicates a reserved command. These commands are unassigned and are reserved for factory use. To ensure correct operation of the device, do not use reserved commands. Rev. E | Page 44 of 64 Data Sheet AD5522 All codes not explicitly referenced in this table are reserved and should not be used (see Table 29). Table 20. Read and Write Functions of the AD5522 B28 RD/WR B27 PMU3 B26 PMU2 B25 PMU1 B24 PMU0 B23 MODE1 B22 MODE0 B21 to B0 Data bits Write Functions 0 0 0 0 0 0 0 Data bits 0 0 0 0 0 0 1 Data bits 0 0 0 0 0 1 0 Data bits 0 0 0 0 0 1 1 All 1s 0 0 0 0 0 1 1 Data bits other than all 1s Write Addressed DAC or PMU Register Address and data bits 0 0 0 0 1 Select DAC or PMU register 0 0 0 1 0 (see Table 19) 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 Read Functions 1 0 0 0 0 0 0 All 0s 1 0 0 0 0 0 1 All 0s 1 0 0 0 0 1 0 X (don’t care) 1 0 0 0 0 1 1 All 0s Read Addressed DAC or PMU Register (Only One PMU or DAC Register Can Be Read at One Time) All 0s if reading PMU 1 0 0 0 1 Select PMU or registers; DAC address DAC register 1 0 0 1 0 plus all 0s if reading a (see Table 19) 1 0 1 0 0 DAC register DAC address 1 1 0 0 0 (see Table 29) Rev. E | Page 45 of 64 CH3 Selected Channel CH2 CH1 CH0 Write to system control register (see Table 23) Reserved Reserved NOP (no operation) Reserved CH0 CH1 CH1 CH2 CH2 CH2 CH2 CH3 CH3 CH3 CH3 CH3 CH3 CH3 CH3 CH0 CH0 CH1 CH1 CH0 CH0 CH1 CH1 CH2 CH2 CH2 CH2 CH0 CH0 CH1 CH1 CH0 Read from system control register Read from comparator status register Reserved Read from alarm status register CH0 CH1 CH2 CH3 AD5522 Data Sheet WRITE SYSTEM CONTROL REGISTER functions in the device. The system control register operates on a per-device basis. The system control register is accessed when the PMU channel address bits (PMU3 to PMU0) and the mode bits (MODE1 and MODE0) are all 0s. This register allows quick setup of various Table 21. System Control Register Bits—Bit B28 to Bit B15 B28 RD/WR B27 PMU3 B26 PMU2 B25 PMU1 B24 PMU0 B23 MODE1 B22 MODE0 B21 CL3 B20 CL2 B19 CL1 B18 CL0 B17 CPOLH3 B16 CPOLH2 B15 CPOLH1 Table 22. System Control Register Bits—Bit B14 to Bit B0 B14 CPOLH0 1 B13 CPBIASEN B12 DUTGND/CH B11 Guard ALM B10 Clamp ALM B9 INT10K B8 Guard EN B7 GAIN1 B6 GAIN0 B5 TMP enable B4 TMP1 B3 TMP0 B2 Latched B11 0 B01 0 Bit B1 and Bit B0 are unused data bits. Table 23. System Control Register Functions Bit 28 (MSB) Bit Name RD/WR Description When low, a write function takes place to the selected register; setting the RD/WR bit high initiates a readback sequence of the PMU, alarm status, comparator status, system control, or DAC register, as determined by the address bits. Set Bit PMU3 to Bit PMU0 to 0 to address the system control register. 27 PMU3 26 PMU2 25 PMU1 24 PMU0 23 MODE1 Set the MODE1 and MODE0 bits to 0 to address the system control register. 22 MODE0 System Control Register-Specific Bits 21 CL3 Current or voltage clamp enable. Bit CL3 to Bit CL0 enable and disable the current or voltage clamp function per channel (0 = disable; 1 = enable). The clamp enable function is also available in the PMU register on a per20 CL2 channel basis. This dual functionality allows flexible enabling or disabling of this function. When reading back 19 CL1 information about the status of the clamp enable function, the data that was most recently written to the clamp 18 CL0 register is available in the readback word from either the PMU register or the system control register. 17 16 15 14 CPOLH3 CPOLH2 CPOLH1 CPOLH0 13 CPBIASEN 12 DUTGND/CH 11 10 GUARD ALM CLAMP ALM 9 INT10K 8 Guard EN Comparator output enable. By default, the comparator outputs are high-Z on power-on. A 1 in each bit position enables the comparator output for the selected channel. Bit 13 (CPBIASEN) must be enabled to power on the comparator functions. The comparator enable function is also available in the PMU register on a per-channel basis. This dual functionality allows flexible enabling or disabling of this function. When reading back information about the status of the comparator enable function, the data that was most recently written to the comparator status register is available in the readback word from either the PMU register or the system control register. Comparator enable. By default, the comparators are powered down when the device is powered on. To enable the comparator function for all channels, write a 1 to this bit. A 0 disables the comparators and shuts them down. The comparator output enable bits (CPOLHx, Bit 17 to Bit 14) allow the user to turn on each comparator output individually, enabling busing of comparator outputs. DUTGND per channel enable. The GUARDINx/DUTGNDx pins are shared pins that can be configured to enable a DUTGND per PMU channel or a guard input per PMU channel. Setting this bit to 1 enables DUTGND per channel. In this mode, the pin functions as a DUTGND pin on a per-channel basis. The guard inputs are disconnected from this pin and instead are connected directly to the MEASVHx line by an internal connection. The default power-on condition is GUARDINx. Clamp and guard alarm functions share one open-drain alarm pin (CGALM). By default, the CGALM pin is disabled. The guard ALM and clamp ALM bits allow the user to choose whether clamp alarm information, guard alarm information, or both sets of alarm information are flagged by the CGALM pin. Set high to enable either alarm function. Internal sense short. Setting this bit high allows the user to connect an internal sense short resistor of 10 kΩ (4 kΩ + 2 kΩ switch + 4 kΩ) between the FOHx and the MEASVHx lines (SW7 is closed). Setting this bit high also closes SW15, allowing the user to connect another 10 kΩ resistor between DUTGNDx and AGND. Guard enable. The guard amplifier is disabled on power-on; to enable the guard amplifier, set this bit to 1. If the guard function is not in use, disabling it saves power (typically 400 μA per channel). Rev. E | Page 46 of 64 Data Sheet Bit 7 6 Bit Name GAIN1 GAIN0 5 TMP ENABLE 4 3 TMP1 TMP0 2 Latched 1 0 (LSB) 0 0 AD5522 Description MEASOUTx output range. The MEASOUTx range defaults to the force voltage span for voltage and current measurements, which includes some overrange to allow for offset correction. The nominal output voltage range is ±11.25 V with the default offset DAC setting, but changes for other offset DAC settings when GAIN1 = 0. Therefore, the MEASOUTx range can be an asymmetrical bipolar voltage range. GAIN1 = 1 enables a unipolar output voltage range, which allows the use of asymmetrical supplies or a smaller input range ADC. See Table 10 and Table 11 for more details. Measure Output Voltage Range for VREF = 5 V, Offset DAC = 0xA492 MEASOUT Current GAIN1 = 0, MEASOUT Gain = 1 GAIN1 = 1, MEASOUT Gain = 0.2 Function Gain MV 5 or 10 ±VDUT (up to ±11.25 V) 0 V to 4.5 V MI (GAIN0 = 0) 10 ±IDUT × RRSENSE × 10 + VMID (up to ±11.25 V) 0 V to 4.5 V MI (GAIN0 = 1) 5 ±IDUT × RRSENSE × 5 + VMID (up to ±5.625 V) 0 V to 2.25 V Thermal shutdown feature. To disable the thermal shutdown feature, set the TMP ENABLE bit to 0 (thermal shutdown is enabled by default). The TMP1 and TMP0 bits allow the user to program the temperature that triggers thermal shutdown. TMP ENABLE TMP1 TMP0 Action 0 X X Thermal shutdown disabled. 1 X X Thermal shutdown enabled. 1 0 0 Shutdown at junction temperature of 130°C (power-on default). 1 0 1 Shutdown at junction temperature of 120°C. 1 1 0 Shutdown at junction temperature of 110°C. 1 1 1 Shutdown at junction temperature of 100°C. Configure the open-drain pin (CGALM) as a latched or unlatched output pin. When high, this bit configures the CGALM alarm output as a latched output, allowing it to drive a controller I/O without needing to poll the line constantly. The power-on default for this pin is unlatched. Unused bits. Set to 0. Rev. E | Page 47 of 64 AD5522 Data Sheet WRITE PMU REGISTER To address PMU functions, set the MODE1 and MODE0 bits to 0. This setting selects the PMU register (see Table 19 and Table 20). The AD5522 has very flexible addressing, which allows writing of data to a single PMU channel, any combination of PMU channels, or all PMU channels. This functionality enables multipin broadcasting to similar pins on a DUT. Bit 27 to Bit 24 select the PMU or group of PMUs that is addressed. Table 24. PMU Register Bits—Bit B28 to Bit B15 B28 RD/WR 1 B27 PMU3 B26 PMU2 B25 PMU1 B24 PMU0 B23 MODE1 B22 MODE0 B21 CH EN B20 FORCE1 B19 FORCE0 B8 CPOLH B7 Compare V/I B6 Clear B51 0 B181 0 B17 C2 B16 C1 B15 C0 Bit B18 is reserved. Table 25. PMU Register Bits—Bit B14 to Bit B0 B14 MEAS1 1 B13 MEAS0 B12 FIN B11 SF0 B10 SS0 B9 CL B41 0 B31 0 B21 0 B11 0 B01 0 Bit B5 to Bit B0 are unused data bits. Table 26. PMU Register Functions Bit 28 (MSB) Bit Name RD/WR Description When low, a write to the selected register takes place; setting the RD/WR bit high initiates a readback sequence of the PMU, alarm status, comparator status, system control, or DAC register, as determined by the address bits. Bit PMU3 to Bit PMU0 address each PMU channel in the device. These bits allow control of an individual PMU channel or any combination of channels, in addition to multichannel programming (see Table 20). 27 PMU3 26 PMU2 25 PMU1 24 PMU0 23 MODE1 Set the MODE1 and MODE0 bits to 0 to access the PMU register selected by the PMU3 to PMU0 bits (Bit 27 to Bit 24). 22 MODE0 PMU Register-Specific Bits 21 CH EN Channel enable. Set high to enable the selected channel or group of channels; set low to disable the selected channel or channels. When disabled, SW2 is closed and SW5 is open (outputs are high-Z). The measure mode is determined by the MEAS1 and MEAS0 bits at all times and is not affected by the CH EN bit. The guard amplifier and the comparators are not affected by this bit. 20 FORCE1 The FORCE1 and FORCE0 bits set the force function for each PMU channel (in association with the PMUx bits). All combinations of forcing and measuring (using the MEAS1 and MEAS0 bits) are available. The high-Z (voltage 19 FORCE0 and current) modes allow the user to optimize glitch response during mode changes. While in high-Z voltage or current mode, with the PMU high-Z, new X1 codes loaded to the FIN DAC register and to the clamp DAC register are calibrated, stored in the X2 register, and loaded directly to the DAC outputs. FORCE1 FORCE0 Action 0 0 FV and current clamp (if clamp is enabled). 0 1 FI and voltage clamp (if clamp is enabled). 1 0 High-Z FOHx voltage (preload FIN DAC and clamp DAC). 1 1 High-Z FOHx current (preload FIN DAC and clamp DAC). 18 Reserved 0 17 C2 Bit C2 to Bit C0 specify the required current range. High-Z FV/FI commands ignore the current range address bits (C2, C1, and C0); therefore, these bit combinations cannot be used to enable or disable the force function 16 C1 for a PMU channel. 15 C0 C2 C1 C0 Selected Current Range 0 0 0 ±5 µA current range. 0 0 1 ±20 µA current range. 0 1 0 ±200 µA current range. 0 1 1 ±2 mA current range (default). 1 0 0 ±external current range. 1 0 1 Disable the always on mode for the external current range buffer1. 1 1 0 Enable the always on mode for the external current range buffer2. 1 1 1 Reserved. Rev. E | Page 48 of 64 Data Sheet Bit 14 13 Bit Name MEAS1 MEAS0 12 FIN 11 10 SF0 SS0 9 CL 8 CPOLH 7 Compare V/I Clear 6 5 4 3 2 1 0 (LSB) Unused AD5522 Description The MEAS1 and MEAS0 bits specify the required measure mode, allowing the MEASOUTx line to be disabled, connected to the temperature sensor, or enabled for measurement of current or voltage. MEAS1 MEAS0 Action 0 0 MEASOUTx is connected to ISENSE 0 1 MEASOUTx is connected to VSENSE 1 0 MEASOUTx is connected to the temperature sensor 1 1 MEASOUTx is high-Z (SW12 open) This bit sets the status of the force input (FIN) amplifier. 0 = input of the force amplifier switched to GND. 1 = input of the force amplifier connected to the FIN DAC output. The SF0 and SS0 bits specify the switching of system force and sense lines to the force and sense paths at the DUT. The channel to which the system force and system sense lines are connected is set by the PMU3 to PMU0 bits. For correct operation, only one PMU channel should be connected to the SYS_FORCE and SYS_SENSE paths at any one time. SF0 SS0 Action 0 0 SYS_FORCE and SYS_SENSE are high-Z for the selected channel 0 1 SYS_FORCE is high-Z and SYS_SENSE is connected to MEASVHx for the selected channels 1 0 SYS_FORCE is connected to FOHx and SYS_SENSE is high-Z for the selected channel 1 1 SYS_FORCE is connected to FOHx and SYS_SENSE is connected to MEASVHx for the selected channel Per-PMU current or voltage clamp enable bit. A logic high enables the clamp function for the selected PMU. The clamp enable function is also available in the system control register. This dual functionality allows flexible enabling or disabling of this function. When reading back information about the status of the clamp enable function on a per-channel basis, the data that was most recently written to the clamp register is available in the readback word from either the PMU register or the system control register. Comparator output enable bit. By default, the comparator outputs are high-Z on power-on. A logic high enables the comparator output for the selected PMU. The comparator function CPBIASEN (Bit 13 in the system control register), must be enabled. The comparator output enable function is also available in the system control register. This dual functionality allows flexible enabling or disabling of this function. When reading back information about the status of the comparator enable function, the data that was most recently written to the comparator status register is available in the readback word from either the PMU register or the system control register. A logic high selects the compare voltage function; a logic low selects the compare current function. To clear or reset a latched alarm bit and pin (temperature, guard, or clamp), write a 1 to this bit. This bit applies to latched alarm conditions (clamp and guard) on all four PMU channels. Unused bits. Set to 0. Writing 101 in Bit 17 to Bit 15 disables the always on mode for the external current range buffer. Use with FV mode (FORCE1 = FORCE0 = 0) only. To complete the disabling of the always on mode, the PMU channel is placed into high-Z mode and the external current range buffer is returned to its default operation (off). 2 Writing 110 in Bit 17 to Bit 15 places the external current range buffer into always on mode. In this mode, the buffer is always active with no regard to the selected current range. The always on mode is intended for use where an external high current stage is being used for a current drive in excess of ±80 mA; having the internal stage always on should help to eliminate timing concerns when transitioning between this current range and other ranges. When first enabling the always on mode, use it in conjunction with FV mode (FORCE1 = FORCE0 = 0); the device now enables the external current range buffer. The 110 code also places the device into high-Z mode (necessary to complete the enabling function). To return to an FV or FI operating mode, select the appropriate mode and current range. The external range sense resistor is connected to an MI circuit only when the external current range address is selected (C2 to C0 are set to 100). The default operation at power-on is disabled (or off). 1 Rev. E | Page 49 of 64 AD5522 Data Sheet WRITE DAC REGISTER chip. Bit D15 to Bit D0 are the DAC data bits used when writing to these registers. The PMU address bits allow addressing of a particular DAC for any combination of PMU channels. The DAC input, gain, and offset registers are addressed through a combination of PMU bits (Bit 27 to Bit 24) and mode bits (Bit 23 and Bit 22). Bit A5 to Bit A0 address each DAC level on Table 27. DAC Register Bits B28 RD/WR B27 PMU3 B26 PMU2 B25 PMU1 B24 PMU0 B23 MODE1 B22 MODE0 B21 A5 B20 A4 B19 A3 B18 A2 B17 A1 B16 A0 B15 to B0 Data Bits[D15 (MSB):D0 (LSB)] Table 28. DAC Register Functions Bit 28 (MSB) Bit Name RD/WR 27 26 25 24 23 22 PMU3 PMU2 PMU1 PMU0 MODE1 MODE0 Description When this bit is low, a write function takes place to the selected register; setting the RD/WR bit high initiates a readback sequence of the PMU, alarm status, comparator status, system control, or DAC register, as determined by the address bits. Bit PMU3 to Bit PMU0 address each PMU and DAC channel in the device. These bits allow control of each individual DAC channel or any combination of channels, in addition to multichannel programming. The MODE1 and MODE0 bits allow addressing of the DAC gain (M), offset (C), or input (X1) register. MODE1 MODE0 Action 0 0 Write to the system control register or the PMU register 0 1 Write to the DAC gain (M) register 1 0 Write to the DAC offset (C) register 1 1 Write to the DAC input data (X1) register DAC Register-Specific Bits 21 A5 DAC address bits. The A5 to A3 bits select the register set that is addressed. See the DAC Addressing section. 20 A4 19 A3 18 A2 DAC address bits. The A2 to A0 bits select the DAC that is addressed. See the DAC Addressing section. 17 A1 16 A0 15 to 0 D15 (MSB) to 16 DAC data bits for X1 and C registers. M register is 15 bits wide, D15 to D1. D0 (LSB) Rev. E | Page 50 of 64 Data Sheet AD5522 DAC Addressing For the FIN and comparator (CPH and CPL) DACs, there is a set of X1, M, and C registers for each current range, and one set for the voltage range; for the clamp DACs (CLL and CLH), there are only two sets of X1, M, and C registers. When calibrating the device, the M and C registers allow volatile storage of gain and offset coefficients. Calculation of the corresponding DAC X2 register occurs only when the X1 data is loaded (no internal calculation occurs on M or C updates). There is one offset DAC for all four channels in the device that is addressed using the PMUx bits. The offset DAC has only an input register associated with it; no M or C registers are associated with this DAC. When writing to the offset DAC, set the MODE1 and MODE0 bits high to address the DAC input register (X1). The same address table is also used for readback of a particular DAC address. Note that CLL is clamp level low and CLH is clamp level high. • • When forcing a voltage, the current clamps are engaged; therefore, both the CLL current ranges register set and the CLH current ranges register set are loaded to the clamp DACs. When forcing a current, the voltage clamps are engaged; therefore, both the CLL voltage range register set and the CLH voltage range register set are loaded to the clamp DACs. All codes not explicitly referenced Table 29 are reserved and should not be used. Table 29. DAC Register Addressing A5 0 0 A4 0 0 A3 0 1 A2 0 0 A1 0 0 A0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 1 0 0 0 1 1 1 0 1 1 0 0 0 0 0 MODE1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 MODE0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 Rev. E | Page 51 of 64 Register Set N/A ±5 µA current range ±20 µA current range ±200 µA current range ±2 mA current range ±external current range Voltage range Current ranges Voltage range Current ranges Voltage range ±5 µA current range Addressed Register Offset DAC X FIN M FIN C FIN X1 FIN M FIN C FIN X1 FIN M FIN C FIN X1 FIN M FIN C FIN X1 FIN M FIN C FIN X1 FIN M FIN C FIN X1 CLL M CLL C CLL X1 1 CLL M CLL C CLL X1 CLH M CLH C CLH X1 2 CLH M CLH C CLH X1 CPL M CPL C CPL X1 AD5522 Data Sheet A5 1 A4 0 A3 0 A2 0 A1 0 A0 1 1 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 1 0 1 1 2 MODE1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 MODE0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 CLL should be within the range of 0x0000 to 0x7FFF. CLH should be within the range of 0x8000 to 0xFFFF. Rev. E | Page 52 of 64 Register Set ±20 µA current range ±200 µA current range ±2 mA current range ±external current range Voltage range ±5 µA current range ±20 µA current range ±200 µA current range ±2 mA current range ±external current range Voltage range Addressed Register CPL M CPL C CPL X1 CPL M CPL C CPL X1 CPL M CPL C CPL X1 CPL M CPL C CPL X1 CPL M CPL C CPL X1 CPH M CPH C CPH X1 CPH M CPH C CPH X1 CPH M CPH C CPH X1 CPH M CPH C CPH X1 CPH M CPH C CPH X1 CPH M CPH C CPH X1 Data Sheet AD5522 READ REGISTERS Readback of all the registers in the device is possible via the SPI and the LVDS interfaces. To read data from a register, it is first necessary to write a readback command to tell the device which register is required for readback. See Table 30 to address the appropriate channel. When the required channel is addressed, the device loads the 24-bit readback data into the MSB positions of the 29-bit serial shift register (the five LSBs are filled with 0s). SCLK rising edges clock this readback data out on SDO (framed by the SYNC signal). A minimum of 24 clock rising edges is required to shift the readback data out of the shift register. If writing a 24-bit word to shift data out of the device, the user must ensure that the 24-bit write is effectively an NOP (no operation) command. The last five bits in the shift register are always 00000: these five bits become the MSBs of the shift register when the 24-bit write is loaded. To ensure that the device receives an NOP command as described in Table 20, the recommended flush command is 0xFFFFFF; thus, no change is made to any register in the device. Readback data can also be shifted out by writing another 29-bit write or read command. If writing a 29-bit command, the readback data is MSB data available on SDO, followed by 00000. Table 30. Read Functions of the AD5522 B28 RD/WR B27 PMU3 B26 PMU2 B25 PMU1 B24 PMU0 B23 MODE1 B22 MODE0 B21 to B0 Data bits Read Functions 1 0 0 0 0 0 0 All 0s 1 0 0 0 0 0 1 All 0s 1 0 0 0 0 1 0 X (don’t care) 1 0 0 0 0 1 1 All 0s Read Addressed PMU Register (Only One PMU Register Can Be Read at One Time) 1 0 0 0 1 0 0 All 0s 1 0 0 1 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 Read Addressed DAC M Register (Only One DAC Register Can Be Read at One Time) 1 0 0 0 1 0 1 DAC address (see Table 29) 1 0 0 1 0 0 1 1 0 1 0 0 0 1 1 1 0 0 0 0 1 Read Addressed DAC C Register (Only One DAC Register Can Be Read at One Time) 1 0 0 0 1 1 0 DAC address (see Table 29) 1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 1 0 0 0 1 0 Read Addressed DAC X1 Register (Only One DAC Register Can Be Read at One Time) 1 0 0 0 1 1 1 DAC address (see Table 29) 1 0 0 1 0 1 1 1 0 1 0 0 1 1 1 1 0 0 0 1 1 Rev. E | Page 53 of 64 CH3 Selected Channel CH2 CH1 CH0 Read from system control register Read from comparator status register Reserved Read from alarm status register CH0 CH1 CH2 CH3 CH0 CH1 CH2 CH3 CH0 CH1 CH2 CH3 CH0 CH1 CH2 CH3 AD5522 Data Sheet READBACK OF SYSTEM CONTROL REGISTER The system control register readback function is a 24-bit word. Mode and system control register data bits are shown in Table 31. Table 31. System Control Register Readback Bit Bit Name Description 23 (MSB) MODE1 Set the MODE1 and MODE0 bits to 0 to address the system control register. 22 MODE0 System Control Register-Specific Readback Bits 21 CL3 Read back the status of the individual current clamp enable bits. 0 = clamp is disabled. 20 CL2 1 = clamp is enabled. 19 CL1 When reading back information about the status of the clamp enable function, the data that was most 18 CL0 recently written to the current clamp register from either the system control register or the PMU register 17 16 15 14 CPOLH3 CPOLH2 CPOLH1 CPOLH0 13 CPBIASEN 12 DUTGND/CH 11 10 GUARD ALM CLAMP ALM 9 INT10K 8 7 6 5 4 3 Guard EN GAIN1 GAIN0 TMP ENABLE TMP1 TMP0 2 Latched 1 0 (LSB) Unused readback bits is available in the readback word. Read back information about the status of the comparator output enable bits. 1 = PMU comparator output is enabled. 0 = PMU comparator output is disabled. When reading back information about the status of the comparator output enable function, the data that was most recently written to the comparator status register from either the system control register or the PMU register is available in the readback word. This readback bit indicates the status of the comparator enable function. 1 = comparator function is enabled. 0 = comparator function is disabled. DUTGND per channel enable. 1 = DUTGND per channel is enabled. 0 = individual guard inputs are available per channel. These bits provide information about which of these alarm bits trigger the CGALM pin. 1 = guard/clamp alarm is enabled. 0 = guard/clamp alarm is disabled. If this bit is high, the internal 10 kΩ resistor (SW7) is connected between FOHx and MEASVHx, and between DUTGND and AGND. If this bit is low, SW7 is open. Read back the status of the guard amplifiers. If this bit is high, the amplifiers are enabled. Status of the selected MEASOUTx output range. See Table 10 and Table 11. Read back the status of the thermal shutdown function. Bits[5:3] Action 0XX Thermal shutdown disabled. 100 Thermal shutdown enabled at junction temperature of 130°C (power-on default). 101 Thermal shutdown enabled at junction temperature of 120°C. 110 Thermal shutdown enabled at junction temperature of 110°C. 111 Thermal shutdown enabled at junction temperature of 100°C. 1XX Thermal shutdown enabled. This bit indicates the status of the open-drain alarm outputs, TMPALM and CGALM. 1 = open-drain alarm outputs are latched. 0 = open-drain alarm outputs are unlatched. Loads with 0s. Rev. E | Page 54 of 64 Data Sheet AD5522 READBACK OF PMU REGISTER The PMU register readback function is a 24-bit word that includes the mode and PMU data bits. Only one PMU register can be read back at any one time. Table 32. PMU Register Readback Bit Bit Name 23 (MSB) MODE1 22 MODE0 PMU Register-Specific Bits 21 CH EN 20 FORCE1 19 FORCE0 18 17 16 15 14 13 Reserved C2 C1 C0 MEAS1 MEAS0 12 FIN 11 10 9 SF0 SS0 CL 8 CPOLH 7 Compare V/I 6 5 LTMPALM TMPALM 4 to 0 (LSB) Unused readback bits Description Set the MODE1 and MODE0 bits to 0 to access the selected PMU register. Channel enable. If this bit is high, the selected channel is enabled; if this bit is low, the channel is disabled. These bits indicate which force mode the selected channel is in. 00 = FV and current clamp (if clamp is enabled). 01 = FI and voltage clamp (if clamp is enabled). 10 = high-Z FOHx voltage. 11 = high-Z FOHx current. 0. These three bits indicate which forced or measured current range is set for the selected channel (see Table 26). These bits indicate which measure mode is selected: voltage, current, temperature sensor, or high-Z. 00 = MEASOUTx is connected to ISENSE. 01 = MEASOUTx is connected to VSENSE. 10 = MEASOUTx is connected to the temperature sensor. 11 = MEASOUTx is high-Z (SW12 open). This bit shows the status of the force input (FIN) amplifier. 0 = input of the force amplifier switched to GND. 1 = input of the force amplifier connected to the FIN DAC output. The system force and sense lines can be connected to any of the four PMU channels. These bits indicate whether the system force and sense lines are switched in (see Table 26). Read back the status of the individual current clamp enable bits. 1 = clamp is enabled on this channel. 0 = clamp is disabled on this channel. When reading back information about the status of the current clamp enable function, the data that was most recently written to the current clamp register from either the system control register or the PMU register is available in the readback word. Read back the status of the comparator output enable bit. 1 = PMU comparator output is enabled. 0 = PMU comparator output is disabled. When reading back information about the status of the comparator output enable function, the data that was most recently written to the comparator register from either the system control register or the PMU register is available in the readback word. 1 = compare voltage function is enabled on the selected channel. 0 = compare current function is enabled on the selected channel. TMPALM corresponds to the open-drain TMPALM output pin that flags a temperature event exceeding the default or user programmed level. The temperature alarm is a per-device alarm; the latched (LTMPALM) and unlatched (TMPALM) bits indicate whether a temperature event occurred and whether the alarm still exists (that is, whether the junction temperature still exceeds the programmed alarm level). To reset an alarm event, the user must write a 1 to the clear bit (Bit 6) in the PMU register. Loads with 0s. Rev. E | Page 55 of 64 AD5522 Data Sheet READBACK OF COMPARATOR STATUS REGISTER READBACK OF ALARM STATUS REGISTER The comparator status register is a read-only register that provides access to the output status of each comparator pin on the chip. Table 33 shows the format of the comparator register readback word. The alarm status register is a read-only register that provides information about temperature, clamp, and guard alarm events (see Table 34). Temperature alarm status is also available in any of the four PMU readback registers. Table 33. Comparator Status Register (Read-Only) Bit Bit Name Description 23 (MSB) MODE1 0 22 MODE0 1 Comparator Status Register-Specific Bits 21 CPOL0 Comparator output conditions per channel corresponding to the comparator output pins. 1 = PMU comparator output is high. 20 CPOH0 0 = PMU comparator output is low. 19 CPOL1 18 17 16 15 14 13 to 0 (LSB) CPOH1 CPOL2 CPOH2 CPOL3 CPOH3 Unused readback bits Loads with zeros. Table 34. Alarm Status Register Readback Bit Bit Name Description 23 MODE1 1 (MSB) 22 MODE0 1 Alarm Status Register-Specific Bits 21 LTMPALM TMPALM corresponds to the open-drain TMPALM output pin that flags a temperature event exceeding the default or user programmed level. The temperature alarm is a per-device alarm; the latched (LTMPALM) and unlatched 20 TMPALM (TMPALM) bits indicate whether a temperature event occurred and whether the alarm still exists (that is, whether the junction temperature still exceeds the programmed alarm level). To reset an alarm event, the user must write a 1 to the clear bit (Bit 6) in the PMU register. 19 LG0 LGx is the per-channel latched guard alarm bit, and Gx is the unlatched guard alarm bit. These bits indicate which channel flagged the alarm on the open-drain alarm pin, CGALM, and whether the alarm condition still exists. 18 G0 17 16 15 14 13 12 LG1 G1 LG2 G2 LG3 G3 11 10 9 8 7 6 5 4 LC0 C0 LC1 C1 LC2 C2 LC3 C3 LCx is the per-channel latched clamp alarm bit, and Cx is the unlatched clamp alarm bit. These bits indicate which channel flagged the alarm on the open-drain alarm pin CGALM and whether the alarm condition still exists. 3 to 0 (LSB) Unused readback bits Loads with 0s. Rev. E | Page 56 of 64 Data Sheet AD5522 READBACK OF DAC REGISTER The DAC register readback function is a 24-bit word that includes the mode, address, and DAC data bits. Table 35. DAC Register Readback Bit 23 (MSB) 22 Bit Name MODE1 MODE0 DAC Register-Specific Bits 21 to 16 A5 to A0 15 to 0 (LSB) D15 to D0 Description The MODE1 and MODE0 bits indicate the type of DAC register (X1, M, or C) that is read. 01 = DAC gain (M) register. 10 = DAC offset (C) register. 11 = DAC input data (X1) register. Address bits indicating the DAC register that is read (see Table 29). Contents of the addressed DAC register (X1, M, or C). Rev. E | Page 57 of 64 AD5522 Data Sheet APPLICATIONS INFORMATION POWER-ON DEFAULT The power-on default for all DAC channels is that the contents of each M register are set to full scale (0xFFFF), and the contents of each C register are set to midscale (0x8000). The contents of the DAC X1 registers at power-on are listed in Table 36. The power-on default for the alarm status register is 0xFFFFF0, and the power-on default for the comparator status register is 0x400000. The power-on default values of the PMU register and the system control register are shown in Table 37 and Table 38. SETTING UP THE DEVICE ON POWER-ON On power-on, default conditions are recalled from the poweron reset register to ensure that each PMU and DAC channel is powered up in a known condition. To operate the device, the user must follow these steps: 1. 2. 3. 4. Configure the device by writing to the system control register to set up different functions as required. Calibrate the device to trim out errors, and load the required calibration values to the gain (M) and offset (C) registers. Load codes to each DAC input (X1) register. When X1 values are loaded to the individual DACs, the calibration engine calculates the appropriate X2 value and stores it, ready for the PMU address to call it. Load the required PMU channel with the required force mode, current range, and so on. Loading the PMU channel configures the switches around the force amplifier, measure function, clamps, and comparators, and also acts as a load signal for the DACs, loading the DAC register with the appropriate stored X2 value. Because the voltage and current ranges have individual DAC registers associated with them, each PMU register mode of operation calls a particular X2 register. Therefore, only updates (that is, changes to the X1 register) to DACs associated with the selected mode of operation are reflected in the output of the PMU. If there is a change to the X1 value associated with a different PMU mode of operation, this X1 value and its M and C coefficients are used to calculate a corresponding X2 value, which is stored in the correct X2 register, but this value is not loaded to the DAC. Table 36. Default Contents of DAC Registers at Power-On DAC Register Offset DAC FIN DAC CLL DAC CLH DAC CPL DAC CPH DAC Default Value 0xA492 0x8000 0x0000 0xFFFF 0x0000 0xFFFF Table 37. Power-On Default for System Control Register Bit 21 (MSB) 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (LSB) Bit Name CL3 CL2 CL1 CL0 CPOLH3 CPOLH2 CPOLH1 CPOLH0 CPBIASEN DUTGND/CH Guard ALM Clamp ALM INT10K Guard EN GAIN1 GAIN0 TMP enable TMP1 TMP0 Latched Unused data bit Unused data bit Default Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Table 38. Power-On Default for PMU Register Bit 21 (MSB) 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (LSB) Rev. E | Page 58 of 64 Bit Name CH EN FORCE1 FORCE0 Reserved C2 C1 C0 MEAS1 MEAS0 FIN SF0 SS0 CL CPOLH Compare V/I LTMPALM TMPALM Unused data bit Unused data bit Unused data bit Unused data bit Unused data bit Default Value 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 Data Sheet AD5522 CHANGING MODES 3. There are different ways of handling a mode change. 2. Load any DAC X1 values that require changes. Remember that for force amplifier and comparator DACs, X1 registers are available per voltage and current range, so the user can preload new DAC values to make DAC updates ahead of time; the calibration engine calculates the X2 values and stores them. Change to the new PMU mode (FI or FV). This action loads the new switch conditions to the PMU circuitry and loads the DAC register with the stored X2 data. 4. The following steps describe another method for changing modes: 1. 2. REQUIRED EXTERNAL COMPONENTS In the PMU register (Bit 20 and Bit 19), enable the high-Z voltage or high-Z current mode to make the amplifier high impedance (SW5 open). Load any DAC X1 values that require changes. Remember that for force amplifier and comparator DACs, X1 registers are available per voltage and current range, so the user can preload new DAC values to make DAC updates ahead of time; the calibration engine calculates the X2 values and stores them. AVSS The minimum required external components for use with the AD5522 are shown in Figure 58. Decoupling is greatly dependent on the type of supplies used, other decoupling on the board, and the noise in the system. It is possible that more or less decoupling may be required. AVDD DVCC 10µF 10µF 10µF 0.1µF 0.1µF 0.1µF REF 0.1µF AVSS VREF AVDD DVCC CCOMP[0:3] EXTFOH3 EXTFOH0 CFF0 CFF3 FOH3 FOH0 MEASVH3 MEASVH0 EXTMEASIH3 EXTMEASIH0 RSENSE (UP TO ±80mA) RSENSE (UP TO ±80mA) EXTMEASIL0 EXTMEASIL3 DUT DUT EXTFOH2 EXTFOH1 CFF1 CFF2 FOH2 FOH1 MEASVH2 MEASVH1 EXTMEASIH2 EXTMEASIH1 RSENSE (UP TO ±80mA) RSENSE (UP TO ±80mA) EXTMEASIL1 DUTGND EXTMEASIL2 DUT DUT Figure 58. External Components Required for Use with the AD5522 Rev. E | Page 59 of 64 06197-037 1. When the high-Z (voltage or current) mode is used, the relevant DAC outputs are automatically updated (FIN, CLL, and CLH DACs). For example, in high-Z voltage mode, when new X1 writes occur, the FIN voltage X2 result is calculated, cached, and loaded to the FIN DAC. When forcing a voltage, current clamps are engaged, so the CLL current register can be loaded, and the gain and offset corrected and loaded to the DAC register. (The CLH current register works the same way.) Change to the new PMU mode (FI or FV). This action loads the new switch conditions to the PMU circuitry. Because the DAC outputs are already loaded, transients are minimized when changing current or voltage mode. AD5522 Data Sheet Table 39. ADCs and ADC Drivers Suggested For Use with AD5522 1 Part No. AD7685 Resolution 16 Sample Rate 250 kSPS Ch. No. 1 AIN Range 0 V to VREF Interface Serial, SPI ADC Driver ADA4841-x Multiplexer 2 ADG704, ADG708 AD7686 16 500 kSPS 1 0 V to VREF Serial, SPI ADA4841-x ADG704, ADG708 AD7693 3 16 500 kSPS 1 −VREF to +VREF Serial, SPI AD7610 16 250 kSPS 1 Serial/Parallel ADG1404, ADG1408, ADG1204 ADG1404, ADG1408, ADG1204 AD7655 16 1 MSPS 4 Bipolar 10 V, Bipolar 5 V, Unipolar 10 V, Unipolar 5 V 0 V to 5 V ADA4841-x, ADA4941-1 AD8021 Serial/Parallel Package MSOP, LFCSP MSOP, LFCSP MSOP, LFCSP LFCSP, LQFP ADA4841-x/ AD8021 Subset of the possible ADCs suitable for use with the AD5522. Visit www.analog.com for more options. For purposes of sharing an ADC among multiple PMU channels. Note that the multiplexer is not absolutely necessary because the AD5522 MEASOUTx path has a tristate mode per channel. 3 Do not allow the MEASOUTx output range to exceed the analog input (AIN) range of the ADC. 1 2 POWER SUPPLY DECOUPLING Careful consideration of the power supply and ground return layout helps to ensure the rated performance. Design the printed circuit board (PCB) on which the AD5522 is mounted so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5522 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. Establish the star ground point as close as possible to the device. For supplies with multiple pins (AVSS and AVDD), it is recommended that these pins be tied together and that each supply be decoupled only once. shielded with digital ground to avoid radiating noise to other parts of the board, and they should never be run near the reference inputs. It is essential to minimize noise on all VREF lines. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other to reduce the effects of feedthrough through the board. As is the case for all thin packages, care must be taken to avoid flexing the package and to avoid a point load on the surface of this package during the assembly process. Also, note that the exposed paddle of the AD5522 is connected to the negative supply, AVSS. The AD5522 should have ample supply decoupling of 10 µF in parallel with 0.1 µF on each supply located as close to the package as possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitors should have low effective series resistance (ESR) and low effective series inductance (ESL)—typical of the common ceramic types that provide a low impedance path to ground at high frequencies—to handle transient currents due to internal logic switching. Avoid running digital lines under the device because they can couple noise onto the device. However, allow the analog ground plane to run under the AD5522 to avoid noise coupling (applies only to the package with paddle up). The power supply lines of the AD5522 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching digital signals should be POWER SUPPLY SEQUENCING When the supplies are connected to the AD5522, it is important that the AGND and DGND pins be connected to the relevant ground planes before the positive or negative supplies are applied. This is the only power sequencing requirement for this device. TYPICAL APPLICATION FOR THE AD5522 Figure 59 shows the AD5522 used in an ATE system. The device can be used as a per-pin parametric unit to speed up the rate at which testing can be done. The central PMU (shown in the block diagram) is usually a highly accurate PMU and is shared among a number of pins in the tester. In general, many discrete levels are required in an ATE system for the pin drivers, comparators, clamps, and active loads. DAC devices such as the AD537x family offer a highly integrated solution for a number of these levels. Rev. E | Page 60 of 64 Data Sheet AD5522 DRIVEN SHIELD DAC ADC CENTRAL PMU GUARD AMP AD5522 VCH DAC DAC TIMING DATA MEMORY TIMING GENERATOR DLL, LOGIC DAC ADC VTERM DAC DAC PMU PMU DAC DAC PMU PMU VH DUT RELAYS FORMATTER DESKEW 50Ω COAX DRIVER VL DAC DAC VCL GND SENSE DAC COMPARE MEMORY FORMATTER DESKEW VTH COMP DAC ACTIVE LOAD DAC AD5560 DEVICE POWER SUPPLY VCOM 06197-038 DAC GUARD AMP ADC IOL DAC DAC VTL IOH Figure 59. Typical Applications Circuit Using the AD5522 as a Per-Pin Parametric Unit Rev. E | Page 61 of 64 AD5522 Data Sheet OUTLINE DIMENSIONS 14.20 14.00 SQ 13.80 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.20 MAX 80 61 61 1 80 1 60 60 PIN 1 EXPOSED PAD TOP VIEW (PINS DOWN) BOTTOM VIEW 0° MIN 0.15 0.05 SEATING PLANE (PINS UP) 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY 20 41 41 40 21 20 21 40 VIEW A 0.50 BSC LEAD PITCH 0.27 0.22 0.17 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD Figure 60. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-80-3 Dimensions shown in millimeters 14.20 14.00 SQ 13.80 0.75 0.60 0.45 1.20 MAX 12.20 12.00 SQ 11.80 80 61 61 1 80 1 60 60 PIN 1 EXPOSED PAD 0° MIN 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY VIEW A ROTATED 90° CCW (PINS UP) TOP VIEW (PINS DOWN) 20 41 40 21 VIEW A 6.50 BSC 41 0.50 BSC LEAD PITCH FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HU Figure 61. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-80-2 Dimensions shown in millimeters Rev. E | Page 62 of 64 20 21 40 0.27 0.22 0.17 071808-A 1.05 1.00 0.95 BOTTOM VIEW 9.50 BSC 071808-A 1.05 1.00 0.95 9.50 BSC SQ Data Sheet AD5522 ORDERING GUIDE Model 1 AD5522JSVDZ AD5522JSVUZ EVAL-AD5522EBDZ EVAL-AD5522EBUZ 1 Temperature Range (TJ) 25°C to 90°C 25°C to 90°C Package Description 80-Lead TQFP_EP with Exposed Pad on Bottom 80-Lead TQFP_EP with Exposed Pad on Top Evaluation Board with Exposed Pad on Bottom Evaluation Board with Exposed Pad on Top Z = RoHS Compliant Part. Rev. E | Page 63 of 64 Package Option SV-80-3 SV-80-2 AD5522 Data Sheet NOTES ©2008–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06197-0-5/12(E) Rev. E | Page 64 of 64