AD AD5522

Quad Parametric Measurement Unit With
Integrated 16-Bit Level Setting DACs
AD5522
Preliminary Technical Data
FEATURES
PRODUCT OVERVIEW
Quad Parametric Measurement Unit
FV, FI, FN, MV, MI Functions
4 Programmable Current Ranges (Internal RSENSE)
5uA, 20uA, 200uA and 2mA
1 Programmable Current Range up to 64mA (external RSENSE)
22.5 V FV Range with Asymmetrical Operation
Integrated 16-Bit DACs Provide Programmable Levels
Offset and Gain Correction on Chip
Low Capacitance Outputs Suited to Relay Less Systems
On-chip Comparators Per Channel
FI Voltage Clamps & FV Current Clamps
Guard Drive Amplifier
System PMU connections
Programmable Temperature Shutdown Feature
SPI/Microwire/DSP & LVDS Compatible Interfaces
Compact 80 lead TQFP Package with Exposed Pad (Top Or
Bottom)
The AD5522 is a high performance, highly integrated parametric
measurement unit consisting of four independent channels. Each
PPMU channel includes five, 16-bit, voltage out DACs setting the
programmable inputs levels for the force voltage input, clamp and
comparator inputs (high and low). Five programmable force and
measure current ranges are available ranging from 5µA to 64mA.
Four of these ranges use on chip sense resistors, while a high
current range up to 64mA is available per channel using off chip
sense resistors. Currents in excess of 64mA require an external
amplifier. Low capacitance DUT connections (FOH, EXT FOH)
ensure the device is suited to relay less test systems.
The PMU functions are controlled via a simple three wire serial
interface compatible with SPI/QSPI/Microwire and DSP interface
standards. Interface clocks of 50MHz allow fast updating of modes.
LVDS (Low Voltage Differential Signaling) interface protocol at
100MHz is also supported. Comparator outputs are provided per
channel for device go no-go testing and characterization. Control
registers provide easy way of changing force or measure conditions,
DAC levels and selected current ranges. SDO (serial data out)
allows the user to readback information for diagnostic purposes.
APPLICATIONS
Automatic Test Equipment (ATE)
per pin Parametric Measurement Unit
Continuity & Leakage Testing
Device Power Supply
Instrumentation
SMU (Source Measure Unit)
Precision Measurement
VREF
16
REFGND
X1 REG
M REG
C REG
16
16
DGND
DVCC
AVSS(0-4) AVDD(0-4)
AGND
CCOMP (0-3)
X2 REG
EXTFOH(0-3)
CLH
*2
*2
OFFSET DAC
FIN
*6
16
X1 REG
M REG
C REG
INTERNAL RANGE SELECT
(5uA, 20uA, 200uA, 2mA)
16
SW 1
16-Bit
FIN DAC
X2 REG
FOH(0-3)
-
16
16
X2 REG
SW 4
16-Bit
CLL DAC
*2
SW 6
SW 7
EXTMEASIH(0-3)
CLL
OFFSET DAC
BIAS TO
CENTER
IRANGE
SW 10
*2
SW 5
RSENSE
SW 2
16
1kΩ
FORCE
AMPLIFER
AGNDx
16
60Ω
+
*6
X1 REG
M REG
C REG
CFF(0-3)
SW 3
16
16
SYS_SENSE
EN
x4
16-Bit
CLH DAC
16
SYS_FORCE
+
-
SW 8
EXTERNAL
RSENSE
(CURRENTS
UP TO 64mA)
10kΩ
+
EXTMEASIL(0-3)
x5 or x10
MEASOUT (0-3)
SW 12
AGND (0-3)
16
MEASOUT
MUX & GAIN
x1/x0.2
X1 REG
M REG
C REG
16
*6
16
X2 REG
SW 9
MEASURE
CURRENT
IN AMP
SW 11
*6
16
+
-
TEMP
SENSOR
MEASVH (0-3)
+
-
16-Bit
CPH DAC
AGNDx
16
CPH
*6
16
X1 REG
M REG
C REG
16
*6
16
CPL
16-Bit
CPL DAC
X2 REG
-
+
-
-
GUARD AMP
DUTGND
SW 16
SW 14
DUT
GUARDIN (0-3)/
DUTGND (0-3)
DUTGND
MEASURE
VOLTAGE
IN AMP
- +
+
GUARD (0-3)
SW 13
+
x1
SW 15
COMPARATOR
10kΩ
AGNDx
16-Bit
OFFSET
DAC
16
TO ALL DAC
OUTPUT
AMPLIFIERS
TO
MEASOUT
MUX
16
SERIAL
INTERFACE
POWER ON
RESET
RESET
SDO
SCLK SDI SYNC BUSY
LOAD
LVDS/ CPOL0/
SCLK
SPI
CPOH0/
SDI
CPOL1/
SYNC
CPOH1/
SDO
CPOL2 CPOH2 CPOL3
/CPO0 /CPO1 /CPO2
TEMP
SENSOR
TMPALM
CLAMP &
GUARD
ALARM
CGALM
CPOH3
/CPO3
Figure 1. Functional Block Diagram
Rev.PrM
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
AD5522
Preliminary Technical Data
TABLE OF CONTENTS
Features..................................................................................................................... 1
Force Voltage, FV ............................................................................................. 26
Revision History...................................................................................................... 2
Force Current, FI.............................................................................................. 27
Specifications ........................................................................................................... 4
SPI INTERFACE .............................................................................................. 28
Table 2. TIMING Characteristics .................................................................... 9
LVDS INTERFACE.......................................................................................... 28
Absolute Maximum Ratings................................................................................ 12
Serial Interface Write Mode ........................................................................... 28
Thermal Resistance.......................................................................................... 12
RESET Function............................................................................................... 28
ESD Caution ..................................................................................................... 12
BUSY and LOAD Function ............................................................................ 28
Pin Configuration and Function Descriptions................................................. 13
Register Update Rates...................................................................................... 29
TERMINOLOGY.................................................................................................. 16
Register Selection............................................................................................. 30
Functional Description ........................................................................................ 17
Write System Control Register....................................................................... 31
Force Amplifier ................................................................................................ 19
Write PMU Register ........................................................................................ 33
Comparators ..................................................................................................... 19
Write DAC Register ......................................................................................... 35
Clamps ............................................................................................................... 19
Read Registers................................................................................................... 37
Current Range selection.................................................................................. 20
Readback of System Control Register........................................................... 38
High Current ranges........................................................................................ 20
Readback of PMU Register............................................................................. 39
Device under test ground (DUTGND) ........................................................ 20
Readback of Comparator Status Register..................................................... 39
Guard amplifer ................................................................................................. 21
Readback of Alarm Status Register ............................................................... 40
Compensation Capacitors .............................................................................. 21
Readback of DAC Register ............................................................................. 40
System Force Sense Switches.......................................................................... 22
Power On Default ............................................................................................ 41
Temperature Sensor......................................................................................... 22
Setting up the device on power on ................................................................ 42
Measure Output (MEASOUT) ...................................................................... 22
Changing Modes .............................................................................................. 42
DAC Levels............................................................................................................. 23
Required external components ...................................................................... 43
Offset DAC........................................................................................................ 23
Typical Application for the AD5522 ............................................................. 45
Offset and Gain registers ................................................................................ 23
Outline Dimensions ............................................................................................. 46
Cached x2 registers .......................................................................................... 23
Ordering Guide ................................................................................................ 47
VREF ..................................................................................................................... 24
Notes ....................................................................................................................... 48
Reference Selection.......................................................................................... 24
Calibration ........................................................................................................ 25
System Level Calibration ................................................................................ 25
REVISION HISTORY
Rev PrM, 12th March – Update to specification pages, addition of typical plots, general update of all sections of datasheet. Update of AD5522 models. .
Rev. PrM | Page 2 of 48
Preliminary Technical Data
VREF
16
X1 REG
M REG
C REG
16
16
REFGND
CCOMP 0
X2 REG
*2
EN
CH0
16-Bit
CLH DAC
16
*2
DGND
DVCC
AVSS(0-4) AVDD(0-4)
AGND
AD5522
EXTFOH 0
CLH
OFFSET DAC
INTERNAL RANGE SELECT
(5uA, 20uA, 200uA, 2mA)
16
16
FIN
*6
16
X1 REG
M REG
C REG
16
SW 1
16-Bit
FIN DAC
+
X2 REG
FOH 0
FORCE
AMPLIFER
AGND
*6
-
SW 6
SW 5
16
16
16
X2 REG
16-Bit
CLL DAC
SW 7
EXTMEASIH 0
CLL
+
-
OFFSET DAC
BIAS TO
CENTER
IRANGE
*2
SW 10
*2
SW 4
RSENSE
SW 2
16
X1 REG
M REG
C REG
CFF 0
SW 3
SW 8
EXTERNAL
RSENSE
(CURRENTS
UP TO 64mA)
10kΩ
+
EXTMEASIL 0
x5 or x10
MEASOUT 0
SW 12
AGND
MEASOUT
MUX & GAIN
x1/x0.2
+
-
TEMP
SENSOR
16
MEASURE
CURRENT
IN AMP
SW 11
*6
16
X1 REG
M REG
C REG
16
16
X2 REG
MEASVH 0
+
-
16-Bit
CPH DAC
AGND
SW 13
+
*6
DUTGND
x1
16
CPH
*6
16
X1 REG
M REG
C REG
16
16
SW 9
+
-
-
CPL
16-Bit
CPL DAC
X2 REG
-
+
GUARD AMP
GUARD 0
DUT
DUTGND
GUARDIN 0/
DUTGND 0
SW 14
SW 15
MEASURE
VOLTAGE
IN AMP
- +
SW 16
10kΩ
COMPARATOR
CPOL0/ SCLK
AGNDx
CPOH0/ SDI
CCOMP 1
MEASOUT 1
CPOL1/ SYNC
EXTFOH 1
CFF 1
FOH 1
EXTMEASIH 1
EXTMEASIL 1
MEASVH 1
GUARD 1
GUARDIN 1/DUTGND 1
CH1
CPOH1/ SDO
AGND
MUX
CCOMP 2
MEASOUT 2
EXTFOH 2
CFF 2
FOH 2
EXTMEASIH 2
EXTMEASIL 2
MEASVH 2
GUARD 2
GUARDIN 2/DUTGND 2
CH2
CPOL2/CPO0
CPOH2/CPO1
AGND
SYS_SENSE
SYS_FORCE
MUX
EN
CCOMP 3
EXTFOH 3
16
X1 REG
M REG
C REG
16
16
16-Bit
CLH DAC
16
X2 REG
*2
*2
CLH
CH3
OFFSET DAC
16
FIN
*6
16
16
X1 REG
M REG
C REG
16
INTERNAL RANGE SELECT
(5uA, 20uA, 200uA, 2mA)
SW 1
16-Bit
FIN DAC
+
X2 REG
FOH 3
FORCE
AMPLIFER
AGND
*6
-
X1 REG
M REG
C REG
16
16
16
X2 REG
16-Bit
CLL DAC
SW 6
SW 7
SW 5
EXTMEASIH 3
CLL
OFFSET DAC
BIAS TO
CENTER
IRANGE
*2
SW 10
*2
SW 4
RSENSE
SW 2
16
CFF 3
SW 3
+
-
SW 8
EXTERNAL
RSENSE
(CURRENTS
UP TO 64mA)
10kΩ
+
EXTMEASIL 3
x5 or x10
MEASOUT 3
SW 12
MEASOUT
MUX & GAIN
x1/x0.2
16
AGND
*6
X1 REG
M REG
C REG
16
16
X2 REG
MEASVH 3
+
-
16-Bit
CPH DAC
AGND
*6
CPH
*6
X1 REG
M REG
C REG
16
16
16-Bit
CPL DAC
X2 REG
SW 16
SW 13
+
DUTGND
x1
16
16
SW 9
MEASURE
CURRENT
IN AMP
SW 11
16
+
-
TEMP
SENSOR
+
-
-
CPL
GUARD 3
GUARD AMP
GUARDIN 3/
DUTGND 3
SW 14
SW 15
-
+
- +
MEASURE
VOLTAGE
IN AMP
DUT
10kΩ
COMPARATOR
AGND
16-Bit
OFFSET
DAC
16
SW 15a
16
SERIAL
INTERFACE
POWER ON
RESET
RESET
10kΩ
AGND
SDO
SCLK SDI SYNC BUSY LOAD
DUTGND
DUTGND
TO ALL DAC
OUTPUT
AMPLIFIERS
LVDS/ CPOL3
SPI
/CPO2
CPOH3
/CPO3
Figure 2. Detailed Block Diagram
Rev. PrM | Page 3 of 48
TO
MEASOUT
MUX
TEMP
SENSOR
TMPALM
CLAMP &
GUARD
ALARM
CGALM
AD5522
Preliminary Technical Data
SPECIFICATIONS
Table 1. AVDD ≥ 10V, AVSS ≤ −5V, |AVDD – AVSS| ≥ 20V and ≤ 33V, DVCC = 2.3V to 5.25V, VREF=5V, Gain (m), Offset (c) and DAC Offset
registers at default values (TJ = +25 to +90oC, max specs unless otherwise noted.)
Parameter
FORCE VOLTAGE
Min
Typ1
Max
Units
FOH Output Voltage Range
AVSS+4
AVDD-4
V
EXTFOH Output Voltage Range
AVSS+3
AVDD-3
V
-100
22.5
100
Output Voltage Span
Offset Error
Offset Error Tempco2
Gain Error
Gain Error Tempco2
±100
-0.5
0.5
±10
V
mV
µV/ oC
%
ppm/ oC
Linearity Error
-0.02
0.02
% FSR
Short Circuit Current Limit2
-120
-10
120
10
mA
mA
MEASURE CURRENT
Offset Error
Offset Error Tempco2
Gain Error
Gain Error Tempco2
Linearity Error
Output Voltage Span2
CM Error
-1
1
-0.01
0.01
22.5
%
µV/ oC
%
ppm/ oC
% FSCR
V
-0.005
0.005
%FSVR/V
±10
-1
1
25
Measure Current Ranges
±5
±20
±200
±2
µA
µA
µA
mA
Up to ±64
FORCE CURRENT
Voltage Compliance, FOH
Voltage Compliance, EXTFOH
Offset Error
AVSS+4
AVSS+3
-2
Gain Error
Gain Error Tempco2
Linearity Error
-0.02
0.02
V
V
%FSCR
ppm FS/
o
C
%
ppm/ oC
% FSCR
CM Error
-0.005
0.005
%FSCR/V
Offset Error Tempco2
Force Current Ranges
AVDD-4
AVDD-3
2
mA
±10
-0.5
0.5
±25
±5
±20
±200
±2
µA
µA
µA
mA
Up to ±64
mA
Rev. PrM | Page 4 of 48
Test Conditions/Comments
All current ranges from FOH at full scale current. Includes
±1V dropped across sense resistor
External high current range at full scale current. Does not
include ±1V dropped across sense resistor
Measured at Midscale Code, 0V. Prior to calibration.
Prior to calibration.
FSR = Fullscale Range. ±10 V range, Gain and offset errors
calibrated out.
On 64mA range.
In all other ranges.
MEASURE = (IDUT X RSENSE x GAIN)
V(Rsense)= ±1V, Measured with zero current flowing.
Instrumentation Amp Gain = 5 or 10
Offset and Gain errors calibrated out
% of FS Change at measure output per V change in DUT
voltage
Set using internal sense resistor
Set using internal sense resistor
Set using internal sense resistor
Set using internal sense resistor
Set using external sense resistor, internal amplifier can
drive to 64mA
Measured at Midscale Code, 0V. Prior to calibration.
Prior to calibration.
% of FS Change at measure output per V change in DUT
voltage
Set using internal sense resistor, 200kΩ
Set using internal sense resistor, 50kΩ
Set using internal sense resistor, 5kΩ
Set using internal sense resistor, 500Ω
Set using external sense resistor, internal amplifier can
drive to 64mA
Preliminary Technical Data
AD5522
MEASURE VOLTAGE
Measure Voltage Range
Offset Error
Offset Error
Offset Error Tempco2
Gain Error
Gain Error
Gain Error Tempco2
Linearity Error
COMPARATOR
Comparator Span
Offset Error
Propagation delay2
VOLTAGE CLAMPS
Clamp Span
Positive Clamp Accuracy
Negative Clamp Accuracy
Recovery Time2
Activation Time2
CURRENT CLAMPS
Clamp Accuracy
Recovery Time2
Activation Time2
FOH, EXTFOH, EXTMEASIL,
EXTMEASIH, CFF
Pin Capacitance2
Leakage Current
Leakage Current Tempco2
MEASVH
Pin Capacitance2
Leakage/Bias Current
Leakage Current Tempco2
SYS_SENSE
Pin Capacitance2
SYS_SENSE Impedance
Leakage Current
Leakage Current Tempco2
SYS_FORCE
Pin Capacitance2
SYS_FORCE Impedance
Leakage Current
Leakage Current Tempco2
AVDD-4
AVSS+4
-10
-40
10
40
±10
-0.5
-0.5
0.5
0.5
±10
-0.01
-10
0.01
1
0.25
22.5
10
V
mV
μs
22.5
150
V
mV
mV
μs
μs
-150
0.5
1.5
1.5
3
0.5
1.5
Programmed
Clamp value
+15
1.5
3
Prog’d
Clamp
value
10
-3
% of FSC
range
pF
nA
nA/ oC
3
pF
nA
nA/ oC
1.3
3
pF
kΩ
nA
nA/ oC
80
3
pF
Ω
nA
nA/ oC
3
±0.1
Gain = 1
Gain = 0.2
Clamp current scales with selected range
On or off switch leakage
SYS_Sense Connected, Force Amplifier Inhibited
3
1
-3
±0.1
SYS_Force Connected, Force Amplifier Inhibited
6
60
-3
±0.1
Includes FOH, MEASVH, SYS_SENSE, SYS_FORCE,
EXTMEASIL
COMBINED LEAKAGE at DUT
Leakage Current
Leakage Current Tempco2
DUTGND
Voltage Range
Leakage Current
GAIN = 1, measured at 0V
GAIN = 0.2, measured at 0V
μs
μs
3
±0.1
-3
V
V
mV
mV
µV/ oC
% FSR
% FSR
ppm/ oC
% FSR
-15
15
nA
nA/ oC typ
500
1
mV
μA
±0.5
-500
-1
Rev. PrM | Page 5 of 48
AD5522
Preliminary Technical Data
MEASURE OUTPUT (MEASOUT)
Measure Output Voltage Span
Measure Pin output Impedance
Output leakage current
Output Capacitance2
Max Load Capacitance2
Output Current drive2
Short Circuit Current2
MEASOUT Slew Rate2
MEASOUT enable time 2
MEASOUT disable time
-3
2
-10
2
MEASOUT MI to MV switching time2
GUARD OUTPUT
Guard Output Voltage Span
Guard Output Offset
Short Circuit Current2
Max Load Capacitance2
Guard Output Impedance
Slew Rate2
Alarm Activation Time2
FORCE AMPLIFIER
Slew Rate2
Gain Bandwidth2
Max stable load Capacitance2
22.5
100
3
15
1
10
2
150
320
400
1100
200
22.5
10
10
1000
-10
-10
100
5
200
0.4
1.3
10,000
100
V
Ω
nA
pF
μF
mA
mA
V/μs
ns
ns
ns
Measured from BUSY rising edge.
V
mV
mA
nF
Ω
V/μs
μs
CLOAD = 10 pf
Alarm delayed to eliminate false alarms.
V/us
MHz
pF
nF
17
17
32
TBD
TBD
40
40
80
80
300
µs
µs
µs
µs
µs
17
18
40
TBD
TBD
40
40
80
TBD
TBD
µs
µs
µs
µs
µs
18
22
45
1000
2300
55
85
120
TBD
4000
µs
µs
µs
µs
µs
20
21
50
1000
2300
65
85
120
TBD
4000
µs
µs
µs
µs
µs
MI SETTLING TIME TO 0.05% OF FS
64mA Range2
2mA range2
200µA range2
20µA range2
5µA range2
FI SETTLING TIME TO 0.05% OF FS
64mA Range2
2mA range2
200µA range2
20µA range2
5µA range2
MV SETTLING TIME TO .05% OF FS
64mA Range2
2mA range2
200µA range2
20µA range2
5µA range2
With SW12 off
Closing SW12, Measured from BUSY rising edge.
Opening SW12, Measured from BUSY rising edge.
FV SETTLING TIME TO 0.05% OF FS
64mA Range2
2mA range2
200µA range2
20µA range2
5µA range2
With respect to AGND
Software Programmable output range
Rev. PrM | Page 6 of 48
Ccomp=100pF, Cff=220pF, Cload=200pF
Ccomp=100pF, Cff=220pF, Cload=200pF
CCOMP = 100pF. Larger Load cap requires larger CCOMP
CCOMP = 1nF. Larger Load cap requires larger CCOMP
Mid scale to full scale change, Measured from /SYNC
rising edge, Clamps ON
Ccomp=100pF, Cff=220pF, Cload=200pF
Ccomp=100pF, Cff=220pF, Cload=200pF
Ccomp=100pF, Cff=220pF, Cload=200pF
Ccomp=100pF, Cff=220pF, Cload=200pF
Ccomp=100pF, Cff=220pF, Cload=200pF
Mid scale to full scale change, Measured from /SYNC
rising edge, Clamps ON
Ccomp=100pF, Cff=220pF, Cload=200pF
Ccomp=100pF, Cff=220pF, Cload=200pF
Ccomp=100pF, Cff=220pF, Cload=200pF
Ccomp=100pF, Cff=220pF, Cload=200pF
Ccomp=100pF, Cff=220pF, Cload=200pF
Mid scale to full scale change, Measured from /SYNC
rising edge, Clamps ON
Ccomp=100pF, Cload=200pF
Ccomp=100pF, Cload=200pF
Ccomp=100pF, Cload=200pF
Ccomp=100pF, Cload=200pF
Ccomp=100pF, Cload=200pF
Mid scale to full scale change, Measured from /SYNC
rising edge, Clamps ON
Ccomp=100pF, Cload=200pF
Ccomp=100pF, Cload=200pF
Ccomp=100pF, Cload=200pF
Ccomp=100pF, Cload=200pF
Ccomp=100pF, Cload=200pF
Preliminary Technical Data
DAC SPECIFICATIONS
Resolution
Voltage Output Span2
Differential Nonlinearity2
COMPARATOR DAC DYNAMIC
SPECIFICATIONS
Output Voltage Settling Time2
Slew Rate2
Digital-to-Analog Glitch Energy2
Glitch Impulse Peak Amplitude2
REFERENCE INPUT
VREF DC Input Impedance
VREF Input Current
VREF Range
DIE TEMPERATURE SENSOR
Accuracy
Output Voltage at 25°C
Output Scale Factor
Output Voltage Range
INTERACTION & CROSSTALK
Crosstalk (VM) 2
Crosstalk (MI) 2
AD5522
16
22.5
1
Bits
V
LSB
1.5
µs
V/µs
nV-s
mV
500mV change to ±½ LSB.
10
5
MΩ
µA
V
Typically 100 MΩ.
Per input. Typically ±30 nA.
0
3
°C
V
mV/°C
V
-0.01
0.01
% FSR
-0.01
0.01
% FSR
0.5
mV
-1
5.5
20
10
1
-10
2
±7
1.5
5
Crosstalk within a channel2
Shorted DUT Crosstalk2
SPI INTERFACE LOGIC
LOGIC INPUTS
VIH, Input High Voltage
VIL, Input Low Voltage
IINH, IINL, Input Current
CIN, Input Capacitance2
CMOS LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
Tristate leakage current
Output Capacitance2
OPEN DRAIN LOGIC OUTPUTS
VOL, Output Low Voltage
Output Capacitance2
LVDS INTERFACE LOGIC
LOGIC INPUTS – Reduced Range Link
Input Voltage Range
Input Differential Threshold
External Termination Resistance
Differential Input Voltage
LOGIC OUTPUTS – Reduced Range Link
Output Offset Voltage
Output Differential Voltage
TBD
TBD
1.7/2.0
-1
0.7/0.8
1
10
V
V
µA
pF
0.4
1
10
V
V
µA
pF
0.4
10
V
pF
1575
100
120
mV
mV
Ω
mV
VREF=5V, within a range of -16.25 to 22.5V
Guaranteed monotonic by design over temperature.
All channels in FIMV mode, measure the voltage for one
channel in the highest current force range, once when all
three other channels are at FI = 0mA and once when
they are at 2mA
All channels in FVMI mode, measure the current for one
channel in the lowest current measure range, once when
all three other channels are at FV = -10V and once when
they are at +10V
All channels in FVMI mode, one channel at midscale,
measure the current for one channel in the lowest
current range, for a change in comparator or clamp DAC
levels for that PMU.
S/C applied to one PMU channel, measure effect on
other channels.
(2.3 to 2.7)/(2.7 to 5.25V) Jedec Compliant Input Levels
(2.3 to 2.7)/(2.7 to 5.25V) Jedec Compliant Input Levels
SDO, CPOX
DVCC – 0.4
-1
875
-100
80
100
100
1200
400
mV
mV
Rev. PrM | Page 7 of 48
IOL = 500 µA
BUSY, TMPALM, CGALM
IOL = 500 µA, CL = 50pF, RPULLUP = 1kΩ
AD5522
NOISE PERFORMANCE
NSD of Measure Voltage In-Amp
NSD of Measure Current In-Amp
NSD of Force Amplifier
POWER SUPPLIES
AVDD
AVSS
DVCC
AIDD
AISS
AIDD
AISS
DICC
Max Power Dissipation2
Power Supply Sensitivity2
∆Forced Voltage/∆AVDD
∆Forced Voltage/∆AVSS
∆Measured Current/∆AVDD
∆Measured Current/∆AVSS
∆Forced Current/∆AVDD
∆Forced Current/∆AVSS
∆Measured Voltage/∆AVDD
∆Measured Voltage/∆AVSS
∆Forced Voltage/∆DVCC
∆Measured Current/∆DVCC
∆Forced Voltage/∆DVCC
∆Measured Current/∆DVCC
1
2
Preliminary Technical Data
290
290
300
10
-5
2.3
28
-23
5.25
25
-25
35
-35
3
7
nV/√Hz
nV/√Hz
nV/√Hz
@ 1kHz, measured at MEASOUT
@ 1kHz, measured at MEASOUT
@ 1kHz, measured at FOH
V
V
V
mA
mA
mA
mA
mA
W
| AVDD – AVSS| ≤ 33V
Internal ranges (5μA to 2mA), Excluding Load Conditions
Internal ranges (5μA to 2mA), Excluding Load Conditions
External range, Excluding Load Conditions
External range, Excluding Load Conditions
From DC to 1kHz
-75
-75
-75
-75
-75
-75
-75
-75
-90
-90
-90
-90
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Typical specifications are at 25°C and nominal supply, ±15.25V, unless otherwise noted.
Guaranteed by design and characterization, not production tested.
FV = Force Voltage, FI = Force Current, MV = Measure Voltage, MI = Measure Current
FSR = Full Scale Range, FSCR = Full Scale Current Range, FS = Full Scale.
Specifications subject to change without notice.
Rev. PrM | Page 8 of 48
Preliminary Technical Data
AD5522
TABLE 2. TIMING CHARACTERISTICS
AVDD ≥ 10V, AVSS ≤ −5V, |AVDD – AVSS| ≥ 20V and ≤ 33V, DVCC = 2.3V to 5.25V, VREF=5V
(TJ = +25 to +90oC, max specs unless otherwise noted.)
SPI INTERFACE (Figure 5 and Figure 6)
Parameter1, 2, 3 Limit at TMIN, TMAX
595
t1
20
t2
8
t3
8
t4
10
Unit
ns min
ns min
ns min
ns min
ns min
t5
15
ns min
Minimum SYNC High Time.
t6
5
ns min
29th SCLK Falling Edge to SYNC Rising Edge.
t7
t8
t93
5
4.5
30
ns min
ns min
ns max
Data Setup Time.
Data Hold Time.
SYNC Rising Edge to BUSY Falling Edge.
t10
Description
Single channel write time
SCLK Cycle Time.
SCLK High Time.
SCLK Low Time.
SYNC Falling Edge to SCLK Falling Edge Setup Time.
BUSY Pulse Width Low
1 DAC X1
1.25
µs max
BUSY Pulse Width Low
2 DAC X1
1.75
µs max
BUSY Pulse Width Low
3 DAC X1
2.25
µs max
BUSY Pulse Width Low
4 DAC X1
2.75
µs max
BUSY Pulse Width Low
Other Regs
270
ns max
BUSY Pulse Width Low, System Control Register/PMU Register/M or C Registers
t11
20
ns min
t12
20
ns min
29th SLCK Falling EDGE to LOAD Falling Edge
LOAD pulse width low
t13
150
ns min
BUSY rising edge to FOH Output Response time
t14
0
ns min
BUSY rising edge to LOAD falling edge
t15
100
ns max
LOAD rising edge to FOH Output Response time
t16
10
ns min
RESET Pulse Width Low.
t17
300
µs max
RESET Time Indicated by BUSY Low.
t18
100
ns min
Minimum SYNC High Time in Readback Mode.
25
45
60
LVDS INTERFACE (Figure 7)
Parameter1, 2, 3 Limit at TMIN, TMAX
t1
10
t2
4
t3
2
ns max
ns max
ns max
DVCC = 5V to 5.25V, SCLK Rising Edge to SDO Valid.
DVCC = 3V to 3.7V, SCLK Rising Edge to SDO Valid
DVCC = 2.3V to 3V, SCLK Rising Edge to SDO Valid
Unit
ns min
ns min
ns min
Description
SCLK Cycle Time.
SCLK Pulse Width High and Low Time.
SYNC to SCLK Setup Time.
t4
t5
t6
2
2
2
ns min
ns min
ns min
Data Setup Time.
Data Hold Time.
SCLK to SYNC Hold Time.
t7
t8
TBD
TBD
ns min
ns min
SCLK Rising Edge to SDO Valid.
SYNC high time
t
4, 5
19
1
Guaranteed by design and characterization, not production tested.
All input signals are specified with tr = tf = 2 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V.
3
See Figure 5 and Figure 6
4
This is measured with load circuit of Figure 4
5
SDO output gets slower with lower DVCC supply and may require use of slower SCLK.
2
Rev. PrM | Page 9 of 48
AD5522
Preliminary Technical Data
V CC
IOL
200µA
RL
TO
OUTPUT
PIN
2.2kΩ
TO
OUTPUT
PIN
CL
V OH (min) - V OL (max)
2
50pF
V OL
CL
50pF
IOL
200µA
Figure 4. Load Circuit for SDO, BUSY Timing Diagram
Figure 3.. Load Circuit forCGALM, TMPALM
t1
SCLK
1
24
29
2
t2
t3
t4
t6
SYNC
t5
t7
t8
DB0
DB28
SDI
t9
t10
BUSY
t11
t12
LOAD1
t13
FOH1
t14
t12
LOAD2
FOH2
t15
t16
RESET
t17
BUSY
1LOAD ACTIVE
2 LOAD ACTIVE
DURING BUSY
AFTER BUSY
Figure 5. SPI Write Timing (Write word contains 29 bits)
Rev. PrM | Page 10 of 48
Preliminary Technical Data
AD5522
SCLK
58
29
t19
t18
SYNC
SDI
DB28
DB23/
DB28
DB0
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
DB23/
DB28
SDO
DB0
SELECTED REGISTER DATA
CLOCKED OUT
UNDEFINED
Figure 6. SPI Read Timing (Readback word contains 24 bits and can be clocked out with a minimum of 24 clock edges)
t8
SYNC
SYNC
t6
t1
t3
SCLK
SCLK
SDI
MSB
D28
t4
t2
MSB
D23/D28
LSB
D0
LSB
D0
SDI
t7
t5
SDO
MSB
DB23/
DB28
SDO
UNDEFINED
LSB
DB0
SELECTED REGISTER DATA CLOCK OUT
Figure 7. LVDS Read and Write Timing, (Readback word contains 24 bits and can be clocked out with a minimum of 24 clock edges)
Rev. PrM | Page 11 of 48
AD5522
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 3. AD5522 Absolute Maximum Ratings
Parameter
Supply Voltage AVDD to AVSS
AVDD to AGND
AVSS to AGND
VREF to AGND
DUTGND to AGND
REFGND to AGND
DVCC to DGND
AGND to DGND
Digital Inputs to DGND
Analog Inputs to AGND
Storage Temperature
Operating Junction Temperature
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Junction Temperature
THERMAL RESISTANCE3
Rating
34V
-0.3V to 34V
0.3V to -34V
-0.3 V, +7V
AVDD +0.3V to AVSS -0.3V
AVDD +0.3V to AVSS -0.3V
- 0.3V to 7V
- 0.3V to +0.3V
- 0.3V to DVCC +0.3V
AVSS - 0.3V to AVDD +0.3V
–65°C to +125°C
+25 to +90°C
Thermal resistance values are specified for the worst-case
conditions, i.e., specified for device soldered in circuit board for
surface mount packages.
Table 4. Thermal Resistance (JEDEC 4 layer (1S2P) board)
Air Flow (LFPM)
TQFP Exposed Pad Down
TQFP Exposed Pad Up
θJA
0
22.3
θJC
4.8
200
17.2
500
15.1
Unit
°C/W
°C/W
θJA
TBD
θJC
2
TBD
TBD
°C/W
°C/W
Table 5. Thermal Resistance (JEDEC 4 layer (1S2P) board
with cooling plate4 at 45°C, natural convection at 55°C
ambient)
Package Thermals
230°C
10s to 40s
150°C max
TQFP Exposed Pad Down
TQFP Exposed Pad Up
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
3
4
θJA
5.4
3.0
θJC
4.8
2
Unit
°C/W
°C/W
Simulated Thermal information.
Assumes perfect thermal contact between cooling plate and exposed
paddle
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrM | Page 12 of 48
Preliminary Technical Data
AD5522
EXTFOH1
AVSS
61
MEASOUT3
63
62
MEASOUT1
MEASOUT0
MEASOUT2
64
65
66
AVSS
SYS_FORCE
68
67
SYS_SENSE
AGND
69
REFGND
71
70
DUTGND
AVDD
VREF
72
73
74
CGALM
SPI/LVDS
75
TMPALM
77
76
AVSS
RESET
78
80
79
EXTFOH0
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AVDD
1
60
AVDD
CFF0
2
59
CFF1
CCOMP0
3
58
CCOMP1
EXTMEASIH0
4
57
EXTMEASIH1
EXTMEASIL0
5
56
EXTMEASIL1
FOH0
6
55
FOH1
GUARD0
7
54
GUARD1
GUARDIN0
/DUTGND0
8
53
GUARDIN1
/DUTGND1
MEASVH0
9
52
MEASVH1
AGND
10
51
AGND
AGND
11
TOP VIEW
EXPOSED PAD ON BOTTOM
50
AGND
MEASVH2
12
49
MEASVH3
GUARDIN2
/DUTGND2
(Not to Scale)
13
48
GUARDIN3
/DUTGND3
GUARD2
14
47
GUARD3
FOH2
15
46
FOH3
EXTMEASIL2
16
45
EXTMEASIL3
EXTMEASIH2
17
44
EXTMEASIH3
CCOMP2
18
43
CCOMP3
CFF2
19
42
CFF3
AVDD
20
41
AVDD
40
EXTFOH3
38
39
AVSS
CPOH3/CPO3
37
CPOL3/CPO2
35
36
CPOL2/CPO0
CPOH2/CPO1
33
34
DVCC
32
SDO
LOAD
30
31
DGND
29
CPOL1/SYNC
CPOH1/SDO
27
28
SDI
26
CPOH0/SDI
SYNC
24
25
BUSY
SCLK
23
AVSS
CPOL0/SCLK
21
22
EXTFOH2
AD5522
Figure 8. Pin Configuration (Exposed Pad on bottom of package)
Table 6. Pin Function Descriptions
Pin No.
Bottom
Pin No.
Top
Mnemonic
Exposed Pad
22, 39, 62,
67, 79,
1, 20, 41, 60,
74
33
2, 14, 19,
42,59,
7, 21, 40,
61, 80
48
AVSS(0-4)
Description
The exposed pad is electrically connected to AVSS.
TQFP with exposed pad on BOTTOM: For enhanced thermal, electrical and board level
performance, the exposed paddle on the bottom of the package should be soldered to a
corresponding thermal land paddle on the PCB.
Negative analog supply voltage
AVDD(0-4)
Positive analog supply voltage
LOAD
Active low logic input used for synchronizing updates within one device or across a group
of devices. If synchronization is not required, LOAD may be tied low and updates to DAC
channels or PMU modes will happen as they are presented to the device. See the BUSY and
LOAD FUNCTIONS section for detailed information.
34
10, 11, 50,
51, 69
30
23
47
12, 30, 31,
70, 71
51
58
DVCC
AGND
Digital supply voltage
Analog ground, reference points for force and measure circuitry
DGND
BUSY
Digital ground reference point.
Open Drain active low input/output indicating the status of interface.
24
25
57
56
SCLK
CPOL0/ SCLK
Clock input, active falling edge
Comparator output low in SPI mode and SCLK in LVDS interface mode
26
55
CPOH0/ SDI
Comparator output high in SPI mode and SDI in LVDS interface mode
27
28
54
53
SDI
SYNC
Serial data input
Frame sync, active low
29
31
52
50
CPOL1/ SYNC
CPOH1/SDO
Comparator output low in SPI mode and SYNC in LVDS interface mode
Comparator output high in SPI mode and SDO in LVDS interface mode
Rev. PrM | Page 13 of 48
AD5522
Preliminary Technical Data
32
35
36
37
38
66, 65, 64,
63
68
70
71
72
75
49
46
45
44
43
15, 16, 17,
18
13
11
10
9
6
SYS_FORCE
SYS_SENSE
REFGND
VREF
SPI/LVDS
76
5
CGALM
77
4
TMPALM
78
3
RESET
3, 18, 43, 58
78, 63, 38,
23
79, 62, 39,
22
1, 60, 41,
20
75, 66, 35,
26
77, 64, 37,
24
76, 65, 36,
25
72, 69, 32,
29
8
CCOMP(0-3)
74, 67, 34,
27
73, 68, 33,
28
GUARD (0-3)
2, 19, 42, 59
80, 21, 40,
61
6, 15, 46, 55
4, 17, 44, 57
5, 16, 45, 56
9, 12, 49, 52
73
7, 14 , 47, 54
8, 13, 48, 53
SDO
CPOL2/CPO0
CPOH2/CPO1
CPOL3/CPO2
CPOH3/CPO3
MEASOUT(0-3)
CFF (0-3)
Serial data out, for readback and diagnostic purposes
Comparator output Low, comparator window in LVDS interface mode
Comparator output Low, comparator window in LVDS interface mode
Comparator output Low, comparator window in LVDS interface mode
Comparator output Low, comparator window in LVDS interface mode
Multiplexed DUT voltage/Current sense output/temperature sensor voltage per channel,
referenced to AGND.
External FORCE signal input, enables connection of system PMU.
External SENSE signal output, enables connection of system PMU.
Accurate analog reference input ground.
Reference Input for DAC channels, 5V for specified performance.
Interface select pin. Logic low selects SPI interface compatible mode, logic high selects
LVDS interface mode. In LVDS mode the CPOH(0-3) pins default to differential interface
pins.
CGALM is an open drain pin providing shared Alarm information for Guard amplifier and
Clamp circuitry.
By default, this output pin is disabled. The System Control Register allows user to enable
this function and to set the open drain output as a latched output, or to configure either
the Guard or Clamp function or both flagging the alarm pin.
When this pin flags an alarm, the origins of the alarm may be determined by reading back
the Alarm Status Register. Two flags per channel in this word (one latched, one unlatched)
indicate which function caused the alarm and if the alarm is still present.
The function of this pin is to flag a Temperature Alarm. It is a latched active low open drain
output indicating the junction temperature has exceeded either the programmed or
default (130degC) temperature setting.
Two flags in the Alarm Status Register (one latched, one unlatched) indicate if the
temperature has dropped below 130degC or still above. User action is required to clear this
latched alarm flag, by writing to the “CLEAR” bit in any of the PMU registers.
Active low, level sensitive input used to reset all internal nodes on the device to their
power-on reset value.
Compensation capacitor Input per channel. See section on compensation capacitors..
FOH(0-3)
External capacitor optimizing the stability performance of the force amplifier (per
channel).. See section on Compensation Capacitors
Per channel, Force output for high current range. Use external resistor here for current
range up to 64mA.
Per channel force output for all other ranges.
EXTMEASIH(0-3)
Per channel sense input (high sense) for high current range.
EXTMEASIL(0-3)
Per channel sense input (Low sense) for high current range.
MEASVH(0-3)
Per channel DUT voltage sense input (high sense)
DUTGND
DUT voltage sense input (low sense). By default, DUTGND is shared between all four PMU
channels. If user requires a DUTGND input per channel, the GUARDIN (0-3)/DUTGND(0-3)
pin may be configured to be a DUTGND input per each PMU channel.
Guard output drive.
EXTFOH(0-3)
GUARDIN(0-3)
/DUTGND(0-3)
This pin has dual functionality; it may be either a Guard input per channel or DUTGND per
channel.
Its function is determined via the serial interface. The power on default is GUARDIN, where
it functions as the input to the Guard Amplifier.
Alternatively, it may be configured to be used as a DUTGND input per channel.
In this case, the input to the Guard amplifier is internally connected to MEASVH and the
GUARDIN/DUTGND pin is used as a DUTGND input per channel. See section on Guard
Amplifier
Rev. PrM | Page 14 of 48
CCOMP2
CFF2
AVDD
62
61
EXTMEASIH2
64
63
FOH2
EXTMEASIL2
65
67
66
GUARDIN2
\DUTGND2
GUARD2
MEASVH2
69
68
70
AGND
AGND
71
GUARDIN0
DUTGND0
MEASVH0
73
72
FOH0
EXTMEASIL0
GUARD0
74
75
77
76
CCOMP0
EXTMEASIH0
AD5522
78
AVDD
80
79
CFF0
Preliminary Technical Data
EXTFOH0
1
60
EXTFOH2
AVSS
2
59
AVSS
RESET
3
58
BUSY
TMPALM
4
57
SCLK
CGALM
5
56
CPOL0/SCLK
SPI/LVDS
6
55
CPOH0/SDI
AVDD
7
54
SDI
8
53
SYNC
52
CPOL1/SYNC
TOP VIEW
EXPOSED PAD ON TOP
51
DGND
50
CPOH1/SDO
(Not to Scale)
49
SDO
48
LOAD
DUTGND
AD5522
VREF
9
REFGND
10
SYS_SENSE
11
AGND
12
SYS_FORCE
13
Figure 9. Pin Configuration (Exposed Pad on Top of package)
Rev. PrM | Page 15 of 48
40
AVDD
EXTMEASIL3
39
36
FOH3
CFF3
35
GUARD3
37
34
38
33
GUARDIN3/
DUTGND3
CCOMP3
32
MEASVH3
EXTMEASIH3
30
31
AGND
EXTFOH3
AGND
41
29
20
28
AVSS
EXTFOH1
MEASVH1
42
GUARDIN1/
DUTGND1
19
27
CPOH3/CPO3
AVSS
GUARD1
43
26
18
FOH1
CPOL3/CPO2
MEASOUT3
25
44
EXTMEASIL1
17
23
CPOH2/CPO1
MEASOUT2
24
45
CCOMP1
16
EXTMEASIH1
CPOL2/CPO0
MEASOUT1
21
DVCC
46
22
47
15
CFF1
14
AVDD
AVSS
MEASOUT0
AD5522
Preliminary Technical Data
TERMINOLOGY
Offset Error
Offset error is a measure of the difference between actual and
ideal voltage expressed in mV.
Gain Error Gain error is the difference between full-scale error
and zero-scale error. It is expressed in %.
Gain Error = Full-Scale Error − Zero-Scale Error
Linearity Error
Relative accuracy, or endpoint linearity, is a measure of the
maximum deviation from a straight line passing through the
endpoints of the full-scale range. It is measured after adjusting
for offset error and gain error and is expressed in % FSR.
CM Error
Common Mode Error is the error at the output of the amplifier
due to the common mode input voltage. It is expressed in % of
FSR/V.
Clamp Accuracy
Clamp accuracy is a measure of where the clamps begin to
function fully and limit the clamped voltage or current.
Leakage Current
Current measured at an output pin, when that function is off or
high impedance.
Pin Capacitance
Capacitance measured at a pin when that function is off or high
impedance.
Slew Rate
The rate of change of output voltage, expressed in V/μs.
DAC SPECIFIC TERMS
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1LSB maximum
ensures monotonicity.
Output Voltage Settling Time
The amount of time it takes for the output of a DAC to settle to
a specified level for a full-scale input change.
Digital-to-Analog Glitch Energy
The amount of energy injected into the analog output at the
major code transition. The area of the glitch in is specified in
nV-s. It is measured by toggling the DAC register data between
0x1FFF and 0x2000.
Digital Crosstalk
The glitch impulse transferred to the output of one converter
due to a change in the DAC register code of another converter
is defined as the digital crosstalk and is specified in nV-s.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the device’s digital inputs can be capacitively coupled both
across and through the device to show up as noise on the
VOUT pins. It can also be coupled along the supply and
ground lines. This noise is digital feedthrough.
Rev. PrM | Page 16 of 48
Preliminary Technical Data
AD5522
TYPICAL PERFORMANCE CHARACTERISTICS
Leakage as function of Temp, V = 12V
2
EXTFOH
CFF
Leakage Current - nA
1.5
FOH
EXTMEASIH
1
EXTMEASIL
MEASVH
GRD_DUTGND
0.5
COMBINED LEAKAGE
0
-0.5
25
35
45
55
65
75
85
Temp - degC
Figure 13Leakage as a function of Temperature (V = 12V).
Figure 10 FV Linearity
Leakage as function of Temp, V = 0V
1
Leakage Current - nA
EXTFOH
CFF
0.8
FOH
EXTMEASIH
0.6
EXTMEASIL
0.4
MEASVH
GRD_DUTGND
0.2
COMBINED LEAKAGE
0
-0.2
25
45
65
85
Temp - degC
Figure 14. Leakage as a function of temp, (V = 0V)
Figure 11MV linearity
Leakage as function of Temp, V = -12V
0.2
Leakage Current - nA
0
-0.2
-0.4
EXTFOH
CFF
-0.6
FOH
EXTMEASIH
-0.8
EXTMEASIL
MEASVH
-1
GRD_DUTGND
-1.2
COMBINED LEAKAGE
25
45
65
85
Temp - degC
Figure 12MI Linearity in 2mA range
Figure 15. Leakage as a function of temp, (V = -12V)
Rev. PrM | Page 17 of 48
95
AD5522
Preliminary Technical Data
0.15
0.1
0.05
nA
0
EXTFOH
-0.05
CFF
FOH
-0.1
EXTMEASIH
EXTMEASIL
-0.15
MEASVH
GRD_DUTGND
12
8
10
6
4
V
2
0
-2
-4
-6
-8
COMBINED LEAKAGE
-1
0
-1
2
-0.2
Figure 18. ACPSRR versus Frequency
Figure 16. Leakage as a function of voltage (25degC).
Figure 17Noise Spectral density
Rev. PrM | Page 18 of 48
Preliminary Technical Data
AD5522
FUNCTIONAL DESCRIPTION
The AD5522 is a highly integrated quad per pin parametric
measurement unit (PPMU) for use in semiconductor automatic
test equipment. It contains programmable modes to force a pin
voltage and measure the corresponding current (FVMI), force
current measure voltage (FIMV), force current measure current
(FIMI), force voltage measure voltage (FVMV) and force
nothing measure voltage (FNMV) or measure current (FNMI).
The PPMU can force or measure a voltage range of 22.5 V. It
can force or measure currents ranging up to 64mA per channel
using the internal amplifier, while the addition of an external
amplifier enables higher current ranges. On Chip are all the
DAC levels required for each PMU channel.
FORCE AMPLIFIER
The force amplifier drives the analog output FOH, which drives
a programmed current or voltage to the DUT (device under
test). Headroom and footroom requirements for this amplifier
is 3V on either end. An additional ±1V is dropped across the
sense resistor when maximum current is flowing through it.
This amplifier is designed to drive DUT capacitances up to
10nF, with a compensation value of 100pF. Larger DUT
capacitive load will require larger compensation capacitances.
Local feedback ensures the amplifiers are stable when disabled.
A disabled channel reduces power consumption by
2.5mA/channel.
COMPARATORS
Per channel, the DUT measured value is monitored by two
comparators configured as window comparators. Internal DAC
levels set the CPL and CPH (low and high) threshold values.
There are no restrictions on the voltage settings of the
comparator high and lows. CPL going higher than CPH is not a
useful operation; however, it will not cause any problems to the
device. CPOL and CPOH are continuous time comparator
outputs.
comparator output available CPO (0-3) provides information
on whether the measured voltage or current is inside or outside
the set CPH and CPL window. Information of whether the
measurement was high or low is available via the serial
interfaces (Comparator Status Register).
Table 8. Comparator Output Function using LVDS interface
TEST CONDITION
CPO Output
CPL < VDUT And IDUT < CPH
1
CPL > VDUT or IDUT > CPH
0
CLAMPS
Current and voltage clamps are included on chip per PMU
channel. They protect the DUT in the event of an open or a
short. Internal DAC levels set the CLL and CLH (low and high)
levels and the clamps work to limit the force amplifier in the
event of a voltage or current at the DUT exceeding the set levels.
The clamps also function to protect the DUT when a transient
voltage or current spike occurs when changing to a different
operating mode or when programming the device to a different
current range.
The voltage clamps are active while forcing current and the
current clamps are active while forcing voltage. By default, the
current clamps are off. Simply set them up via the status register
through the serial interface. The voltage clamps are always
active in FI mode.
If a clamp level has been hit, this will be flagged via the CGALM
open drain output and the resulting alarm information may be
read back via the SPI or LVDS interface. CLL should never be
greater than CLH.
Table 7. Comparator Output Function
TEST CONDITION
CPOL
CPOH
VDUT or IDUT > CPH
0
VDUT or IDUT < CPH
1
VDUT or IDUT > CPL
1
VDUT or IDUT < CPL
0
CPH > VDUT or IDUT > CPL
1
1
When using SPI interface, full comparator functionality is
available. When using the LVDS interface, the comparator
function is limited to one output per comparator, due to the
large pin count requirement of the LVDS interface. In this case,
Rev. PrM | Page 19 of 48
AD5522
Preliminary Technical Data
CURRENT RANGE SELECTION
HIGH CURRENT
BUFFER
EN
EXTFOH
Integrated thin film resistors minimize external components
and allow easy selection of current ranges from 5 µA (200kΩ),
20μA (50kΩ), 200μA (5kΩ) and 2mA (500Ω). Per channel, one
current range up to 64mA may be accommodated by
connecting an external sense resistor. For current ranges in
excess of 64mA, it is recommended an external amplifier be
used.
CFF
INTERNAL RANGE SELECT
(5uA, 20uA, 200uA, 2mA)
FIN
+
DAC
FOH
-
Rsense
EXTMEASIH
OFFSET DAC
BIAS TO
CENTER
IRANGE
+
+
x5 or x10
MEASOUT
x1/x0.2
VFIN
FI =
RSENSE × Gain
Where:
FI = Forced Current
VFIN = Voltage of the FIN DAC, See VOUT for DAC levels.
RSENSE = Selected Sense Resistor
Gain of Current Measure Instrumentation amplifier, it may be
set (via the serial interface) to 5 or 10.
Using the 5kΩ sense resistor and ISENSE gain of 10, the
maximum current range possible is ±225μA. Similarly for the
other current ranges, there is an over range of 12.5% to allow for
correction.
Also, the forced current range will only be the quoted full scale
range with an applied reference of 5V or 2.5V (with ISENSE
AMP gain = 5). The ISENSE amplifier is biased by the Offset
DAC output voltage, in such as way as to center the Measure
current output irrespective of the voltage span used.
EXTMEASIL
+
-
-
MEASVH
AGND
For the suggested current ranges, the maximum voltage drop
across the sense resistors is ±1V, however, to allow for
correction of errors, there is some over range available in the
current ranges. The full-scale voltage range that can be loaded
to the DAC is ±11.5V; the forced current may be calculated as
follows:
Rsense
10kΩ
+
DUT
+
DUTGND
x1
+
-
-
Figure 19. Addition of high current amplifier for wider current range(>64mA)
DEVICE UNDER TEST GROUND (DUTGND)
By default, there is one DUTGND input available for all four
PMU channels. In some applications of a PMU, it is necessary
that each channel operate from its own DUTGND level.
Therefore the shared pin GUARDIN(0-3)/DUTGND(0-3) may
be configured as either the input to the GUARD amplifier
(GUARDIN), or as a DUTGND per channel function.
This may be configured through the serial interface on power
on as per required operation. The default connection is SW13b
(GUARDIN) and SW14b (DUTGND PER DEVICE).
When configured as DUTGND per channel, this multifunction
pin is no longer connected to the input of the guard amplifier,
instead it is connected to the low end of the instrumentation
amplifier (SW14a), and the input of the Guard amplifier is now
connected internally to MEASVH (SW13a).
MEASVH (0-3)
+
AGNDx
HIGH CURRENT RANGES
With the use of an external high current amplifier, one high
current range in excess of 64mA is possible. The high current
amplifier simply buffers the force output and provides the drive
for the required current.
Rev. PrM | Page 20 of 48
SW 16
SW 13
+
b
x1
+
-
-
When using the EXTFOHx outputs for current ranges up to
64mA, there is no switch in series with the EXTFOHx line,
ensuring minimum capacitance presented at the output of the
force amplifier. This is also an important feature if using a Pin
electronics driver to provide high current ranges.
a
GUARD AMP
MEASURE
VOLTAGE
IN AMP
GUARD (0-3)
a
SW 14
b
GUARDIN (0-3)/
DUTGND (0-3)
a
DUTGND
Figure 20. Using the DUTGND per channel Feature
DUT
Preliminary Technical Data
AD5522
GUARD AMPLIFER
COMPENSATION CAPACITORS
A Guard amplifier allows the user to bootstrap the shield of the
cable to the voltage applied to the DUT, ensuring minimal
drops across the cable. This is particularly important for
measurements requiring a high degree of accuracy and in
leakage current testing.
Each channel requires an external compensation capacitor
(CCOMP) to ensure stability into the maximum load capacitance
while ensuring settling time is optimized. In addition, one CFF
pin is provided to further optimize stability and settling time
performance when in Force voltage mode. When changing
from Force current to force voltage mode, the switch
connecting CFF capacitor is automatically closed. While the
force amplifier is designed to drive load capacitances up to 10nF
(with Ccomp = 100pF), using larger compensation capacitor
values, it is possible to drive larger load at the expense of an
increase in settling time. If a wide range of load capacitance
must be driven, then an external multiplexer connected to the
CCOMP pin will allow optimization of settling time versus
stability. The series resistance of a switch placed on CCOMP,
should typically be <50Ω.
If not required, all four Guard Amplifiers may be disabled via
the serial interface (through the System Control Register), this
decreases the power consumption by 400uA per channel.
As described in the DUTGND section, the GUARDIN(0-3)
/DUTGND(0-3) is a shared pin. It can function either as a
guard amplifier input per channel or as a DUTGND input per
channel as required by the end application. Refer to Figure 20.
A Guard alarm event occurs when the guard output moves
more than 100mV away from the Guard input voltage for more
than 200μs. In the event this happens, this will be flagged via
the CGALM open drain output. As the guard and clamp alarm
functions share the same alarm outputCGALM, the alarm
information (alarm trigger and alarm channel) is available via
the serial interface (ALARM STATUS REGISTER).
Alternatively, the serial interfaces allow the user to setup the
CGALM output to flag either the clamp status or the guard
status. By default, this open drain alarm pin is an unlatched
output, but may be set to a latched output via the serial
interface, System Control Register.
Similarly, connecting the CFF node to a multiplexer externally,
would cater for a wide range of CDUT in Force Voltage mode.
The series resistance of the multiplexer used should be such
that:
1
⎛
⎜
2
RON
Π
× CDUT
⎝
⎞
⎟ > 100kHz
⎠
Table 9. Suggested Compensation Capacitor Selection
CLOAD
CCOMP
CFF
≤1nF
100pF
220pF
≤10nF
100pF
1nF
≤100nF
CLOAD/100
CLOAD/10
Rev. PrM | Page 21 of 48
AD5522
Preliminary Technical Data
SYSTEM FORCE SENSE SWITCHES
MEASURE OUTPUT (MEASOUT)
Each channel has switches to allow connection of the force
(FOHx) and sense (MEASVHx) lines to a central PMU for
calibration purposes. There is one set of SYS_FORCE and
SYS_SENSE pins per device. For calibration purposes, it is
recommended the SYS_FORCE path be connected individually
to each PMU channel, FOH path.
The measured DUT voltage or current (voltage representation
of DUT current) is available on MEASOUT (0-3) with respect
to AGND. The default MEASOUT range is the forced voltage
range for voltage measure and current measure (nominally
±11.25V, depends on reference voltage and offset DAC) and
includes some over range to allow for offset correction. The
serial interface allows the user to select another MEASOUT
range of VREF to AGND, allowing for a smaller input range ADC
to be used. Each PMU channel MEASOUT line may be made
high impedance via the serial interface.
TEMPERATURE SENSOR
An on board temperature sensor monitors temperatures and in
the event of the temperature exceeding a factory defined value,
(130°C) or a user programmable value, the device will protect
itself by shutting down all channels and will flag an alarm
through the latched open drain TMPALM pin. Alarm status
may be readback from the Alarm Status Register or the PMU
registers where latched and unlatched bits tell if an alarm has
occurred and whether the temperature has dropped below the
set alarm temperature.
When using low supply voltages, ensure that there is sufficient
headroom and footroom for the required force voltage range.
The Offset DAC also directly offsets the MEASURE output
voltage level, but only when GAIN1 = 0.
Table 10. MEASOUT Output Ranges
MEASOUT Function
GAIN1 = “0”VREF = 5V
GAIN1 = “1”
MEASOUT Gain = 1
±VDUT (up to 11.25V)
MEASOUT Gain = 1/5
MV
±VRSENSE X 10 = up to ±11.25V
± VRSENSE X 5 = up to ±5.625
0 to 4.5V
0 to 2.25V
MI
GAIN0 = “0”
GAIN0 = “1”
CURRENT MEAS GAIN = 10
CURRENT MEAS GAIN = 5
Rev. PrM | Page 22 of 48
0 to
4.5VREF
5
Preliminary Technical Data
AD5522
DAC LEVELS
Each channel contains five dedicated DAC levels : one for the
force amplifier, one each for the clamp high and low levels and
one each for the comparator high and low levels.
The architecture of a single DAC channel consists of a 16-bit
resistor-string DAC followed by an output buffer amplifier. This
resistor-string architecture guarantees DAC monotonicity. The
16-bit binary digital code loaded to the DAC register
determines at what node on the string the voltage is tapped off
before being fed to the output amplifier.
The transfer function for DAC outputs is:
Therefore, depending on headroom available, the input to the
Force Amplifier may be unipolar positive, or bipolar, either
symmetrical or asymmetrical about DUTGND but always
within a voltage span of 22.5V.
The offset DAC offsets all DAC functions. It also centers the
current range, such that zero current always flows at midscale
code irrespective of offset DAC setting.
Rearranging the transfer function for the DAC output gives the
following equation to determine what Offset DAC code is
required for a given reference and output voltage range.
⎛ 216 (VOUT − DUTGND) ⎞ ⎛ 4.5 × DACCODE ⎞
⎟⎟ − ⎜
OFFSETDAC ⋅CODE = ⎜⎜
⎟
3.5VREF
3.5
⎠
⎠ ⎝
⎝
⎛ OFFSETDAC ⋅CODE ⎞
⎛ DACCODE ⎞
VOUT = 4.5VREF ⎜
⎟ + DUTGND
⎟ − 3.5VREF ⎜
216
216
⎠
⎝
⎠
⎝
OFFSET AND GAIN REGISTERS
Where the voltage range must be take into account the +/-4V
headroom and footroom requirements for the amplifier and
sense resistor and must be within the range -16.25V to 22.5V
(22V range + 500mV overrange to allow for correction).
OFFSET DAC
The device is capable of forcing a 22.5V (4.5 × VREF) voltage
range. Included on chip is one 16 Bit offset DAC (one for all
four channels) which allows for adjustment of the voltage range.
The useable range is -16.25V to 22.5V. Zero scale gives a fullscale range of 0V to +22.5V, mid scale gives ±11.25V, while the
most negative useful range is in a range of -16.25V to 6.25V.
Full scale loaded to the Offset DAC does not give a useful
output voltage range as the output amplifiers are limited by
available footroom. The following table shows the effect of the
Offset DAC on the other DACs in the device.
Table 11. OFFSET DAC Relationship with other DACs with
VREF = 5V
Offset DAC
Code
0
0
0
DAC Code
DAC Output Voltage Range
0
32768
65535
0.00 V
11.25 V
22.50 V
32768
32768
32768
0
32768
65535
-8.75 V
2.50 V
13.75 V
42130
42130
42130
0
32768
65535
-11.25 V
0.00 V
11.25 V
60855
60855
60855
0
32768
65535
-16.25
-5.00
6.25
65535
-
Footroom Limitations
Each DAC level contains independent offset and gain control
registers that allow the user to digitally trim offset and gain.
These registers give the user the ability to calibrate out errors in
the complete signal chain, including the DAC, using the
internal m and c registers, which hold the correction factors. All
registers in the AD5522 are volatile, so need to be loaded on
power on during a calibration cycle.
The digital input transfer function for each DAC can be
represented as
x2 = [(m + 1)/ 2n × x1] + (c – 2n – 1)
where:
x2 = the data-word loaded to the resistor string DAC.
x1 = the 16-bit data-word written to the DAC input register.
m = code in gain register (default code = 216 – 1.)
c = code in offset register (default code = 215)
n = DAC resolution (n = 16).
The calibration engine is only engaged when data is written to
the x1 register. This has the advantage of minimizing the setup
time of the device.
CACHED X2 REGISTERS
Each DAC has a number of cached x2 values. These registers
store the result of an offset and gain calibration in advance of a
mode change. This enables the user to preload registers; allow
the calibration engine to calculate the appropriate x2 value and
store until ready to change modes. As the data is ready and held
in the appropriate register, this enables mode changing be as
time efficient as possible. If an update occurs to a DAC register
set that is currently part of the operating PMU mode, the DAC
output will update immediately (depending on LOAD
condition).
Rev. PrM | Page 23 of 48
AD5522
Preliminary Technical Data
Offset and Gain registers for the FIN DAC
VREF
The FIN (force amplifier input) DAC level contains
independent offset and gain control registers that allow the user
to digitally trim offset and gain. There are six sets of x1, m and c
registers, one set (x1, m and c) for the force voltage range, and
one set for each of the force current ranges (4 internal current
ranges and 1 external current range). Six x2 registers store
calculated DAC values ready to load to the DAC register on a
mode change.
One buffered analog input supplies all 20 DACs with the
necessary reference voltage to generate the required DC levels.
OFFSET DAC
VREF
16
16
16
X1 REG
M REG
C REG
16
FIN
16-Bit
FIN DAC
X2 REG
*6
Serial I/F
Figure 21. FIN DAC Registers
Offset and Gain registers for the COMPARATOR DACs
The Comparator DAC levels contain independent offset and
gain control registers that allow the user to digitally trim offset
and gain. There are six sets of (x1, m and c) registers, one set for
the voltage mode, and one set for each of the four internal
current ranges and one set for the external current range. In this
way, x1 may also be preprogrammed, so switching different
modes, allows for efficient switching into the required compare
mode. Six x2 registers store cached calculated DAC values ready
to load to the DAC register on a mode change.
16
16
X1 REG
M REG
C REG
16
VREF
16
X2 REG
16-Bit
CPH DAC
CPH
*6
16
16
X1 REG
M REG
C REG
16
Serial I/F
16
X2 REG
CPL
16-Bit
CPL DAC
Figure 22. Comparator Registers
Offset and Gain registers for the Clamp DACs
The clamp DAC levels contain independent offset and gain
control registers that allow the user to digitally trim offset and
gain. There are just two sets of registers, one for the voltage
mode and another register set (x1, m and c) for all five current
ranges. Two x2 registers store cached calculated DAC values
ready to load to the DAC register on a PMU mode change.
16
X1 REG
M REG
C REG
16
16
16
16-Bit
CLH DAC
CLH
16
16-Bit
CLL DAC
CLL
X2 REG
16
X1 REG
M REG
C REG
16
16
X2 REG
The voltage applied to the VREF pin determines the output
voltage range and span applied to the force amplifier, clamp and
comparator inputs. This device can be used with a reference
input ranging from 2V to 5V, however, for most applications, a
reference input of 5V or 2.5V will be sufficient to meet all
voltage range requirements. The DAC amplifier gain is 4.5,
which gives a DAC output span of 22.5V. The DACs have offset
and gain registers which can be used to calibrate out system
errors.
In addition, the gain register can be used to reduce the DAC
output range to the desired force voltage range. The Force DAC
will retain 16 bit resolution even with a gain register setting of
quarter scale (0x4000). Therefore, from a single 5V reference, it
is possible to get a voltage span as high as 22.5V or as low as
5.625V all from one 5V reference.
When using the offset and gain registers, the chosen output
range should take into account the system offset and gain errors
that need to be trimmed out. Therefore, the chosen output
range should be larger than the actual, required range.
When using low supply voltages, ensure that there is sufficient
headroom and footroom for the required force voltage range.
Also, note that with a supply differential of less than 18V and a
full scale current range requirement, it is necessary to reduce
the current measure in amp gain to 5 so the feedback path can
swing through the full range.
Also, the forced current range will only be the quoted full scale
range with an applied reference of 5V or 2.5V (with ISENSE
AMP gain = 5).
*6
VREF
REFERENCE SELECTION
For other voltage/current ranges, the required reference level
can be calculated as follows:
1.
Identify the nominal range required
2.
Identify the maximum offset span and the maximum
gain required on the full output signal range.
3.
Calculate the new maximum output range including
the expected maximum offset and gain errors.
4.
Choose the new required VOUTmax and VOUTmin,
keeping the VOUT limits centered on the nominal
values. Note that AVDD and AVSS must provide
sufficient headroom.
5.
Calculate the value of VREF as follows:
VREF = (VOUTMAX – VOUTMIN)/4.5
Serial I/F
Figure 23. Clamp Registers
Rev. PrM | Page 24 of 48
Preliminary Technical Data
AD5522
Reference Selection Example
12/12.26× 65535 = 64145
Nominal Output Range = 10V (-2V to +8V)
Offset Error = ±100mV
Gain Error = ±0.5%
REFGND = AGND = 0V
Example 1: Gain Error = +0.5%, Offset Error = +100mV
1) Gain Error (0.5%) Calibration: 63937 × 0.995 = 63617
=> Load Code “0b1111 1000 1000 0001” to m register
2) Offset Error (100mV) Calibration:
LSB Size = 10.25/65535 = 156 µV;
Offset Coefficient for 100mV Offset = 100/0.156 = 641 LSBs
=> Load Code “0b0111 1101 0111 1111” to c register
1)
Gain Error = ±0.5%
=> Maximum Positive Gain Error = +0.5%
=> Output Range incl. Gain Error
= 10 + 0.005(10)=10.05V
2)
Offset Error = ±100mV
=> Maximum Offset Error Span = 2(100mV)=0.2V
=> Output Range including Gain Error and Offset Error =
10.05V + 0.2V = 10.25V
3)
VREF Calculation
Actual Output Range = 10.25V, that is -2.125V to +8.125V
(centered);
VREF = (8.125V + 2.125V)/4.5 = 2.28V
SYSTEM LEVEL CALIBRATION
There are many ways to calibrate the device on power on. The
following gives an example of how to calibrate the FIN DAC of
the device without a DUT or DUT board connected.
Calibration Procedure for Force and Measure circuitry:
1)
Calibrate Force Voltage (2 point)
Write zero scale to the Force DAC (FIN), connect
SYS_FORCE to FOHx and SYS_SENSE to MEASVHx,
close the internal Force/Sense Switch (SW 7). Using the
System PMU, measure the error between voltage at FOHx,
MEASVHx and desired value.
Similarly, load Full scale to the Force DAC, and measure
the error between FOHx , MEASVH and the desired value.
Work out m and c values. Load these values to appropriate
m and c registers for Force DAC.
2)
Calibrate Measure Voltage (2 point)
Connect SYS_FORCE to FOH, SYS_SENSE to MEASVHx
Close Internal Force/Sense switch (SW 7). Force voltage on
FOH via SYS_FORCE and measure voltage at MEASOUT.
The difference is the error between the actual forced
voltage and the voltage at MEASOUT.
3)
Calibrate Force current (2 point)
In Force current mode, write zero and fullscale to the Force
DAC. Connect SYS_FORCE to external ammeter and to
FOH pin. Measure error on zero and fullscale current and
calculate m and c values.
4)
Calibrate Measure Current (2 Point)
Write zero scale to the Force DAC in Force Current mode.
Connect SYS_FORCE to an external ammeter and to the
FOH pin. Measure the error between ammeter reading and
MEASOUT reading. Repeat with Full scale loaded to the
Force DAC.
5)
Repeat for all four channels.
If the solution yields an inconvenient reference level, the user
can adopt one of the following approaches:
1.
Use a resistor divider to divide down a convenient,
higher reference level to the required level.
2.
Select a convenient reference level above VREF and
modify the Gain and Offset registers to digitally
downsize the reference. In this way the user can use
almost any convenient reference level.
3.
Use a combination of these two approaches
In this case, the optimum reference to choose is a 2.5V
reference, then use the m and c registers and the OFFSET DAC
to achieve the required -2V to +8V range. The ISENSE
amplifier gain should be changed to a gain of 5. This ensures a
full scale current range of the specified values and also allows
optimization of power supplies and minimizes power
consumption within the device.
CALIBRATION
The user can perform a system calibration by overwriting the
default values in the m and c registers for any individual DAC
channels as follows:
Calculate the nominal offset and gain coefficients for the new
output range (see previous example)
Calculate the new m and c values for each channel based on
the specified offset and gain errors
Calibration Example
Nominal Offset Coefficient = 32768
Nominal Gain Coefficient = 10/10.25x 65535 = 63937
Similarly, calibrate the comparators and clamp DACs and load
the appropriate gain and offset registers. Calibrating these
DACs will require some successive approximation to find where
the comparator trips or the clamps engage.
Rev. PrM | Page 25 of 48
AD5522
Preliminary Technical Data
CIRCUIT OPERATION
FORCE VOLTAGE, FV
Most PMU measurements are performed while in force voltage
and measure current mode, for example, when the device is
used as a device power supply, or in continuity or leakage
testing. In the force voltage mode, the voltage forced is mapped
directly to the DUT. The voltage measure amplifier completes
the loop giving negative feedback to the forcing amplifier. See
Figure 24.
Forced Voltage at DUT = VFIN
Where:
VFIN = Voltage of the FIN DAC, See VOUT for DAC levels.
EXTFOH
CFF
INTERNAL RANGE SELECT
(5uA, 20uA, 200uA, 2mA)
FIN
+
DAC
FOH
-
Rsense
EXTMEASIH
OFFSET DAC
BIAS TO
CENTER
IRANGE
+
-
MEASOUT
x1/x0.2
-
Rsense
up to
(64mA)
10kΩ
+
x5 or x10
+
-
EXTMEASIL
MEASVH
AGND
+
DUT
+
DUTGND
x1
-
+
-
Figure 24. Forcing voltage, measuring current
Rev. PrM | Page 26 of 48
Preliminary Technical Data
AD5522
FORCE CURRENT, FI
In the force current mode, the voltage at FIN is now converted
to a current and applied to the DUT. The feedback path is now
the current measure amplifier, feeding back the voltage
measured across the sense resistor and MEASOUT reflects the
voltage measured across the DUT. See Figure 25.
For the suggested current ranges, the maximum voltage drop
across the sense resistors is ±1V, however, to allow for
correction of errors, there is some over range available in the
current ranges. The maximum full-scale voltage range that can
be loaded to the FIN DAC is ±11.5V; the forced current may be
calculated as follows:
FI =
VFIN
RSENSE × Gain
Where:
FI = Forced Current
VFIN = Voltage of the FIN DAC, See VOUT for DAC levels.
RSENSE = Selected Sense Resistor
Gain of Current Measure Instrumentation amplifier, it may be
set (via the serial interface) to 5 or 10.
The ISENSE amplifier is biased by the Offset DAC output
voltage, in such as way as to center the Measure current output
irrespective of the voltage span used.
Using the 5kΩ sense resistor and ISENSE gain of 10, the
maximum current range possible is ±225μA. Similarly for the
other current ranges, there is an over range of 12.5% to allow for
correction.
EXTFOH
CFF
INTERNAL RANGE SELECT
(5uA, 20uA, 200uA, 2mA)
FIN
+
DAC
FOH
-
Rsense
EXTMEASIH
OFFSET DAC
BIAS TO
CENTER
IRANGE
+
-
MEASOUT
x1/x0.2
-
Rsense
up to
(64mA)
10kΩ
+
x5 or x10
+
-
EXTMEASIL
MEASVH
AGND
+
DUT
+
DUTGND
x1
-
+
-
Figure 25. .Forcing current, measuring voltage
Rev. PrM | Page 27 of 48
AD5522
Preliminary Technical Data
The AD5522 contains two high-speed serial interfaces, an SPI
compatible, interface operating at clock frequencies up to
50MHz, and an EIA-644-compliant, LVDS interface. To
minimize both the power consumption of the device and onchip digital noise, the interface powers up fully only when the
device is being written to, that is, on the falling edge of SYNC.
the section Power On Default). This sequence takes approx
300µs. The falling edge of RESET initiates the reset process;
BUSY goes low for the duration, returning high when RESET is
complete. While BUSY is low, all interfaces are disabled. When
BUSY returns high, normal operation resumes and the status of
the RESET pin is ignored until it goes low again. The SDO
output will be high impedance during a power on reset or a
RESET.
SPI INTERFACE
Power on reset follows the same function as RESET.
The serial interface operates over a 2.3V to 5.25V DVCC supply
range. The serial interface is controlled by four pin, as follows:
BUSY AND LOAD FUNCTION
SYNC Frame synchronization input.
BUSY is an open drain output that indicates the status of the
AD5522 interface. When writing to any of the registers BUSY
goes low and stays low until the command completes.
SERIAL INTERFACE
SDI Serial data input pin.
SCLK Clocks data in and out of the device.
SDO Serial data output pin for data readback purposes.
There is also an SPI/LVDS select pin, which must be held low
for SPI interface and high for LVDS interface.
LVDS INTERFACE
The LVDS interface uses the same input pins as the SPI
interface with the same designations. In addition, three other
pins are provided for the complementary signals needed for
differential operation, thus:
SYNC/SYNC Differential frame synchronization signal.
Writing to a DAC register drives the BUSY signal low for longer
than a simple PMU or System Control Register write. For the
DACs, the value of the internal cached (x2) data is calculated
and stored each time the user writes new data to the
corresponding x1 register. During this write and calculation, the
BUSY output is driven low. While BUSY is low, the user can
continue writing new data to the x1, m, or c registers, but no
output updates can take place.
X2 values are stored and held until a PMU word is written that
calls the appropriate cached x2 register. Only then does a DAC
output update.
The DAC outputs and PMU modes are updated by taking the
LOAD input low. If LOAD goes low while BUSY is active, the
LOAD event is stored and the DAC outputs or PMU modes
update immediately after BUSY goes high. A user can also hold
the LOAD input permanently low. In this case, the change in
DAC outputs or PMU modes update immediately after BUSY
goes high.
SDI/SDI Differential serial data input.
SCLK/SCLK Differential clock input.
SDO/SDO Serial data output pin for data readback
SERIAL INTERFACE WRITE MODE
The AD5522 allows writing of data via the serial interface to
every register directly accessible to the serial interface, which is
all registers except the DAC registers.
The serial word is 29 bits long. The serial interface works with
both a continuous and a burst (gated) serial clock. Serial data
applied to SDI is clocked into the AD5522 by clock pulses
applied to SCLK. The first falling edge of SYNC starts the write
cycle. At least 29 falling clock edges must be applied to SCLK to
clock in 29 bits of data, before SYNC is taken high again.
The input register addressed is updated on the rising edge of
SYNC. In order for another serial transfer to take place, SYNC
must be taken low again.
The BUSY pin is bidirectional and has a 50 kΩ internal pullup
resistor. Where multiple AD5522 devices may be used in one
system, the BUSY pins can be tied together. This is useful where
it is required that no DAC or PMU in any device is updated
until all others are ready. When each device has finished
updating the x2 registers, it will release the BUSY pin. If
another device has not finished updating its x2 registers, it will
hold BUSY low, thus delaying the effect of LOAD going low.
As there is only one multiplier shared between four channels,
this task must be done sequentially, so the length of the BUSY
pulse will vary according to the number of channels being
updated.
RESET FUNCTION
Bringing the level sensitive RESET line low resets the contents
of all internal registers to their power-on reset state (detailed in
Rev. PrM | Page 28 of 48
Preliminary Technical Data
AD5522
Table 12. BUSY Pulse Width
REGISTER UPDATE RATES
Action
BUSY Pulse Width
(μs max)
Loading data to PMU, System Control
Register or Readback
0.27
Loading x1 to any 1 PMU DAC Channel
1.25
Loading x1 to any 2 PMU DAC Channels
1.75
Loading x1 to any 3 PMU DAC Channels
2.25
Loading x1 to any 4 PMU DAC Channels
2.75
As mentioned previously the value of the X2 register is
calculated each time the user writes new data to the
corresponding X1 register. The calculation is performed by a
three stage process. The first two stages take 500ns each and the
third stage takes 250ns. When the writes to one of the X1
registers is complete the calculation process begins. If the write
operation involves the update of a single DAC channel the user
is free to write to another register provided that the write
operation doesn’t finish until the first stage calculation is
complete, i.e. 500ns after the completion of the first write
operation.
BUSY Pulse Width = ((Number of channels +1) × 500ns) + 250ns
Calibration Engine Time
BUSY also goes low during power-on reset and when a falling
edge is detected on the RESET pin.
~600ns
WRITE
#1
WRITE
#1
500ns
1st
STAGE
500ns
250ns
2nd
STAGE
3rd
STAGE
1st
STAGE
1st
STAGE
WRITE
#2
Calibration Engine Time
~600ns
500ns
2nd
STAGE
1st
STAGE
WRITE
#2
500ns
250ns
2nd
STAGE
3rd
STAGE
1st
STAGE
WRITE
#3
3rd
STAGE
2nd
STAGE
1st
STAGE
e.g. WRITE TO
3 FIN DAC REGISTERS
1st
STAGE
3rd
STAGE
2nd
STAGE
3rd
STAGE
Figure 27. Multiple Single Channel writes engaging calibration engine
3rd
STAGE
2nd
STAGE
2nd
STAGE
3rd
STAGE
Figure 26. Multiple writes to DAC x1 registers
Writing data to the System control register, PMU control
register, m or c registers do not involve the digital calibration
engine, thus speeding up configuration of the device on power
on.
Rev. PrM | Page 29 of 48
AD5522
Preliminary Technical Data
REGISTER SELECTION
PMU Address Bits, PMU3, PMU2, PMU1, PMU0
The serial word assignment consists of 29 bits. Bits 28 through
to 22 are common to all registers, whether writing to or reading
from the device. PMU3 to PMU0 data bits address each PMU
channel (or associated DAC register). When PMU3 to PMU0
are all zeros, the System Control Register is addressed. Mode
Bits MODE0 and MODE1 address the different sets of DAC
registers and the PMU register.
Bits PMU3 through PMU0 address each of the PMU channels
on chip. This allows individual control of each PMU channel or
any manner of combined addressing in addition to multi
channel programming. PMU bits also allow access to write
registers such as the System Control Register and the many
DAC registers, in addition to reading from all the registers.
Table 13. Mode Bits
B23
MODE1
0
0
1
1
Readback Control, RD/WR
The R/W bit set high initiates a readback sequence of PMU,
Alarm, Comparator, System Control Register or DAC
information as determined by address bits.
B22
MODE0
0
1
0
1
WRITE FUNCTION
Action
System Control Register or PMU Register
DAC Gain (m) Register
DAC Offset (c) Register
DAC Input Data Register, (x1)
Table 14. Read and Write Functions of the AD5522
B28
RD/WR
B27
PMU3
B26
PMU2
WRITE FUNCTIONS
0
0
0
B25
PMU1
B24
PMU0
B23
MODE1
B22
MODE0
B21 to B0
DATA BITS
0
0
0
0
DATA BITS
0
0
0
0
0
0
1
DATA BITS
0
0
0
0
0
1
0
DATA BITS
0
0
0
0
0
1
1
11 1111 1111 1111 1111 1111b
0
0
0
0
0
1
1
DATA BITS other than all 1’s
WRITE ADDRESSED DAC OR PMU REGISTER
0
0
0
0
1
Select DAC or PMU Registers.
DATA BITS
See Table 13
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
1
1
1
1
READ FUNCTIONS
1
0
0
0
0
0
0
All zeros
1
0
0
0
0
0
1
All zeros
1
0
0
0
0
1
0
X
1
0
0
0
0
1
1
All zeros
READ ADDRESSED DAC or PMU REGISTER – Can only read one PMU or DAC register at one time.
1
0
0
0
1
PMU/DAC REGISTER ADDRESS DAC ADDRESS SEE
1
0
0
1
0
SEE Table 13
Table 21
1
0
1
0
0
1
1
0
0
0
SELECTED REGISTER
CH3
CH2
CH1
CH0
Write to System Control Register (Table 16)
RESERVED
RESERVED
NOP (No Operation)
RESERVED
×
×
×
×
CH3
CH3
CH3
×
×
×
CH2
×
CH2
CH2
×
CH1
CH1
×
×
CH1
CH1
CHO
×
CH0
×
×
×
CH0
Read from System Control Register
Read from Comparator Status Registers
Reserved
Read from Alarm Status Register
×
×
×
CH3
×
×
CH2
×
×
CH1
×
×
CH0
×
×
×
NOP (No Operation)
If a NOP (No Operation) command is loaded, no change is made to DAC or PMU registers. This code is useful when performing a read
back of a register within the device (via the SDO pin) where a change of DAC code or PMU function may not be required
Reserved Commands
Any bit combination that is not described in the Register address tables for the PMU, DAC and System Control Registers are Reserved
commands. These commands are unassigned commands; they are reserved for factory use. To ensure correct operation of the device, do
not used reserved commands.
Rev. PrM | Page 30 of 48
Preliminary Technical Data
AD5522
WRITE SYSTEM CONTROL REGISTER
The System Control Register is accessed when the PMU channel address PMU3-PMU0 and Mode Bits, MODE1 and MODE0 are all
zeros. It allows quick setup of different functions within the device. The System Control Register operates on a per device basis.
CPBIASEN
DUTGND/CH
GUARD ALM
B8
B7
B6
B5
B4
B3
B2
B1/0
0
CPOLH0
B9
LATCHED
CPOLH1
B10
TMP0
B11
TMP1
B12
TMP ENABLE
B13
GAIN0
B14
GAIN1
B15
GUARD EN
B16
INT10K
B17
CLAMP ALM
B18
CPOLH2
B19
CPOLH3
CL3
B20
CL0
B21
CL1
B22
CL2
B23
MODE0
B24
MODE1
B25
PMU0
PMU3
B26
PMU1
B27
PMU2
B28
RD/WR
Table 15. System Control Register Bits
Table 16. System Control Register Functions
Bit
28
(MSB)
Bit name
RD/WR
27
26
25
24
PMU3
PMU2
PMU1
PMU0
Description
When low, a write function takes place to the selected register, while if the RD/WR bit is set high, this initiates a readback sequence
of PMU, Alarm, Comparator, System Control or DAC register as determined by address bits.
Bits PMU3 through PMU0 address each of the PMU channels in the device. If all four of these bits are set to zero, the System Control
Register is addressed.
B27
B26
B25
B24
B23
B22
SELECTED REGISTER
PMU3 PMU2 PMU1 PMU0 MODE1
MODE0
CH3
CH2
CH1
CH0
0
0
0
0
0
0
Write to System Control Register
×
×
CHO
0
0
0
1
Select DAC or PMU Registers. ×
See below
×
×
CH1
×
0
0
1
0
0
0
1
1
1
23
22
MODE1
MODE0
0
1
0
1
1
1
0
0
1
1
1
0
0
0
1
×
×
CH1
×
CH2
×
CH0
×
-
-
-
-
CH3
×
×
×
-
-
-
-
CH3
CH2
CH1
×
CH3
CH2
CH1
CH0
Mode Bits, MODE0 and MODE1 allow addressing of the PMU register or the DAC gain (m), offset (c ) or input register (x1). Set to
Zero to access the System Control Register.
MODE1 MODE0 Action
0
0
System Control Register or PMU Register
0
1
DAC Gain (m) Register
1
0
DAC Offset (c) Register
1
1
DAC Input Data Register, (x1)
SYSTEM CONTROL REGISTER SPECIFIC BITS
Current Clamp Enable. Bits CL3 through CL0 enable and disable the current clamp function per channel. A “0” disables, while a “1”
21
CL3
enables. The clamp enable function is also available in the PMU register on a per channel basis. This dual functionality allows
20
CL2
flexible enable or disabling of this function. When reading back information on the status of the clamp enable function, what was
19
CL1
most recently written to the current clamp register is available in the readback word from either PMU or System Control Registers.
18
CL0
The Voltage clamps (FI mode) are always enabled.
17
16
15
14
CPOLH3
CPOLH2
CPOLH1
CPOLH0
13
CPBIASEN
12
DUTGND/CH
11
10
GUARD ALM
CLAMP ALM
9
INT10K
Comparator Output Enable. By default the comparator outputs are hi-Z on power on. A “1” in each bit position enables the
comparator output for the selected channel. The CPBIASEN (Bit 13) must be enabled to power on the comparator functions. The
comparator enable function is also available in the PMU register on a per channel basis. This dual functionality allows flexible
enable or disabling of this function. When reading back information on the status of the comparator enable function, what was
most recently written to the comparator register is available in the readback word from either PMU or System Control Registers.
Comparator Enable. By default the comparators are powered down on power on. To enable the comparator function for all
channels, write a “1” to the CPBIASEN bit. A “0” disabled the comparators and shuts them down. Comparator Output Enables bits
(CPOLHx) allow the user to switch on each comparator output individually, enabling bussing of comparator outputs.
DUTGND per channel enable. The GUARDIN(0-3)/DUTGND(0-3) pins are shared pin functions and may be configured to enable a
DUTGND per PMU channel or GUARD input per PMU channel. Setting this bit to “1” enables DUTGND per channel. In this mode, this
pin now functions as a DUTGND pin on a per channel basis. The guard inputs are disconnected from this pin and instead connected
directly to the MEASVH line by an internal connection. Default power on condition is GUARDIN(0-3).
Clamp and Guard Alarm Function share one open drain CGALM alarm pin. By default, the CGALM pin is disabled. Bits GUARD ALM
and CLAMP ALM allow the user to choose if they only wish to have both or either information flagged to the CGALM pin. Set high to
enable either alarm function.
Internal Sense Short, INT10K. Setting this bit high allows the user to connect in an internal sense short resistor of 10kΩ between the
FOH and the MEASVH lines, (closes SW 7), it also closes SW 15, connecting another 10 kΩ resistor between DUTGND and AGND.
Rev. PrM | Page 31 of 48
AD5522
8
GUARD EN
7
6
GAIN1
GAIN0
Preliminary Technical Data
Guard enable. The Guard Amplifier is disabled on power on; write a “1” to enable it. Disabling the guard function if not in use saves
power (typically 400μA per Channel).
MEASOUT Output Range. The MEASOUT range defaults to the voltage force span for voltage and current measurements, this is
±11.25V, which includes some over range to allow for offset correction. The MEASOUT range may be reduced by using the GAIN0
and GAIN1 data bits. This allows for use of asymmetrical supplies and also for use of a smaller input range ADC.
GAIN1 = “0”VREF = 5V
MEASOUT Function
GAIN1 = “1”
MV
MI
GAIN0 = “0”
GAIN0 = “1”
CURRENT MEAS GAIN = 10
CURRENT MEAS GAIN = 5
MEASOUT Gain = 1
±VDUT (up to 11.25V)
MEASOUT Gain = 1/5
±VRSENSE X 10 = up to ±11.25V
± VRSENSE X 5 = up to ±5.625
0 to 4.5V
0 to 2.25V
0 to
4.5VREF
5
5
4
3
TMP ENABLE
TMP1
TMP0
Thermal Shutdown Function, TMP ENABLE, TMP1, TMP0
To disable the Thermal Shutdown feature, write a “0” to the TMP ENABLE bit (enabled by default). Bits TMP1 and TMP0 allow the
user to program the thermal shutdown temperature of operation.
TMP ENABLE TMP1 TMP0 Action
0
X
X
Thermal Shutdown Disabled
1
X
X
Thermal Shutdown Enabled
1
0
0
Shutdown at Junction Temp of 130°C
(Power On Default)
1
0
1
Shutdown at Junction Temp of 120°C
1
1
0
Shutdown at Junction Temp of 110°C
1
1
1
Shutdown at Junction Temp of 100°C
2
LATCHED
1
0
(LSB)
0
0
Configure open drain CGALM as a latched or unlatched output pin. When high, this bit sets the CGALM alarm output as latched
outputs allowing it to drive a controller I/O without having to poll the line constantly. Default condition on power on is unlatched.
Unused bits. Set to 0.
Rev. PrM | Page 32 of 48
Preliminary Technical Data
AD5522
WRITE PMU REGISTER
To address PMU functions, set Mode bits MODE1, MODE0 low, this selects the PMU register as outlined in Table 13 and Table 14. The
AD5522 has very flexible addressing, in that it allows writing of data to a single PMU channel, any combination of them or all PMU
channels. This enables multi pin broadcasting to similar pins on a DUT. Bits 27 to 24 select which PMU or group of PMUs is addressed.
Table 17. PMU Register Bits
B28
B27
B26
B25
B24
B23
B22
B21
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5 to B0
RD/WR
PMU3
PMU2
PMU1
PMU0
MODE1
MODE0
CH
EN
FORCE1
FORCE0
X
C2
C1
C0
MEAS1
MEAS0
FIN
SF0
SF0
CL
CPOLH
COMPARE
V/I
CLEAR
UNUSED
DATA
BITS
Table 18. PMU Register Functions
Bit
28
(MSB)
Bit name
RD/WR
27
26
25
24
PMU3
PMU2
PMU1
PMU0
Description
When low, a write function takes place to the selected register, while if the RD/WR bit is set high, this initiates a readback
sequence of PMU, Alarm, Comparator, System Control or DAC register as determined by address bits.
Bits PMU3 through PMU0 address each of the PMU channels in the device. This allows individual control of each PMU channel
or any manner of combined addressing in addition to multi-channel programming.
B27
B26
B25
B24
B23
B22
SELECTED REGISTER
PMU3 PMU2 PMU1 PMU0 MODE1
MODE0
CH3
CH2
CH1
CH0
0
0
0
0
0
0
Write to System Control Register
×
×
CHO
Select DAC or PMU Registers. ×
0
0
0
1
×
×
CH1
×
See below
0
0
1
0
0
0
1
1
1
23
22
MODE1
MODE0
0
1
0
1
1
1
0
0
1
1
1
0
0
0
1
×
×
CH1
CH0
×
CH2
×
×
-
-
-
-
CH3
×
×
×
-
-
-
-
CH3
CH2
CH1
×
CH3
CH2
CH1
CH0
Mode Bits, MODE0 and MODE1 allow addressing of the PMU register or the DAC gain (m), offset (c ) or input register (x1). Set
to zero to access the PMU Register.
MODE1 MODE0 Action
0
0
System Control Register or PMU Register
0
1
DAC Gain (m) Register
1
0
DAC Offset (c) Register
1
1
DAC Input Data Register, (x1)
PMU REGISTER SPECIFIC BITS
21
CH EN
Channel Enable, Set high to enable the selected channel, similarly, set low to disable a selected channel or group of channels.
When disabled, SW 2 is closed, SW 5 open.
20
FORCE1
Bits FORCE1 and FORCE0 address the force function for each of the PMU channels (in association with P3-P0). All
combinations of forcing and measuring (using MEAS0 and MEAS1) are available. The Hi-Z (voltage and current) modes allows
19
FORCE0
user to optimize glitch response during mode changes. While in these modes, with PMU Hi-Z, new x1 codes loaded to the FIN
DAC register and the Clamp DAC register will be calibrated, stored in x2 register and loaded directly to the DAC outputs.
FORCE1 FORCE0 Action
0
0
FV & Current Clamp (if clamp enabled)
0
1
FI & Voltage Clamp (if clamp enabled)
1
0
Hi-Z FOH Voltage (pre load FIN DAC & Clamp DAC)
1
1
Hi-Z FOH Current (pre load FIN DAC & Clamp DAC)
18
17
16
15
RESERVED
C2
C1
C0
0
Bits C2 through C0 address allow selection of the required current range.
C2 C1 C0 Action
0
0
0
±5µA current range
0
0
1
±20µA current range
0
1
0
±200µA current range
0
1
1
±2mA current range
1
0
0
±external current range
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Rev. PrM | Page 33 of 48
AD5522
Preliminary Technical Data
14
13
MEAS1
MEAS0
Bits MEAS1 and MEAS0 allow selection of the required measure mode, allowing the measout line to be disabled, connected
to the temperature sensor or enabled for measurement or current or voltage.
MEAS1 MEAS0 Action
0
0
MEASOUT connected to I SENSE
0
1
MEASOUT connected to V SENSE
1
0
MEASOUT connected to Temperature Sensor
1
1
MEASOUT Hi-Z (SW 12 Open)
12
11
10
FIN
SFO
SSO
Bit FIN = 0 switches the input of the force amplifier to GND, while FIN = 1 connects it to FIN DAC output.
Bits SF0 through SS0 address each of the different combinations of switching the system force and sense lines to the force
and sense at the DUT. Selection of which channel the system force and sense lines are connected to as per P3 to P0
addressing. For correct operation, only one PMU channel should be connected at any one time to the SYS_FORCE/SYS_SENSE
paths.
SF0 SS0 Action
0
0
SYS_FORCE and SYS_SENSE Hi-Z
0
1
SYS_FORCE Hi-Z, SYS_SENSE connected to MEASVHx
1
0
SYS_FORCE connected to FOHx, SYS_SENSE Hi-Z
1
1
SYS_FORCE connected to FOHx, SYS_SENSE connected to MEASVHx
9
CL
8
CPOLH
7
6
COMPARE V/I
CLEAR
5
4
3
2
1
0 (LSB)
0
Per PMU current clamp enable bit. A logic high enables the clamp function for the selected PMU. The current clamp enable
function is also available in the System control register. This dual functionality allows flexible enable or disabling of this
function. When reading back information on the status of the clamp enable function on a per channel basis, what was most
recently written to the current clamp register is available in the readback word from either PMU or System Control Registers.
The Voltage clamps (FI mode) are always enabled.
Comparator output enable bit. A logic high enables the comparator output for the selected PMU, the comparator function
CPBIASEN must be enabled in the SYSTEM CONTROL REGISTER. The comparator output enable function is also available in
the System control register. This dual functionality allows flexible enable or disabling of this function.
A logic high selects compare voltage function, while logic low, current function.
To clear or reset a latched alarm bit and pin (temperature, guard or clamp), load a “1” to the Clear bit position. This bit applies
to latched alarm (clamp and guard) conditions on all four PMU channels.
Unused bits. Set to 0.
Rev. PrM | Page 34 of 48
Preliminary Technical Data
AD5522
WRITE DAC REGISTER
The DAC input, gain and offset registers are addressed through a combination of PMU bits (Bits 27 through 24) and MODE bits (Bits 23
and 22). Bits A5 through A0 address each of the DAC levels on chip. D15 through D0 are the DAC data Bits when writing to these
registers. PMU address bits allow addressing to DAC across any combination of PMU channels.
Table 19. DAC Register Bits
B28
RD/WR
B27
PMU3
B26
PMU2
B25
PMU1
B24
PMU0
B23
MODE1
B22
MODE0
B21
A5
B20
A4
B19
A3
B18
A2
B17
A1
B16
A0
B15 to B0
DATA BITS D15 (MSB to D0 (LSB)
Table 20. DAC Register Functions
Bit
28 (MSB)
Bit name
Description
RD/WR
27
26
25
24
PMU3
PMU2
PMU1
PMU0
When low, a write function takes place to the selected register, while if the RD/WR bit is set high, this initiates a
readback sequence of PMU, Alarm, Comparator, System Control or DAC register as determined by address bits.
Bits PMU3 through PMU0 address each of the PMU and DAC channels in the device. This allows individual
control of each DAC channel or any manner of combined addressing in addition to multi-channel programming.
B27
B26
B25
B24
B23
B22
SELECTED REGISTER
PMU3 PMU2 PMU1 PMU0 MODE1
MODE0
CH3
CH2
CH1
CH0
0
0
0
0
0
0
Write to System Control Register
×
×
CHO
Select DAC or PMU Registers. ×
0
0
0
1
See below
×
×
CH1
×
0
0
1
0
0
0
1
1
1
23
22
MODE1
MODE0
DAC REGISTER SPECIFIC BITS
21,20,19
A5,A4,A3
18,17,16
A2,A1,A0
15 to 0(LSB)
D15 (MSB) to D0(LSB)
0
1
0
1
1
1
0
0
1
1
1
0
0
0
1
×
×
CH1
CH0
×
CH2
×
×
-
-
-
-
CH3
×
×
×
-
-
-
-
CH3
CH2
CH1
×
CH3
CH2
CH1
CH0
Mode Bits, MODE0 and MODE1 allow addressing of the DAC gain (m), offset (c ) or input register (x1)
MODE1 MODE0 Action
0
0
System Control Register or PMU Register
0
1
DAC Gain (m) Register
1
0
DAC Offset (c) Register
1
1
DAC Input Data Register, (x1)
DAC Address Bits. A5 to A3 select which register set is addressed. See Table 21
DAC Address Bits, A2 to A0 select which DAC is addressed. See Table 21
16 DAC Data bits. D15 MSB.
Rev. PrM | Page 35 of 48
AD5522
Preliminary Technical Data
DAC Addressing
For the FIN and Comparator (CPH & CPL) DACs, there are sets of x1, m and c registers for each current range and for the voltage range,
but only two sets for the Clamp function (CLL and CLH).
When calibrating the device, m and c registers allow volatile storage of offset and gain coefficients. Calculation of the corresponding DAC
x2 register only occurs when x1 data is loaded (no internal calculation occurs on m or c updates).
There is one Offset DAC per all four channels in the device, it is addressed through any PMU0-3 address. The Offset DAC only has an
input register associated with it; there are no m or c registers for this DAC. When writing to this DAC, set both Mode bits high to address
the DAC input register (x1).
This address table is also used for readback of a particular DAC address.
Table 21. DAC Register Addressing
000
±5µA I range
Address bits A5 to A3 (DAC ADDRESS Register)
000
001
MODE1 MODE0
RESERVED
0
1
RESERVED
1
0
1
1
OFFSET DAC FIN
001
010
011
100
101
110
111
±20µA I range
±200µA I range
±2mA I range
±external I range
Voltage range
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Register Set
A2 to A0
(REGISTER
ADDRESS)
FIN
FIN
FIN
FIN
FIN
RESERVED
RESERVED
010
011
100
101
110
111
RESERVED
RESERVED
CPL
CPH
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
CLL I1
CLL V2
RESERVED
RESERVED
CLH I1
CLH V2
RESERVED
RESERVED
CPL
CPL
CPL
CPL
CPL
RESERVED
RESERVED
CPH
CPH
CPH
CPH
CPH
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
1
CLL I = Clamp Level Low Current register. CLH I = Clamp Level High Current Register. When forcing a voltage, current clamps are engaged, so this register set will be
loaded to the Clamp DAC.
2
CLL V = Clamp Level Low Voltage register. CLH V = Clamp Level High Voltage Register. When forcing a current, voltage clamps are engaged, so this register set will be
loaded to the Clamp DAC.
Rev. PrM | Page 36 of 48
Preliminary Technical Data
AD5522
READ REGISTERS
Readback of all the registers in the device is possible via the both SPI and LVDS interfaces. In order to readback data from a register, it is
first necessary to write a “readback” command to tell the device which register is required to readback. See Table 22 to address the
appropriate channel.
Table 22. Read Functions of the AD5522
B28
RD/WR
B27
PMU3
B26
PMU2
B25
PMU1
B24
PMU0
B23
MODE1
B22
MODE0
B21 to B0
DATA BITS
CH3
SELECTED REGISTER
CH2
CH1
CH0
READ FUNCTIONS
1
0
0
0
0
0
0
All zeros
Read from System Control Register
1
0
0
0
0
0
1
All zeros
Read from Comparator Status Registers
1
0
0
0
0
1
0
X
Reserved
1
0
0
0
0
1
1
All zeros
Read from Alarm Status Register
READ ADDRESSED PMU REGISTER – ONLY ONE PMU REGISTER CAN BE READ AT ONE TIME
All zeros
1
0
0
0
1
0
0
×
×
×
CH0
1
0
0
1
0
0
0
×
×
CH1
×
1
0
1
0
0
0
0
×
CH2
×
×
1
1
0
0
0
0
0
CH3
×
×
×
READ ADDRESSED DAC “m” Register – ONLY ONE DAC REGISTER CAN BE READ AT ONE TIME
DAC ADDRESS
1
0
0
0
1
0
1
×
×
×
CH0
SEE Table 21
1
0
0
1
0
0
1
×
×
CH1
×
1
0
1
0
0
0
1
×
CH2
×
×
CH3
×
×
×
1
1
0
0
0
0
1
READ ADDRESSED DAC “c” Register – ONLY ONE DAC REGISTER CAN BE READ AT ONE TIME
DAC ADDRESS
1
0
0
0
1
1
0
×
×
×
CH0
SEE Table 21
1
0
0
1
0
1
0
×
×
CH1
×
1
0
1
0
0
1
0
×
CH2
×
×
CH3
×
×
×
1
1
0
0
0
1
0
READ ADDRESSED DAC “x1” Register – ONLY ONE DAC REGISTER CAN BE READ AT ONE TIME
DAC ADDRESS
1
0
0
0
1
1
1
×
×
×
CH0
SEE Table 21
1
0
0
1
0
1
1
×
×
CH1
×
1
0
1
0
0
1
1
×
CH2
×
×
CH3
×
×
×
1
1
0
0
0
1
1
Once the required channel has been addressed, the device will load the 24 bit Readback data into the MSB positions of the 29 Bit serial
shift register, the five LSB bits will be filled with zeros. SCLK rising edges clock this readback data out on SDO(framed by the SYNC
signal).
A minimum of 24 clock rising edges are required to shift the readback data out of the shift register. If writing a 24-bit word to shift data
out of the device, user must ensure that the 24 bit write is effectively a NOP (No Operation) command. The last 5 bits in the shift register
will always be 00000b, these five bits will become the MSBs of the shift register when the 24 bit write is loaded. To ensure the device
receives a NOP command as outlined in Table 14, the recommended flush command is 0xFFFFFF and no change will be made to any
register within the device.
Readback data may also be shifted out by writing another 29 bit write or read command. If writing a 29-bit command, the readback data
will be MSB data available on SDO, followed by 00000b.
Rev. PrM | Page 37 of 48
AD5522
Preliminary Technical Data
READBACK OF SYSTEM CONTROL REGISTER
The readback function is a 24 bit word, mode, address and System Control Register data bits as shown in the following table.
Table 23. Readback System Control Register Data
Bit
Bit name
Description
23 (MSB)
MODE1
0
22
MODE0
0
SYSTEM CONTROL REGISTER SPECIFIC READBACK BITS
21
CL3
Readback the status of the individual Clamp Enable bits. A “0” means the clamp is disabled, while a “1” enabled.
The clamp enable function is also available in the System Control Register. This dual functionality allows flexible
20
CL2
enable or disabling of this function. When reading back information on the status of the clamp enable function,
19
CL1
what was most recently written to the clamp register from either System Control register or PMU register will be
18
CL0
available in the readback word.
17
16
15
14
CPOLH3
CPOLH2
CPOLH1
CPOLH0
13
CPBIASEN
12
DUTGND/CH
11
10
9
GUARD ALM
CLAMP ALM
INT10K
8
7
6
5
4
3
2
GUARD EN
GAIN1
GAIN0
TMP ENABLE
TMP1
TMP0
LATCHED
1
0 (LSB)
Unused Readback bits
Readback information on the Comparator Output Enable status. A “1” signifies the function is enabled, while a
“0” disabled. A logic high indicates that the PMU comparator output is enabled, while if low, it’s disabled. The
comparator output enable function is also available in the PMU Register. This dual functionality allows flexible
enable or disabling of this function. When reading back information on the status of the comparator output
enable function, what was most recently written to the comparator register from either System Control register
or PMU register will be available in the readback word.
This readback bit tells the status of the Comparator Enable function. A “1” in this bit position means the
Comparator functions are enabled, while a “0” disabled.
DUTGND per channel enable. If this bit is set at “1”, DUTGND per channel is enabled, while if “0”, individual
guard inputs are available per channel.
These bits give status on which of these alarm bits trigger the CGALM pin.
If this bit is set high, the internal 10k resistor is connected between FOH and MEASVH, and between DUTGND
and AGND. If low, they are disconnected.
Readback status of the Guard amplifies. If high, Amplifiers are enabled.
Status of the selected MEASOUT Output Range.
Information is available on the status of the setting for Thermal shutdown function. Refer to System control
write register.
This bit tells of the status of the open drain outputs. When high, the open drain alarm outputs are latched
outputs, while if low, they are unlatched.
Will be loaded with zeros.
Rev. PrM | Page 38 of 48
Preliminary Technical Data
AD5522
READBACK OF PMU REGISTER
The PMU readback function is a 24 bit word, mode, address and PMU data bits.
Table 24. Readback PMU Register (Only one PMU register may be read back at any one time).
Bit
Bit name
23 (MSB)
MODE1
22
MODE0
PMU REGISTER SPECIFIC BITS
21
CH EN
20
FORCE1
19
FORCE0
18
RESERVED
17
C2
16
C1
15
C0
14
MEAS1
13
MEAS0
12
FIN
11
SFO
10
SSO
9
CL
8
CPOLH
7
COMPARE V/I
6
LTMPALM
5
TMPALM
4, 3, 2, 1, 0 (LSB)
Unused Readback bits
Description
0
0
Channel Enable, If high selected channel is enabled, otherwise disabled.
These bits tell what force and measure mode the selected channel is in.
0
These three bits tell what forced or measured current range is set for the selected channel.
Bits MEAS1 and MEAS0 tell which measure mode is selected, voltage, current, temperature sensor or HiZ.
This bit shows the status of the Force input amplifier.
The system force and sense lines may be connected to any of the four PMU channels. Reading back these
bits tell if they are switched in or not.
A logic high in this readback position tells if the Per PMU clamp is enabled, while if low, the clamp is
disabled. The clamp enable function is also available in the System Control Register. This dual
functionality allows flexible enable or disabling of this function. When reading back information on the
status of the clamp enable function, what was most recently written to the clamp register from either
System Control register or PMU register will be available in the readback word.
A logic high indicates that the PMU comparator output is enabled, while if low, it’s disabled. The
comparator output enable function is also available in the System Control Register. This dual
functionality allows flexible enable or disabling of this function. When reading back information on the
status of the comparator output enable function, what was most recently written to the comparator
register from either System Control register or PMU register will be available in the readback word.
A logic high selects indicates the selected channel is comparing voltage function, while logic low, current
function.
TMPALM corresponds to the open drain TMPALM output pin which flags the user of a temperature event
exceeding the default or user programmed level. The temperature alarm is a per device alarm, and latched
(LTMPALM) and unlatched (TMPALM) bits tell a temperature event occurred and if the alarm still exists (if
the junction temperature still exceeds the programmed alarm level). To reset an alarm event, the user
must write to the CLEAR bit in the PMU register.
Will be loaded with zeros.
READBACK OF COMPARATOR STATUS REGISTER
The Comparator output status Register is a read only register giving access to the output status of each of the comparators on the chip.
Table 25 shows the format of the comparator readback word.
Table 25. Comparator Status Readback Register
Bit
Bit name
Description
23 (MSB)
MODE1
0
22
MODE0
1
COMPARATOR STATUS REGISTER SPECIFIC BITS
Comparator output conditions per channel corresponding to the comparator output pins.
21
CP0L0
20
CP0H0
19
CP0L1
18
CP0H1
17
CP0L2
16
CP0H2
15
CP0L3
14
CP0H3
13 to 0 (LSB)
Unused Readback bits
Will be loaded with zeros.
Rev. PrM | Page 39 of 48
AD5522
Preliminary Technical Data
READBACK OF ALARM STATUS REGISTER
The Alarm Status register is a READ only register that gives information on temperature, clamp and guard alarm events. In the event the
Guard and Clamp alarm functions are not used, (the alarm function may be switched off in the System Control Register). In this case, the
Temperature alarm status is also available in the contents of any of the four PMU readback registers.
Table 26. Alarm Status Readback Register
Bit
Bit name
Description
23 (MSB)
MODE1
1
22
MODE0
1
ALARM STATUS READBACK REGISTER SPECIFIC BITS
21
LTMPALM
TMPALM corresponds to the open drain TMPALM output pin which flags the user of a temperature event
exceeding the default or user programmed level. The temperature alarm is a per device alarm, and latched
20
TMPALM
(LTMPALM) and unlatched (TMPALM) bits tell a temperature event occurred and if the alarm still exists (if
the junction temperature still exceeds the programmed alarm level). To reset an alarm event, the user
must write to the CLEAR bit in the PMU register.
19
LG0
LGx is the per channel latched Guard Alarm bit and Gx is an unlatched alarm bit. These bits give
information on which channel flagged an alarm on the open drain alarm CGALM pin and if the alarm
18
G0
condition still exists.
17
LG1
16
G1
15
LG2
14
G2
13
LG3
12
G3
11
LC0
10
C0
9
LC1
8
C1
7
LC2
6
C2
5
LC3
4
C3
3 to 0 (LSB)
Unused Readback bits
LCx is a per channel latched Clamp alarm bit and Cx is the unlatched alarm bit. These bits give
information on which channel flagged an alarm on the open drain alarm CGALM pin and if the alarm
condition still exists.
Will be loaded with zeros.
READBACK OF DAC REGISTER
The DAC readback function is a 24 bit word, mode, address and DAC data bits.
Table 27. DAC Register Readback
Bit
Bit name
23 (MSB)
MODE1
22
MODE0
DAC READBACK REGISTER SPECIFIC BITS
21 to 16
A5, A4, A3, A2, A1
15 to 0 (LSB)
D15 to D0
Description
0
0
Address Bits indicating the DAC register that is read.
Contents of the addressed DAC register (x1, m or c).
Rev. PrM | Page 40 of 48
Preliminary Technical Data
AD5522
POWER ON DEFAULT
The power on default for all DAC channels is that the contents of each m register is set to full-scale (0xFFFF) and c register to
midscale(0x8000). The contents of the DAC registers are :
Offset DAC: 0xA492, FIN DACs: 0x8000, CLL DACs: 0x0000, CLH DACs: 0xFFFF, CPL DACs: 0x0000, CPH DACs: 0xFFFF
The power on default for the Alarm Status Register is 0xFFFFF0, while the Comparator Status registers powers up at 0x400000. The
power on defaults of the PMU register and the System Control Register are shown below.
Table 28. Power on Default for System Control Register and PMU Register
Bit
21 (MSB)
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
SYSTEM CONTROL REGISTER POWER ON DEFAULT
Bit name
Description
CL3
0
CL2
0
CL1
0
CL0
0
CPOLH3
0
CPOLH2
0
CPOLH1
0
CPOLH0
0
CPBIASEN
0
DUTGND/CH
0
GUARD ALM
0
CLAMP ALM
0
INT10K
0
GUARD EN
0
GAIN1
0
GAIN0
0
PMU REGISTER POWER ON DEFAULT
Bit name
Description
CH EN
0
FORCE1
0
FORCE0
0
RESERVED
0
C2
0
C1
1
C0
1
MEAS1
1
MEAS0
1
FIN
0
SFO
0
SSO
0
CL
0
CPOLH
0
COMPARE V/I
0
1
LTMPALM
5
TMP ENABLE
1
TMPALM
1
4
3
2
1
0 (LSB)
TMP1
TMP0
LATCHED
Unused Data Bits
0
0
0
0
0
Unused Data Bits
0
0
0
0
0
Rev. PrM | Page 41 of 48
AD5522
Preliminary Technical Data
SETTING UP THE DEVICE ON POWER ON
CHANGING MODES
On power on, default conditions are recalled from the power on
reset register ensuring each PMU and DAC channel is powered
up to a known condition. To operate the device, the user must:
There are different ways of handling a mode change:
1)
Configure the device by writing to the System Control
register to set up different functions as required.
2)
Calibrate out errors and load required calibration values to
(Gain) m and (Offset) c registers, and load codes to each
DAC input register (x1). Once x1 values are loaded to the
individual DACs, the calibration engine calculates the
appropriate x2 value and stores it ready for the PMU
address to call it.
3)
4)
Load the required PMU channel with the required force
mode, current range etc. Loading the PMU channel
configures the switches around the Force Amplifier,
Measure function, clamps and comparators and also acts as
a load signal for the DACs, loading the DAC register with
the appropriate stored x2 value.
As the voltage and current ranges have individual DAC
registers associated with them, each PMU register mode of
operation calls a particular x2 register. Hence, only updates
(changes to x1 register) to DACs associated with the
selected mode of operation are reflected to the output of
the PMU. If there is a change to the x1 value associated
with a different PMU mode of operation, then this x1 value
and it’s m and c coefficients are used to calculate a
corresponding x2 value which is stored in the correct x2
register, but it does not get loaded to the DAC.
1)
Load any DAC x1 values that are required to change.
Remember that x1 registers are available per voltage and
current range (for Force Amplifier and Comparator
DACs), so you can preload these and may not need to
make changes. The calibration engine will calculate the x2
values and store them.
2)
Now change into the new PMU mode. This will load the
new switch conditions in the PMU circuitry and load the
DAC register with the stored x2 data.
or
1)
Use the Hi-Z V or Hi-Z I mode in the PMU register, this
makes the amplifier high impedance.
2)
Now load any DAC x1 values that need to be loaded.
Remember that x1 registers are available per voltage and
current range, so you can preload these and may not need
to make changes.
3)
When the Hi-Z (V or I) modes are used, the relevant DAC
outputs are automatically updated (FIN, CLL, CLH DACs).
For example, when selecting Hi-Z V (Voltage), the FIN
Voltage x2 result is loaded, offset and gain corrected,
cached and loaded to the FIN DAC. When forcing a
voltage, current clamps are engaged, so the CLL I (Current)
register can be loaded, gain and offset corrected and loaded
to the DAC register. Similarly, for the CLH I register.
4)
Now change into the new PMU mode (FI/FV). This will
load the new switch conditions in the PMU circuitry. As
the DAC outputs are already loaded, transients when
changing current or voltage mode will be minimized.
Rev. PrM | Page 42 of 48
Preliminary Technical Data
AD5522
REQUIRED EXTERNAL COMPONENTS
The minimum required external components are shown in the
block diagram below. Decoupling will be very dependent on the
type of supplies used, other decoupling on the board and the
noise in the system. It is possible more or less decoupling may
be required as a result.
AVSS
AVDD DVCC
10µF
10µF
0.1µF
AVSS
0.1µF
AVDD
REF
10µF
0.1µF
0.1µF
VREF
DVCC
CCOMP(0-3)
EXTFOH3
CFF3
EXTFOH0
CFF0
FOH3
FOH0
MEASVH3
MEASVH0
EXTMEASIH3
EXTMEASIH0
up to
64mA
up to
64mA
EXTMEASIL0
EXTMEASIL3
DUT
DUT
EXTFOH2
CFF2
EXTFOH1
CFF1
FOH2
FOH1
MEASVH2
MEASVH1
EXTMEASIH2
EXTMEASIH1
up to
64mA
up to
64mA
EXTMEASIL1
DUTGND
EXTMEASIL2
DUT
DUT
Figure 28. External components required for use with this PMU device.
Rev. PrM | Page 43 of 48
AD5522
Preliminary Technical Data
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful
consideration of the power supply and ground return layout
helps to ensure the rated performance. The printed circuit
board on which the AD5522 is mounted should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. If the AD5522 is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
For supplies with multiple pins (AVSS, AVDD, VCC), it is
recommended to tie these pins together and to decouple each
supply once.
The AD5522 should have ample supply decoupling of 10 µF in
parallel with 0.1 µF on each supply located as close to the
package as possible, ideally right up against the device. The
10µF capacitors are the tantalum bead type. The 0.1 µF
capacitor should have low effective series resistance (ESR) and
effective series inductance (ESI), such as the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching.
Digital lines running under the device should be avoided,
because these couple noise onto the device. The analog ground
plane should be allowed to run under the AD5522 to avoid
noise coupling (only with the package with paddle up).. The
power supply lines of the AD5522 should use as large a trace as
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching digital
signals should be shielded with digital ground to avoid
radiating noise to other parts of the board, and should never be
run near the reference inputs. It is essential to minimize noise
on all VREF lines. Avoid crossover of digital and analog signals.
Traces on opposite sides of the board should run at right angles
to each other. This reduces the effects of feedthrough through
the board. As is the case for all thin packages, care must be
taken to avoid flexing the package and to avoid a point load on
the surface of this package during the assembly process.
Also note that the exposed paddle of the AD5522 is connected
to the negative supply AVSS.
Rev. PrM | Page 44 of 48
Preliminary Technical Data
AD5522
TYPICAL APPLICATION FOR THE AD5522
.
Figure 29 shows the AD5522 as used in an ATE system. This
device can used as a per pin parametric unit in order to speed
up the rate at which testing can be done.
The central PMU shown in the block diagram is usually a
highly accurate PMU, and is shared among a number of pins in
the tester. In general, many discrete levels are required in an
ATE system for the pin drivers, comparators, clamps, and active
loads. DAC devices, such as the AD5379, offer a highly
integrated solution for a number of these levels. The AD5379 is
a dense 40-channel DAC designed with high channel
requirements, such as ATE
Driven Shield
DAC
Guard Amp
Central PMU
AD5522
ADC
DAC
Timing
Generator
DLL,Logic
DAC
ADC
Vterm
DAC
Timing Data
Memory
VCH
PPMU
VH
DUT
DAC
Relays
Formatter
De-Skew
50 Ω Coax
Driver
VL
DAC
VCL
Guard Amp
DAC
DAC
Compare
Memory
GND Sense
VTH
Formatter
De-Skew
Comp
DAC
VTL
DAC
IOL
DAC
Device Power supply
ADC
Active Load
VCOM
DAC
DAC
IOH
Figure 29. Typical Applications Circuit using the AD5522 as a per pin parametric unit.
Rev. PrM | Page 45 of 48
AD5522
Preliminary Technical Data
OUTLINE DIMENSIONS
14.20
14.00 SQ
13.80
0.75
0.60
0.45
12.20
12.00 SQ
11.80
1.20
MAX
80
61
61
1
60
80
1
60
PIN 1
EXPOSED
PAD
TOP VIEW
(PINS DOWN)
BOTTOM VIEW
0° MIN
1.05
1.00
0.95
0.15
0.05
(PINS UP)
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
SEATING
PLANE
9.50
BSC SQ
20
41
41
40
21
20
21
40
VIEW A
0.50 BSC
LEAD PITCH
0.27
0.22
0.17
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD
Figure 30. 80 lead TQFP/EP with exposed pad on bottom
14.20
14.00 SQ
13.80
0.75
0.60
0.45
1.20
MAX
12.20
12.00 SQ
11.80
80
61
61
1
80
1
60
60
PIN 1
EXPOSED
PAD
0° MIN
1.05
1.00
0.95
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
BOTTOM VIEW
9.50
BSC
(PINS UP)
TOP VIEW
(PINS DOWN)
20
41
40
21
VIEW A
6.50
BSC
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HU
Figure 31. 80 lead TQFP/EP with exposed pad on top
Rev. PrM | Page 46 of 48
41
20
21
40
0.50 BSC
LEAD PITCH
0.27
0.22
0.17
Preliminary Technical Data
AD5522
ORDERING GUIDE
Model
Function
Package Description1
AD5522JSVD
Quad PMU with 4 internal current ranges, full comparator
function, 1 external current range, SPI and LVDS serial
interfaces.
Quad PMU with 4 internal current ranges, full comparator
function, 1 external current range, SPI and LVDS serial
interfaces.
Quad PMU, 4 internal current ranges, window comparator
function, SPI interface.
80 Lead TQFP with exposed pad on bottom
Package
Options
SV-80
80 Lead TQFP with exposed pad on top
SV-80
64 Lead LFCSP with exposed pad on bottom
9mm x 9mm
CP-64
AD5522JSVUZ2
AD5523JCPZ2,3
1
Exposed pad is electrically connected internally to AVSS.
2
Lead Free Package.
Reduced functionality. Contact factory for AD5523 datasheet and more details.
3
Rev. PrM | Page 47 of 48
AD5522
Preliminary Technical Data
NOTES
© 2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
Printed in the U.S.A.
PR06197-0-03/07(PrM)
Rev. PrM | Page 48 of 48