Supertex inc. TP2424 P-Channel Enhancement-Mode Vertical DMOS FET Features General Description ►► Low threshold ►► High input impedance ►► Low input capacitance ►► Fast switching speeds ►► Free from secondary breakdown ►► Low input and output leakage This low threshold enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Applications ►► ►► ►► ►► ►► ►► Logic level interfaces Solid state relays Linear amplifiers Power management Analog switches Telecom switches Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Ordering Information Part Number TP2424N8-G Product Summary Package Option Packing TO-243AA (SOT-89) 2000/Reel -G denotes a lead (Pb)-free / RoHS compliant package. Contact factory for Wafer / Die availablity. Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant. Parameter Value Drain-to-source voltage BVDSS Drain-to-gate voltage BVDGS Gate-to-source voltage ±20V Typical Thermal Resistance θja TO-243AA (SOT-89) 133OC/W VGS(th) ID(ON) -2.4V -800mA (max) (max) 8.0Ω (min) DRAIN SOURCE DRAIN GATE -55OC to +150OC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Package -240V RDS(ON) Pin Configuration Absolute Maximum Ratings Operating and storage temperature BVDSS/BVDGS TO-243AA (SOT-89) Product Marking TP4CW W = Code for week sealed = “Green” Packaging Package may or may not include the following marks: Si or TO-243AA (SOT-89) Doc.# DSFP-TP2424 B081313 Supertex inc. www.supertex.com TP2424 Thermal Characteristics ID Package Power Dissipation (continuous) ID (pulsed) @ TA = 25OC -316mA -1.9A 1.6W TO-243AA (SOT-89) † IDR† IDRM -316mA -1.9A † ID (continuous) is limited by max rated Tj . ‡ Mounted on FR5 board, 25mm x 25mm x 1.57mm. Electrical Characteristics (T = 25°C unless otherwise specified) A Sym Parameter Min Typ Max Units BVDSS Drain-to-source breakdown voltage -240 - - V VGS = 0V, ID = -250μA VGS(th) Gate threshold voltage -1.0 - -2.4 V VGS = VDS, ID= -1.0mA Change in VGS(th) with temperature - - 4.5 O mV/ C VGS = VDS, ID= -1.0mA Gate body leakage - - -100 nA VGS = ± 20V, VDS = 0V - -10 μA VGS = 0V, VDS = Max Rating - -1.0 mA VDS = 0.8 Max Rating, VGS = 0V, TA = 125°C -0.3 - - -0.8 - - ∆VGS(th) IGSS IDSS Zero gate voltage drain current ID(ON) On-state drain current RDS(ON) ∆RDS(ON) - - 10 - - 8.0 Change in RDS(ON) with temperature - - 0.75 %/ C VGS = -10V, ID = -500mA 150 - - mmho VDS = -25V, ID = -200mA CISS Input capacitance - - 200 COSS Common source output capacitance - - 100 CRSS Reverse transfer capacitance - - 40 td(ON) Turn-on delay time - - 20 Rise time - - 30 Turn-off delay time - - 35 Fall time - - 25 Diode forward voltage drop - - Reverse recovery time - 300 tf VSD trr VGS = -10V, VDS = -25V - Forward transconductance td(OFF) VGS = -4.5V, VDS = -25V Static drain-to-source on-state resistance GFS tr A Conditions Ω O VGS = -4.5V, ID = -150mA VGS = -10V, ID = -500mA pF VGS = 0V, VDS = -25V, f = 1.0 MHz ns VDD = -25V, ID = -250mA, RGEN = 25Ω -1.5 V VGS = 0V, ISD = -500mA - ns VGS = 0V, ISD = -500mA Notes: 1. All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. Switching Waveforms and Test Circuit 0V INPUT -10V Pulse Generator 10% t(ON) td(ON) 0V OUTPUT VDD Doc.# DSFP-TP2424 B081313 tr td(OFF) 90% 10% RGEN 90% t(OFF) D.U.T. tf INPUT OUTPUT RL 90% 10% 2 VDD Supertex inc. www.supertex.com TP2424 3-Lead TO-243AA (SOT-89) Package Outline (N8) D D1 C E H L 1 2 E1 3 b b1 e A e1 Top View Symbol Dimensions (mm) Side View A b b1 C D D1 E E1 MIN 1.40 0.44 0.36 0.35 4.40 1.62 2.29 2.00† NOM - - - - - - - - MAX 1.60 0.56 0.48 0.44 4.60 1.83 2.60 2.29 e e1 1.50 BSC 3.00 BSC H L 3.94 0.73† - - 4.25 1.20 JEDEC Registration TO-243, Variation AA, Issue C, July 1986. † This dimension differs from the JEDEC drawing Drawings not to scale. Supertex Doc. #: DSPD-3TO243AAN8, Version F111010. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2013 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-TP2424 B081313 3 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com