REVISIONS LTR DESCRIPTION DATE Prepared in accordance with ASME Y14.24 APPROVED Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 PMIC N/A PREPARED BY Phu H. Nguyen Original date of drawing YY MM DD CHECKED BY 14-07-10 Phu H. Nguyen APPROVED BY Thomas M. Hess SIZE A REV AMSC N/A 4 CODE IDENT. NO. 5 6 7 8 9 10 11 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http://www.landandmaritime.dla.mil/ TITLE MICROCIRCUIT, LINEAR, 0.5 A, 60 V STEP DOWN DC/DC CONVERTER WITH ECO-MODE, MONOLITHIC SILICON DWG NO. V62/14617 16236 PAGE 1 OF 11 5962-V091-14 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 0.5 A, 60 V step down DC/DC converter with ECO-Mode microcircuit, with an operating temperature range of -55°C to +125°C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/14617 - Drawing number 01 X E Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type Generic 01 Circuit function TPS54060 -EP 0.5 A, 60 V step down DC/DC converter with ECO-Mode 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 10 JEDEC MO-187 X Package style Plastic Small Outline Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator A B C D E Z DLA LAND AND MARITIME COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14617 PAGE 2 1.3 Absolute maximum ratings. 1/ Input voltage: VIN ................................................................................................... EN .................................................................................................... BOOT ............................................................................................... VSENSE .......................................................................................... COMP .............................................................................................. PWRGD ........................................................................................... SS/TR .............................................................................................. RT/CLK ............................................................................................ Output voltage: BOOT-PH ......................................................................................... PH .................................................................................................... PH, 10-ns Transient ......................................................................... Voltage difference, PAD to GND ............................................................. Source current: EN .................................................................................................... BOOT ............................................................................................... VSENSE .......................................................................................... PH .................................................................................................... RT/CLK ............................................................................................ Sink current: VIN ................................................................................................... COMP .............................................................................................. PWRGR ........................................................................................... SS/TR .............................................................................................. Operating junction temperature ............................................................... Recommended ambient temperature ...................................................... Storage temperature ............................................................................... Electrostatic discharge: (HBM) QSS 009-105 (JESD22-A114A) ........................................... (CDM) QSS 009-147 (JESD22-C101B.01) ...................................... 1/ -0.3 V- to 65 V -0.3 V to 5 V 73 V -0.3 V to 3 V -0.3 V to 3 V -0.3 V to 6 V -0.3 V to 3 V -0.3 V to 3.6 V 8V -0.6 V to 65 V -2 V to 65 V ±200 mV 100 µA 100 mA 10 µA Current limit A 100 µA Current limit A 100 µA 10 mA 200 µA -55°C to 150°C -55°C to 125°C -65°C to 150°C 1 kV 500 V Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14617 PAGE 3 1.5 Thermal characteristics. Thermal metric 2/ 3/ Junction to ambient thermal resistance, θJA Junction to ambient thermal resistance, θJA 4/ Junction to top characterization parameter, ΨJT Junction to board characterization parameter, ΨJB Junction to case (top) thermal resistance, θJCtop Junction to case (bottom) thermal resistance, θJCbot Junction to board thermal resistance, θJB Case outline X 62.5 57 1.7 20.1 83 21 28 Units °C/W 2. APPLICABLE DOCUMENTS JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 JESD 22-A114 JESD22-C101 – – – Registered and Standard Outlines for Semiconductor Devices Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components (Copies of these documents are available online at http:/www.jedec.org or from JEDEC – Solid State Technology Association, 3103 North 10th Street, Suite 240–S, Arlington, VA 22201-2107). 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3, 1.4, and table I herein. _______________ 2/ 3/ 4/ For more information about traditional and new thermal metrics, see manufacturer data. Power rating at a specific ambient temperature TA should be determined with a junction temperature of 150°C. This is the point where distortion starts to substantially increase. See power dissipation estimate in application section from the manufacturer data. Test board conditions: a) 3 inches x 3 inches, 2 layers, thickness: 0.062 inch b) 2 oz. copper traces located on the top of the PCB. c) 2 oz. copper ground plane, bottom layer. d) 6 thermal vias (13 mils) located under the device package. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14617 PAGE 4 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Terminal function. The terminal function shall be as shown in figure 3. 3.5.4 Simplified schematic. The simplified schematic shall be as shown in figure 4. 3.5.5 Functional block diagram. The functional block diagram shall be as shown in figure 5. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14617 PAGE 5 TABLE I. Electrical performance characteristics. 1/ Test Symbol Supply voltage (VIN PIN) Operating input voltage Internal under voltage lockout threshold Shutdown supply current Operating: nonswitching supply current Enable and UVLO (EN PIN) Enable threshold voltage Input current Hysteresis current Voltage reference Voltage reference Limits Test conditions 2/ Min Typ 3.5 No voltage hysteresis, rising and falling EN = 0 V, 3.5 V ≤ VIN ≤ 60 V VSENSE = 0.83 V, VIN = 12 V No voltage hysteresis, rising and falling Enable threshold +50 mV Enable threshold -50 mV TJ = 25°C Unit Max 60 2.5 1.3 116 8 150 V V µA 0.9 1.25 -3.8 -0.9 -2.9 1.6 V µA 0.792 0.8 0.808 V 0.78 0.8 0.821 High side MOSFET VIN = 3.5 V, BOOT-PH = 3 V VIN = 12 V, BOOT-PH = 6 V On-resistance Error amplifier Input current Error amplifier transconductance (gM) Error amplifier transconductance (gM) during slow start Error amplifier dc gain Error amplifier bandwidth Error amplifier source/sink COMP to switch current transconductance Current limit Current limit threshold Thermal Shutdown Thermal shutdown Timing resistor and external clock (RT/CLK PIN) Switch frequency range using RT mode Switching frequency fSW Switch frequency range using CLK mode Minimum CLK input pulse width RT/CLK high threshold RT/CLK low threshold RT/CLK falling edge to PH rising edge delay PLL lock in time 300 200 -2 µA < ICOMP < 2 µA, VCOMP = 1 V -2 µA < ICOMP < 2 µA, VCOMP = 1 V, VVSENSE = 0.4 V VVSENSE = 0.8 V V(COMP) = 1 V, 100 mV overdrive VIN = 12 V 0.5 V(VIN) = 12 V V(VIN) = 12 V, RT = 200 kΩ V(VIN) = 12 V 130 440 300 V(VIN) = 12 V V(VIN) = 12 V Measured at 500 kHz with resistor in series Measured at 500 kHz 0.5 mΩ 465 50 97 26 nA µMhos 10,000 2700 ±7 1.9 V/V kHz µA A/V 0.94 A 182 °C 581 40 1.9 0.7 60 2500 740 2200 2.2 100 kHz kHz kHz ns V V ns µs See footnote at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14617 PAGE 6 TABLE I. Electrical performance characteristics - Continued. 1/ Test Symbol Slow start and tracking (SS/TR) Charge current SS/TR to VSENSE matching SS/TR to reference crossover SS/TR discharge current (overload) SS/TR discharge voltage Power good (PWRGD PIN) VSENSE threshold Hysteresis Output high leakage On resistance Minimum VIN for defined output 1/ 2/ Limits Test conditions 2/ Min Typ VSS/TR = 0.4 V VSS/TR = 0.4 V 98 % nominal VSENSE = 0 V, V(SS/TR) = 0.4 V VSENSE = 0 V VVSENSE VSENSE falling (Fault) VSENSE rising (Good) VSENSE rising (Fault) VSENSE falling (Good) VSENSE falling VSENSE = VREF, V(PWRGD) = 5.5 V, 25°C I(PWRGD) = 3 mA, VSENSE < 0.79 V V(PWRGD) = 0.5 V, I(PWRGD) = 100 µA Unit Max 2 45 1.0 112 54 µA mV V µA mV 92% 94% 109% 107% 2% 10 50 0.95 nA Ω V 1.5 Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. -55°C ≤ TJ ≤ +150°C, VIN = 3.5 V to 60 V (unless otherwise noted). DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14617 PAGE 7 Case X e THERMAL PAD SIZE AND SHAPE SHOWN ON SEPARATE SHEET b 0.08 M c 10 6 0°-8° E PIN 1 IDENTIFIER GAGE PLANE E1 5 L L1 DETAIL A D SEE DETAIL A A SEATING PLANE A1 Symbol A A1 b c D/E Dimensions Millimeters Symbol Min Max 0.05 0.17 0.13 2.90 1.10 0.15 0.27 0.23 3.10 E1 e L L1 0.10 Millimeters Min Max 4.75 5.05 0.50 BSC 0.40 0.70 0.25 REF NOTES: 1. All linear dimensions are in millimeters. 2. This drawing is subject to change without notice. 3. Body dimensions do not include mold flash or protrusion not to exceed 0.15. 4. This package is designed to be soldered to a thermal pad on the board. Refer to technical brief from manufacturer for information regarding recommended board layout. 5. See the additional figure in the Product data sheet from manufacturer for details regarding the exposed thermal pad features and dimensions. 6. Falls within JEDEC MO-187 variation BA-T. FIGURE 1. Case outline. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14617 PAGE 8 Case outline X Terminal Terminal symbol number BOOT 10 VIN 9 EN 8 Terminal number 1 2 3 4 5 SS/TR RT/CLK Terminal symbol PH GND COMP 7 6 VSENSE PWRGD FIGURE 2. Terminal connections. Terminal Name No. BOOT 1 I/O Description O COMP 8 O EN 3 I GND PH POWERPAD 9 10 (11) I - POWRGD 6 O RT/CLK 5 I SS/TR 4 I VIN VSENSE 2 7 I I A bootstrap capacitor is required between BOOT and PH. If the voltage on this capacitor is below the minimum required by the output device, the output is forced to switch off until the capacitor is refreshed. Error amplifier output, and input to the output switch current comparator. Connect frequency compensation components to this pin. Enable pin, internal pull-up current source. Pull below 1.2V to disable. Float to enable. Adjust the input undervoltage lockout with two resistors. Ground The source of the internal high-side power MOSFET. GND pin must be electrically connected to the exposed pad on the printed circuit board for proper operation. An open drain output, asserts low if output voltage is low due to thermal shutdown, dropout, overvoltage or EN shut down. Resistor Timing and External Clock. An internal amplifier holds this pin at a fixed voltage when using an external resistor to ground to set the switching frequency. If the pin is pulled above the PLL upper threshold, a mode change occurs and the pin becomes a synchronization input. The internal amplifier is disabled and the pin is a high impedance clock input to the internal PLL. If clocking edges stop, the internal amplifier is re-enabled and the mode returns to a resistor set function. Slow-start and Tracking. An external capacitor connected to this pin sets the output rise time. Since the voltage on this pin overrides the internal reference, it can be used for tracking and sequencing. Input supply voltage, 3.5 V to 60 V. Inverting node of the transconductance (gm) error amplifier. FIGURE 3. Terminal function. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14617 PAGE 9 VIN PWRGD BOOT EN PH SS/TR RT/CLK VSENSE COMP GND FIGURE 4. Simplified schematic. PWRGD EN VIN SHUTDOWN UV THERMAL LOGIC UVLO SHUTDOWN ENABLE COMPARATOR SHUTDOWN SHUTDOWN LOGIC OV ENABLE THRESHOLD BOOT CHARGE VOLTAGE MINIMUM REFERENCE BOOT CLAMP UVLO PULSE SKIP ERROR AMPLIFIER VSENSE CURRENT SENSE PWM - COMPARATOR BOOT + SS/TR LOGIC + AND PWM LATCH SHUTDOWN SLOPE COMPENSATION PH COMP POWERPAD FREQUENCY SHIFT OVERLOAD MAXIMUM RECOVERY CLAMP GND OSCILLATOR WITH PLL RT/CLK FIGURE 5. Functional block diagram. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14617 PAGE 10 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number 2/ V62/14617-01XE 01295 TPS54060MDGQTEP 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. 2/ The case outline X is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54060MDGQTEPR). CAGE code 01295 DLA LAND AND MARITIME COLUMBUS, OHIO Source of supply Texas Instruments, Inc. Semiconductor Group 8505 Forest Lane P.O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P.O. Box 84, M/S 853 Sherman, TX 75090-9493 SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/14617 PAGE 11