REVISIONS LTR DESCRIPTION DATE Prepared in accordance with ASME Y14.24 APPROVED Vendor item drawing REV PAGE REV PAGE REV STATUS OF PAGES REV PAGE 1 2 3 PMIC N/A PREPARED BY Phu H. Nguyen Original date of drawing YY MM DD CHECKED BY 12-10-26 Phu H. Nguyen APPROVED BY Thomas M. Hess SIZE A REV AMSC N/A 4 CODE IDENT. NO. 5 6 7 8 9 10 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http://www.landandmaritime.dla.mil/ TITLE MICROCIRCUIT, LINEAR, 2.5 V TO 5.5 V, 500 µA, QUAD VOLTAGE OUTPUT 12 BIT DAC IN 10-LEAD PACKAGE, MONOLITHIC SILICON DWG NO. V62/12628 16236 PAGE 1 OF 10 5962-V020-13 1. SCOPE 1.1 Scope. This drawing documents the general requirements of a high performance 2.5 V to 5.5 V, 500 µA, quad voltage output 12 bit DAC in 10 lead package microcircuit, with an operating temperature range of -55°C to +125°C. 1.2 Vendor Item Drawing Administrative Control Number. The manufacturer’s PIN is the item of identification. The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation: V62/12628 - Drawing number 01 X E Device type (See 1.2.1) Case outline (See 1.2.2) Lead finish (See 1.2.3) 1.2.1 Device type(s). Device type Generic 01 AD5324-EP Circuit function 2.5 V to 5.5 V, 500 µA, quad voltage output 12 bit DAC in 10 lead package 1.2.2 Case outline(s). The case outlines are as specified herein. Outline letter Number of pins JEDEC PUB 95 10 JEDEC MO-187-BA X Package style Mini Small Outline Package 1.2.3 Lead finishes. The lead finishes are as specified below or other lead finishes as provided by the device manufacturer: Finish designator A B C D E Z DLA LAND AND MARITIME COLUMBUS, OHIO Material Hot solder dip Tin-lead plate Gold plate Palladium Gold flash palladium Other SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12628 PAGE 2 1.3 Absolute maximum ratings. 1/ 2/ VDD to GND ............................................................................................. Digital input voltage to GND .................................................................... Reference input voltage to GND ............................................................. VOUTA through VOUTD to GND ................................................................. Operating temperature range: Industrial .......................................................................................... Storage temperature range .............................................................. Junction temperature (TJ max) ......................................................... Case outline X Power dissipation ............................................................................. θJA Thermal impedance .................................................................. θJC Thermal impedance ................................................................. Reflow soldering Peak temperature ............................................................................ Time at peak temperature ................................................................ -0.3 V to +7.0 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -55°C to +125°C -65°C to 150°C 150°C (TJ max – TA)/ θJA 206°C/W 44°C/W 220°C 10 sec to 40 sec 2. APPLICABLE DOCUMENTS JEDEC – SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP95 – Registered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at http:/www.jedec.org or from JEDEC – Solid State Technology Association, 3103 North 10th Street, Suite 240–S, Arlington, VA 22201.) 3. REQUIREMENTS 3.1 Marking. Parts shall be permanently and legibly marked with the manufacturer’s part number as shown in 6.3 herein and as follows: A. B. C. Manufacturer’s name, CAGE code, or logo Pin 1 identifier ESDS identification (optional) 3.2 Unit container. The unit container shall be marked with the manufacturer’s part number and with items A and C (if applicable) above. 1/ 2/ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Transient currents of up to 100 mA do not cause SCR latch up. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12628 PAGE 3 3.3 Electrical characteristics. The maximum and recommended operating conditions and electrical performance characteristics are as specified in 1.3 and table I herein. 3.4 Design, construction, and physical dimension. The design, construction, and physical dimensions are as specified herein. 3.5 Diagrams. 3.5.1 Case outline. The case outline shall be as shown in 1.2.2 and figure 1. 3.5.2 Terminal connections. The terminal connections shall be as shown in figure 2. 3.5.3 Terminal function. The terminal function shall be as shown in figure 3. 3.5.4 Functional block diagram. The functional block diagram shall be as shown in figure 4. 3.5.5 Serial Interface timing diagram. The serial Interface timing diagram shall be as shown in figure 5. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12628 PAGE 4 TABLE I. Electrical performance characteristics. 1/ Test Symbol DC Performance 3/ Resolution Relative accuracy Differential nonlinearity 4/ Offset error Gain error Lower dead band Offset error drift 7/ Limits Test conditions 2/ Min Max 12 TYP ±10 ±1 ±3 ±1 60 -12 TYP 5/ See FIGURE 5 See FIGURE 5 6/ Gain error drift 7/ Bits LSB LSB % of FSR % of FSR mV ppm of FSR/°C -5 TYP DC power supply rejection ratio 7/ DC crosstalk 7/ DAC reference inputs 7/ VREF input range ΔVDD = %10 RL = 2 kΩ to GND or VDD VREF input impedance Normal operation Power down mode Frequency = 10 kHz Reference feedthrough Output characteristics 7/ Minimum output voltage 8/ Maximum output voltage 8/ DC output impedance 9/ 10/ VDD = 5 V VDD = 3 V Coming out of power down mode VDD = 5 V Coming out of power down mode VDD = 3 V Short circuit current Power up time Logic inputs Input current Unit -60 TYP 200 TYP ppm of FSR/°C dB µV 0.25 VDD 37 >10 TYP -90 TYP V kΩ MΩ dB 0.001 TYP VDD – 0.001 TYP 0.5 TYP 25 TYP 16 TYP 2.5 TYP 5 TYP V Ω mA µs 7/ Input low voltage VIL Input high voltage VIH Pin capacitance Power requirements VDD IDD (Normal mode) 11/ VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V IDD (Power down mode) VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V ±1 0.8 0.6 0.5 VDD = 5 V ±10% VDD = 3 V ±10% VDD = 2.5 V VDD = 5 V ±10% VDD = 3 V ±10% VDD = 2.5 V µA V 2.4 2.1 2.0 3 TYP pF 2.5 5.5 V VIH = VDD and VIL = GND VIH = VDD and VIL = GND 900 700 µA µA VIH = VDD and VIL = GND VIH = VDD and VIL = GND 1 1 µA µA See footnote at end of table. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12628 PAGE 5 TABLE I. Electrical performance characteristics - Continued. 1/ Test AC characteristics Output voltage settling time Slew rate Major code transition glitch energy Digital feedthrough Digital crosstalk DAC to DAC crosstalk Multiplying bandwidth Total harmonic distortion Test Symbol 2/ 3/ 4/ 5/ 6/ 7/ 8/ 9/ 10/ 11/ 12/ Min VREF = VDD = 5 V; ¼ scale to ¾ scale change (0x400 to 0xC00) Test conditions 2/ 2.5 V ≤ VDD ≤ 3.6 V Min 40 16 16 16 5 4.5 0 80 Max µs 0.7 TYP 12 TYP 1 TYP 1 TYP 3 TYP 200 TYP -70 TYP VREF = 2 V ±0.1 Vp-p VREF = 2.5 V ±0.1 Vp-p, frequency = 10 kHz Symbol Unit 10 1 LSB change around major carry Timing characteristics 7/ 12/ (see FIGURE 5) SCLK cycle time t1 SCLK high time t2 SCLK low time t3 ������� t4 SYNC to SCLK falling edge setup time Data setup time t5 Data hold time t6 ������� rising edge t7 SCLK falling edge to SYNC ������� t8 Minimum SYNC high time 1/ Limits Test conditions 2/ Max V/µs nV-sec kHz dB 3.6 V ≤ VDD ≤ 5.5 V Min Unit Max 33 13 13 13 5 4.5 0 33 ns Testing and other quality control techniques are used to the extent deemed necessary to assure product performance over the specified temperature range. Product may not necessarily be tested across the full temperature range and all parameters may not necessarily be tested. In the absence of specific parametric testing, product performance is assured by characterization and/or design. VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; TA = -55°C to +125°C; TA = 25°C for typical (TYP) value; unless otherwise noted. DC specifications tested with the output unloaded. Linearity is tested using a reduced code range: Code 115 to Code 3981. Guaranteed monotonic by design over all code. Lower dead band exits only if offset error is negative. Guaranteed by design and characterization, not production test. For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and offsets plus gain error must be positive. Measurement of the minimum and maximum. V drive capability of the output amplifier. IDD specification is valid for all DAC codes; interface inactive; load currents excluded. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12628 PAGE 6 Case X e b 10 PLS 6 10 E E1 PIN 1 INDEX AREA 5 D A2 0°-6° A c SEATING PLANE A1 L Symbol A A1 A2 b c Dimensions Millimeters Symbol Min Max 0.05 0.75 0.17 0..80 1.10 0.15 0.95 0.33 0.23 D/E E1 e L Millimeters Min Max 2.90 3.10 4.65 5.15 0.50 BSC 0.40 0.80 NOTES: 1. All linear dimensions are in millimeters. 2. Falls within JEDEC MO-15-AB3. FIGURE 1. Case outline. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12628 PAGE 7 Case outline X Terminal Terminal symbol number VDD 10 Terminal number 1 2 3 4 5 VOUTA VOUTB VOUTC REFIN Terminal symbol ������� SYNC 9 8 7 6 SCLK DIN GND VOUTD FIGURE 2. Terminal connections. Terminal Number Mnemonic 1 VDD 2 VOUTA 3 VOUTB 4 VOUTC 5 REFIN 6 VOUTD 7 GND 8 DIN 9 SCLK 10 ������� SYNC Description Power supply input. This part can be operated from 2.5 V to 5.5 V and the supply can be decoupled to GND Buffered analog output voltage from DAC A. The output amplifier has rail to rail operation. Buffered analog output voltage from DAC B. The output amplifier has rail to rail operation. Buffered analog output voltage from DAC C. The output amplifier has rail to rail operation. Reference input pin for all four DACs. It is an input range from 0.25 V to VDD. Buffered analog output voltage from DAC D. The output amplifier has rail to rail operation. Ground reference point for all circuitry on the part. Serial data input. This device has a 16 bit shift register on the falling edge of the serial clock input. Data can be transferred at clock speeds up to 30 MHz. The SCLK input buffer is powered down after each writer cycle. Serial clock input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at clock speeds up to 30 MHz. The SCLK input buffer is powered down after each write cycle. Active low control input. This is the frame synchronization signal for the input data. When ������� SYNC goes low, it ������� enables the input shift register and data is transferred in on the falling edge of the foolowing 16 clocks. If SYNC th ������� acts as an interrupt and the write is taken high before 16 falling edge of SCLK. the rising edge of SYNC sequence is ignored by the device. FIGURE 3. Terminal function. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12628 PAGE 8 V DD REFIN LDAC BUFFER DAC REGISTER INPUT REGISTER STRING DAC A VOUT A BUFFER SCLK INTERFACE LOGIC SYNC DAC REGISTER INPUT REGISTER STRING DAC B VOUT B BUFFER DAC REGISTER INPUT REGISTER DIN STRING DAC C VOUT C BUFFER DAC REGISTER INPUT REGISTER POWER-ON RESET STRING DAC D VOUT D POWER-DOWN LOGIC GND FIGURE 4. Functional block diagram. t1 SCLK t8 t3 t4 t2 t7 SYNC t 5 DIN t6 DB15 D05 FIGURE 5. Serial interface timing diagram. DLA LAND AND MARITIME COLUMBUS, OHIO SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12628 PAGE 9 4. VERIFICATION 4.1 Product assurance requirements. The manufacturer is responsible for performing all inspection and test requirements as indicated in their internal documentation. Such procedures should include proper handling of electrostatic sensitive devices, classification, packaging, and labeling of moisture sensitive devices, as applicable. 5. PREPARATION FOR DELIVERY 5.1 Packaging. Preservation, packaging, labeling, and marking shall be in accordance with the manufacturer’s standard commercial practices for electrostatic discharge sensitive devices. 6. NOTES 6.1 ESDS. Devices are electrostatic discharge sensitive and are classified as ESDS class 1 minimum. 6.2 Configuration control. The data contained herein is based on the salient characteristics of the device manufacturer’s data book. The device manufacturer reserves the right to make changes without notice. This drawing will be modified as changes are provided. 6.3 Suggested source(s) of supply. Identification of the suggested source(s) of supply herein is not to be construed as a guarantee of present or continued availability as a source of supply for the item. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Vendor item drawing administrative control number 1/ Device manufacturer CAGE code Vendor part number V62/12628-01XE 24355 AD5324SRMZ-EP-RL7 1/ The vendor item drawing establishes an administrative control number for identifying the item on the engineering documentation. CAGE code 24355 DLA LAND AND MARITIME COLUMBUS, OHIO Source of supply Analog Devices 1 Technology Way P.O. Box 9106 Norwood, MA 02062-9106 SIZE A CODE IDENT NO. 16236 REV DWG NO. V62/12628 PAGE 10