INFINEON PTFA182001E

PTFA182001E
Confidential, Limited Internal Distribution
Thermally-Enhanced High Power RF LDMOS FET
200 W, 1805 – 1880 MHz
Description
The PTFA182001E is a 200-watt LDMOS FET intended for EDGE
applications from 1805 to 1880 MHz. Features include input and output
matching, and thermally-enhanced single-ended package with a
slotted flange. Manufactured with Infineon's advanced LDMOS
process, this device provides excellent thermal performance and
superior reliability.
Features
2-Tone Drive-up
VDD = 30 V, IDQ = 1600 mA,
ƒ = 1840 MHz, tone spacing = 1 MHz
45
40
Efficiency
-35
Drain Efficiency (%)
Intermodulation Distortion (dBc)
-25
-30
35
IM3
-40
30
-45
25
IM5
-50
20
-55
15
IM7
-60
5
39
41
43
45
47
49
51
53
•
Pb-free, RoHS-compliant and thermally-enhanced
package
•
Broadband internal matching
•
Typical EDGE performance at 1836.6 MHz, 30 V
- Average output power = 50 dBm
- Linear gain = 16.3 dB
- Efficiency = 37%
- EVM = 3.1%
- 400 kHz modulation = –61 dBc
- 600 kHz modulation = –76 dBc
•
Typical CW performance, 1880 MHz, 30 V
- Output power at P–1dB = 220 W
- Efficiency = 49%
•
Integrated ESD protection: Human Body Model,
Class 2 (minimum)
•
Excellent thermal stability, low HCI drift
•
Capable of handling 5:1 VSWR @ 30 V, 200 W
(CW) output power
10
-65
37
PTFA182001E
Package H-30260-2
55
Output Power, PEP (dBm)
RF Characteristics
Two-tone Measurements (tested in Infineon test fixture)
VDD = 30 V, IDQ = 1.6 A, POUT = 200 W PEP, ƒ = 1840 MHz, tone spacing = 1 MHz
Characteristic
Symbol
Min
Typ
Max
Unit
Gain
Gps
15.7
16.6
—
dB
Drain Efficiency
ηD
37
38
—
%
Intermodulation Distortion
IMD
—
–31.5
–30
dBc
All published data at TCASE = 25°C unless otherwise indicated
*See Infineon distributor for future availability.
ESD: Electrostatic discharge sensitive device—observe handling precautions!
Data Sheet
1 of 10
Rev. 01, 2008-03-12
PTFA182001E
Confidential, Limited Internal Distribution
DC Characteristics
Characteristic
Conditions
Symbol
Min
Typ
Max
Unit
Drain-Source Breakdown Voltage
VGS = 0 V, IDS = 10 mA
V(BR)DSS
65
—
—
V
Drain Leakage Current
VDS = 28 V, VGS = 0 V
IDSS
—
—
1.0
µA
Drain Leakage Current
VDS = 63 V, VGS = 0 V
IDSS
—
—
10.0
µA
On-State Resistance
VGS = 10 V, VDS = 0.1 V
RDS(on)
—
0.05
—
Ω
Operating Gate Voltage
VDS = 30 V, IDQ = 1.8 A
VGS
2.0
2.5
3.0
V
Gate Leakage Current
VGS = 10 V, VDS = 0 V
IGSS
—
—
1.0
µA
Maximum Ratings
Parameter
Symbol
Value
Unit
Drain-Source Voltage
VDSS
65
V
Gate-Source Voltage
VGS
–0.5 to +12
V
Junction Temperature
TJ
200
°C
Total Device Dissipation
PD
625
W
3.57
W/°C
Above 25°C derate by
Storage Temperature Range
TSTG
–40 to +150
°C
Thermal Resistance (TCASE = 70°C, 200 W CW)
RθJC
0.28
°C/W
Ordering Information
Type and Version
Package Type
Package Description
Marking
PTFA182001E
H-30260-2
Thermally-enhanced slotted flange, single-ended
PTFA182001E
V1
*See Infineon distributor for future availability.
Data Sheet
2 of 10
Rev. 01, 2008-03-12
PTFA182001E
Confidential, Limited Internal Distribution
Typical Performance (data taken in a production test fixture)
Broadband Performance
Power Sweep, CW Conditions
VDD = 30 V, IDQ = 1600 mA, POUT = 50 W
VDD = 30 V, IDQ = 1600 mA, ƒ = 1880 MHz
-10
Return Loss
30
-15
25
-20
Efficiency
20
-25
-30
Gain
10
1760
1800
1840
15
20
Efficiency
10
13
0
30 32 34 36 38 40 42 44 46 48 50 52 54
Frequency (MHz)
Output Power (dBm)
Intermodulation Distortion Products
vs. Tone Spacing
Edge EVM and Modulation Spectrum
vs. Quiescent Current
VDD = 30 V IDQ = 1600 mA , ƒ = 1840 MHz,
POUT = 53 dBm PEP
VDD = 30 V, ƒ = 1836.6 MHz, POUT = 50 dBm
-10
EVM RMS (avg. %) .
Intermodulation Distortion (dBc)
0
-20
3rd Order
-30
5th
-40
7th
-50
30
Gain
14
-35
1920
1880
16
40
3.6
-10
3.4
-20
3.2
-30
3.0
-40
EVM
2.8
400 kHz
2.6
-60
2.4
-70
2.2
600 kHz
2.0
-60
0
5
10
15
20
25
30
35
1.4
40
1.5
1.6
1.7
1.8
1.9
-80
-90
2.0
Quiescent Current (A)
Tone Spacing (MHz)
Data Sheet
-50
Modulation Spectrum (dBc)
15
17
Gain (dB)
35
50
TCASE = 25°C
TCASE = 90°C
Drain Efficiency (%)
18
-5
Input Return Loss (dB)
Gain (dB), Efficiency (%)
40
3 of 10
Rev. 01, 2008-03-12
PTFA182001E
Confidential, Limited Internal Distribution
Typical Performance (cont.)
EDGE EVM Performance
EDGE Modulation Spectrum Performance
VDD = 30 V, IDQ = 1600 mA, ƒ = 1836.6 MHz
VDD = 30 V, IDQ = 1600 mA, ƒ = 1836.6 MHz
50
Efficiency
40
3
30
2
20
1
10
Drain Efficiency (%)
EVM RMS (avg. %) .
4
Modulation Spectrum (dBc)
-40
EVM
0
36
38
40
42
44
46
48
50
Efficiency
-50
40
-60
400 kHz
30
-70
600 kHz
20
-80
10
-90
0
34
50
0
34
52
36
EDGE Modulation Spectrum Performance
40
42
44
46
48
50
-40
VDD = 30 V, IDQ = 1600 mA, ƒ = 1880 MHz,
single-carrier WCDMA input PAR = 7.5 dB
50
100
Input
Efficiency
-70
600 kHz
30
20
-80
10
-90
36
38
40
42
44
46
48
50
50.0 dBm
1
50.5 dBm
52.0 dBm
0.1
0.001
52
1
Output Power (dBm)
Data Sheet
48.0 dBm
0.01
0
34
46.0 dBm
10
Probability (%)
40
Drain Efficiency (%)
-50
-60
52
Output Peak-to-Average Ratio Compression
(PARC) at various Power levels
VDD = 30 V, IDQ = 1600 mA, ƒ = 1879.8 MHz
Modulation Spectrum (dBc)
38
Output Power, avg. (dBm)
Output Power, avg. (dBm)
400 kHz
Drain Efficiency (%)
5
2
3
4
5
6
7
8
Peak-to-Average (dB)
4 of 10
Rev. 01, 2008-03-12
PTFA182001E
Confidential, Limited Internal Distribution
Typical Performance (cont.)
Power Sweep (CW) over Temperature
Voltage Sweep
VDD = 30 V, IDQ = 1600 mA, ƒ = 1880 MHz
IDQ = 1600 mA, ƒ = 1840 MHz, tone spacing = 1 MHz,
Output Power (PEP) = 53 dBm
-10
3rd Order IMD (dBc)
17
Power Gain (dB)
50
-15°C
16
25°C
15
85°C
14
13
Efficiency
-20
40
IM3 Up
-30
30
-40
20
Gain
12
-50
1
10
100
1000
10
23
25
27
29
31
Gain (dB), Drain Efficiency (%)
18
33
Output Power (W)
Supply Voltage (V)
Bias Voltage vs. Temperature
Normalized Bias Voltage (V)
Voltage normalized to typical gate voltage,
series show current
1.03
0.44 A
1.02
1.32 A
1.01
2.20 A
3.30 A
1.00
6.61 A
0.99
9.91 A
0.98
0.97
0.96
0.95
-20
0
20
40
60
80
100
Case Temperature (°C)
Data Sheet
5 of 10
Rev. 01, 2008-03-12
PTFA182001E
Confidential, Limited Internal Distribution
Broadband Circuit Impedance
R-
0. 2
Z0 = 50 Ω
D
Z Load
0 .1
Z Source
Z Load
R
jX
R
jX
1770
11.72
–4.39
1.22
1.17
1800
11.45
–4.87
1.17
1.44
1840
10.97
–5.48
1.15
1.78
1880
10.33
–5.99
1.08
2.08
1910
9.76
–6.27
1.04
2.35
0.3
Z Source
1910 MHz
1770 MHz
0.1
<---
MHz
0.1
0.0
D-
Z Load Ω
D L OA
S T OW AR
NGT H
Z Source Ω
Frequency
1910 MHz
EL E
W AV
S
0.2
1770 MHz
G
0. 2
See next page for circuit information
Data Sheet
6 of 10
Rev. 01, 2008-03-12
PTFA182001E
Confidential, Limited Internal Distribution
Reference Circuit (cont.)
C1
0.001µF
R2
1.3K V
R1
1.2K V
QQ1
LM7805
VDD
Q1
BCP56
C2
0.001µF
C3
0.001µF
R3
510 V
L1
R8
2K V
VDD
C6
10pF
C5
0.1µF
C4
4.7µF
16V
R5
510 V
C13
10pF
C15
1µF
C14
1µF
C16
2.2µF
C17
0.1µF
l9
C18
100µF
50V
l11
R6
10 V
C25
1.4pF
DUT
J1
l1
C7
0.6pF
l3
l2
C8
10pF
l4
l5
l6
l7
l13
l8
R7
10 V
C9
1.5pF
l12
l14
C27
10pF
l15
C11
0.1µF
l17
l18
J2
C28
0.2pF
l10
C10
4.7µF
16V
l16
C26
1.4pF
L2
C12
10pF
C19
10pF
C20
1µF
C21
1µF
C22
2.2µF
C23
0.1µF
C24
100µF
50V
Reference circuit schematic for ƒ = 1840 MHz
Circuit Assembly Information
DUT
PCB
PTFA182001E
0.76 mm [.030"] thick, εr = 3.48
LDMOS Transistor
Rogers RO4350
1 oz. copper
Microstrip
Electrical Characteristics at 1840 MHz
Dimensions: L x W (mm)
Dimensions: L x W (in.)
l1
l2
l3
l4
l5
l6 (taper)
l7
l8
l9, l10
l11, l12
l13
l14 (taper)
l15 (taper)
l16
l17
l18
0.056 λ, 50.2 Ω
0.024 λ, 50.2 Ω
0.051 λ, 50.2 Ω
0.050 λ, 50.2 Ω
0.019 λ, 42.8 Ω
0.054 λ, 42.8 Ω./ 6.9 Ω
0.040 λ, 6.9 Ω
0.021 λ, 6.9 Ω
0.186 λ, 59.1 Ω
0.328 λ, 50.7 Ω
0.062 λ, 5.0 Ω
0.043 λ, 5.0 Ω./ 15.1 Ω
0.021 λ, 15.1 Ω./ 41.2 Ω
0.026 λ, 41.2 Ω
0.095 λ, 50.2 Ω
0.072 λ, 50.2 Ω
5.54 x 1.68
2.39 x 1.68
5.00 x 1.68
4.93 x 1.68
1.88 x 2.16
5.23 x 2.16 / 20.32
3.63 x 20.32
1.85 x 20.32
18.59 x 1.27
32.39 x 1.65
5.51 x 28.83
3.84 x 28.83 / 8.43
1.96 x 8.43 / 2.29
2.49 x 2.29
9.42 x 1.68
7.11 x 1.68
0.218 x 0.066
0.094 x 0.066
0.197 x 0.066
0.194 x 0.066
0.074 x 0.085
0.206 x 0.085 / 0.800
0.143 x 0.800
0.073 x 0.800
0.732 x 0.050
1.275 x 0.065
0.217 x 1.135
0.151 x 1.135 / 0.332
0.077 x 0.332 / 0.090
0.098 x 0.090
0.371 x 0.066
0.280 x 0.066
Data Sheet
7 of 10
Rev. 01, 2008-03-12
PTFA182001E
Confidential, Limited Internal Distribution
Reference Circuit (cont.)
GND
VDD
Reference circuit assembly diagram* (not to scale)
Component
Description
Suggested Manufacturer
P/N or Comment
C1, C2, C3
C4, C10
C5, C11, C17, C23
C6, C12
C7
C8, C13, C19, C27
C9
C14, C15, C20, C21
C16, C22
C18, C24
C25, C26
C28
L1, L2
Q1
QQ1
R1
R2
R3, R5
R4
R6, R7
R8
Capacitor, 0.001 µF
Capacitor, 4.7 µF, 16 V
Capacitor, 0.1 µF
Capacitor, 10 pF AVX
Ceramic capacitor, 0.6 pF
Ceramic capacitor, 10 pF
Ceramic capacitor, 1.5 pF
Ceramic capacitor, 1 µF
Capacitor, 2.2 µF
Electrolytic capacitor, 100 µF, 50 V
Ceramic capacitor, 1.4 pF
Ceramic capacitor, 0.2 pF
Ferrite, 8.9 mm
Transistor
Voltage regulator
Chip resistor 1.2k ohms
Chip resistor 1.3k ohms
Chip resistor 510 ohms
Not used
Chip resistor 10 ohms
Potentiometer, 2 k-ohms
Digi-Key
Digi-Key
Digi-Key
Garrett Electronics
ATC
ATC
ATC
Digi-Key
Digi-Key
Digi-Key
ATC
ATC
Elna Magnetics
Infinion Technologies
National Semiconductor
Digi-Key
Digi-Key
Digi-Key
PCC1772CT-ND
PCS3475CT-ND
PCC104BCT-ND
08051J100GBTTR
100B 0R6
100B 100
100B 1R5
445-1411-2-ND
445-1447-2-ND
PCE3718CT-ND
100B 1R4
100A 0R2
BDS 4.6/3/8.9-4S2
BCP56
LM7805
P1.2KGCT-ND
P1.3KGCT-ND
P510ECT-ND
Digi-Key
Digi-Key
P10ECT-ND
3224W-202ETR-ND
*Gerber Files for this circuit available on request
Data Sheet
8 of 10
Rev. 01, 2008-03-12
PTFA182001E
Confidential, Limited Internal Distribution
Package Outline Specifications
Package H-30260-2
45° X 2.03
[.080]
2X 12.70
[.500]
4X R 1.52
[.060]
C
L
D
(2X 4.83±0.50
[.190±.020])
S
LID 13.21 +0.10
–0.15
+.004
[.520 –.006]
2X 3.25
[.128]
C
L
FLANGE 13.72
[.540]
23.37±0.51
[.920±.020]
2X 1.63
[.064] R
G
27.94
[1.100]
SPH 1.57
[.062]
22.35±0.23
[.880±.009]
C
L
4.11±0.38
[.162±.015]
0.0381 [.0015] -A-
1.02
[.040]
2 6 0 -c a s e s _ 3 0 2 6 0 3
/ -1 1 -0 8
34.04
[1.340]
Diagram Notes—unless otherwise specified:
1. Lead thickness: 0.10 +0.051/–0.025 [.004 +.002/–.001].
2. All tolerances ± 0.127 [.005] unless specified otherwise.
3. Pins: D = drain, S = source, G = gate.
4. Interpret dimensions and tolerances per ASME Y14.5M-1994.
5. Primary dimensions are mm. Alternate dimensions are inches.
6. Gold plating thickness:
S - flange: 2.54 micron [100 microinch] (min)
D, G - leads: 1.14 ± 0.38 micron [45 ± 15 microinch]
Find the latest and most complete information about products and packaging at the Infineon Internet page
http://www.infineon.com/rfpower
Data Sheet
9 of 10
Rev. 01, 2008-03-12
PTFA182001E
Confidential, Limited Internal Distribution
Revision History:
2008-03-12
none
Previous Version:
Data Sheet
Page
Subjects (major changes since last revision)
1, 3, 9, 10
Update to product V4, with new package technologies. Update package outline diagrams.
We Listen to Your Comments
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Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
[email protected]
To request other information, contact us at:
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or +1 408 776 0600 International
GOLDMOS® is a registered trademark of Infineon Technologies AG.
Edition 2008-03-12
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2006 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and
liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any
third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com/rfpower).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of
that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices
or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect
human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Data Sheet
10 of 10
Rev. 01, 2008-03-12