Product Overview NBSG14: SiGe Clock / Data Fanout Buffer, 1:4 Differential, 2.5 V / 3.3 V, with RSECL Outputs For complete documentation, see the data sheet Product Description The NBSG14 is a 1-to-4 clock/data distribution chip, optimized for ultra-low skew and jitter. Inputs incorporate internal 50-ohm termination resistors and accept </bR>NECL (Negative ECL), PECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV. Features • • • • • • • • • Maximum Input Clock Frequency up to 12 GHz Maximum Input Data Rate up to 12 Gb/s Typical 50 Ω Internal Input Termination Resistors 30 ps Typical Rise and Fall Times 125 ps Typical Propagation Delay RSPECL Output with Operating Range: V<subCC</sub> = 2.375 V to 3.465 V with VEE = 0 V RSNECL Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V RSECL Output Level (400 mV Peak-to-Peak Output), Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices End Products Part Electrical Specifications Product Compliance Status Type Chann els Input / Input Output Level Ratio Output VCC Level Typ (V) tJitterR MS Typ (ps) tskew(oo) Max (ps) tpd Typ (ns) tR & tF Max (ps) fmaxClo fmaxDat Packa ck Typ a Typ ge (MHz) (Mbps) Type NBSG14MNG Pb-free Active Buffer 1 1:4 ECL 0.2 15 0.125 55 12000 12000 QFN16 0.2 15 0.125 55 12000 12000 QFN16 0.2 15 0.125 55 12000 12000 QFN16 Halide free CML LVD S 2.5 3.3 TTL CMO S ECL NBSG14MNHTBG Pb-free Active Buffer 1 1:4 Halide free LVD S ECL 2.5 3.3 TTL CML CMO S ECL NBSG14MNR2G Pb-free Halide free Active Buffer 1 1:4 LVD S ECL 3.3 2.5 TTL ECL CML CMO S For more information please contact your local sales support at www.onsemi.com Created on: 6/30/2016