NBSG16 Product Preview 2.5V / 3.3VSiGe Differential Receiver/Driver with RSECL* Outputs http://onsemi.com *Reduced Swing ECL The SG16 is a Silicon Germanium differential receiver/driver. The device is functionally equivalent to the EP16 and LVEP16 devices with much higher bandwidth and lower EMI capabilities. Inputs contain internal 50 termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), HSTL, GTL, TTL, CMOS, CML, or LVDS. Outputs are RSECL (Reduced Swing ECL), 400 mV. For LVDS, CML, or CMOS outputs, use the device product numbers NBSGL16, NBSGM16, or NBSGC16. The VBB and VMM pins are internally generated voltage supplies available to this device only. The VBB is used for single–ended NECL or PECL inputs and the VMM pin is used for CMOS inputs. For all single–ended input conditions, the unused differential input is connected to VBB or VMM as a switching reference voltage. VBB or VMM may also rebias AC coupled inputs. When used, decouple VBB and VMM via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB and VMM outputs should be left open. • Maximum Frequency > 12 GHz Typical • 40 ps Typical Rise and Fall Times • RSPECL Output with RSPECL, PECL, HSTL, GTL, TTL, CMOS, • • • • • • • • • • • CML, or LVDS Inputs with Operating Range: VCC = 2.375 V to 3.6 V with VEE = 0 V RSNECL Output with RSNECL or NECL Inputs with Operating Range: VCC = 0 V with VEE = –2.375 V to –3.6 V RSECL Output Level (400 mV Peak–to–Peak Output), Differential Output Only 75 k Pulldown Resistor on D and D, 36.5 k Pullup Resistor on D MARKING DIAGRAM* SG 16 LYW BGA–16 BA SUFFIX CASE 489 L = Wafer Lot Y = Year W = Work Week *For additional information, refer to Application Note AND8002/D ORDERING INFORMATION Device Package Shipping NBSG16BA 4x4 BGA–16 810 Units/Tray NBSG16BAR2 4x4 BGA–16 2500 Tape & Reel 50 Internal Input Resistors Compatible with Existing 2.5 V/3.3 V LVEP, EP, and LVEL Devices ESD Protection: (TBD) VBB and VMM Reference Voltage Output Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test (TBD) Moisture Sensitivity Level 3: ASE Requires Drypack Flammability Rating: TBD Transistor Count: 167 Devices This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. Semiconductor Components Industries, LLC, 2001 June, 2001 – Rev. 0 1 Publication Order Number: NBSG16/D NBSG16 1 2 3 4 A VEE NC NC VEE B D VTD VCC Q C D D VTD VEE VCC VBB PIN DESCRIPTION Q VMM VEE PIN FUNCTION D*, D** ECL, HSTL, GTL, TTL, CMOS. CML, LVDS compatible inputs Q, Q RSECL Data Outputs VTD 50 Internal Input Termination Resistor VTD 50 Internal Input Termination Resistor VMM CMOS Reference Voltage Output, VCC/2 VBB ECL Reference Voltage Output VCC Positive Supply VEE Negative Supply NC No Connect * Pin will default low when left open. ** Pin will default to a slightly higher potential than D when both are left open. VCC (B3, C3) Figure 1. Pinout (Top View) (B2) VTD VMM (D3) 36.5 50 (B1) D Q (B4) (C1) D Q (C4) 50 75 75 (C2) VTD VBB (D2) VEE (A1, A4, D1, D4) Figure 2. Logic Diagram MAXIMUM RATINGS (Note 1.) Symbol Parameter Condition 1 Condition 2 Rating Units VCC Positive Power Supply VEE = 0 V 3.8 V VEE Negative Power Supply VCC = 0 V –3.8 V VI Positive Input In ut Negative Input VEE = 0 V VCC = 0 V 3.8 –3.8 V V Iout Output Current Continuous Surge 25 50 mA mA IBB VBB Sink/Source 1 mA IMM VMM Sink/Source 1 mA TA Operating Temperature Range –40 to +85 °C Tstg Storage Temperature Range –65 to +150 °C θJA Thermal Resistance (Junction to Ambient) 0 LFPM 500 LFPM 16 BGA 16 BGA 149 127 °C/W °C/W θJC Thermal Resistance (Junction to Case) std bd 16 BGA TBD °C/W Tsol Wave Solder TBD 265 °C 1. Maximum Ratings are those values beyond which device damage may occur. http://onsemi.com 2 VI VCC VI VEE NBSG16 DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 2.5 V; VEE = 0 V (Note 2.) –40°C Symbol Characteristic IEE Power Supply Current VOH Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit 25 mA Output HIGH Voltage (Note 3.) 1400 mV VOL Output LOW Voltage (Note 3.) 1000 mV VBB PECL Output Voltage Reference 1200 VIHCMR Input HIGH Voltage Common Mode Range (Note 4.) VMM CMOS Output Voltage Reference RT Internal Termination Resistor IIH Input HIGH Current IIL Input LOW Current 1.2 2.5 1.2 VCC/2 2.5 0.5 –150 2.5 V 1250 mV 50 Ω 150 D D 1.2 150 0.5 –150 150 µA µA 0.5 –150 NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.125 V to –1.1 V. 3. All loading with 50 ohms to VCC–2.0 volts. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. DC CHARACTERISTICS, INPUT WITH RSPECL OUTPUT VCC = 3.3 V; VEE = 0 V (Note 5.) –40°C Symbol Characteristic IEE Power Supply Current VOH Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit 25 mA Output HIGH Voltage (Note 6.) 2200 mV VOL Output LOW Voltage (Note 6.) 1800 mV VBB PECL Output Voltage Reference 2000 VIHCMR Input HIGH Voltage Common Mode Range (Note 7.) VMM CMOS Output Voltage Reference RT Internal Termination Resistor IIH Input HIGH Current IIL Input LOW Current 1.2 3.3 1.2 VCC/2 150 D D 0.5 –150 3.3 1.2 V 1650 mV 50 Ω 150 0.5 –150 3.3 150 0.5 –150 µA µA NOTE: SiGe Circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 5. Input and output parameters vary 1:1 with VCC. VEE can vary +0.925 V to –0.3 V. 6. All loading with 50 ohms to VCC–2.0 volts. 7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 3 NBSG16 DC CHARACTERISTICS, NECL OR RSNECL INPUT WITH NECL OUTPUT VCC = 0 V; VEE = –3.6 V to –2.375 V (Note 8.) –40°C Symbol Characteristic IEE Power Supply Current VOH Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit 25 mA Output HIGH Voltage (Note 9.) –1100 mV VOL Output LOW Voltage (Note 9.) –1500 mV VBB NECL Output Voltage Reference –1300 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 10.) VMM CMOS Output Voltage Reference IIH Input HIGH Current IIL Input LOW Current VEE+1.2 0.0 VEE+1.2 0.0 VEE+1.2 0.0 VEE/2 150 D D 0.5 –150 V mV 150 0.5 –150 150 µA µA 0.5 –150 NOTE: SiGe circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 8. Input and output parameters vary 1:1 with VCC. 9. All loading with 50 ohms to VCC –2.0 volts. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. AC CHARACTERISTICS VCC = 0 V; VEE = –3.6 V to –2.375 V or VCC = 2.375 V to 3.6 V; VEE = 0 V –40°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit fmax Maximum Frequency (See Figure 3. Fmax/JITTER) (Note 11.) > 12 GHz tPLH, tPHL Propagation Delay to Output Differential 150 ps tSKEW Duty Cycle Skew (Note 12.) TBD ps tJITTER Cycle–to–Cycle Jitter (See Figure 3. Fmax/JITTER) (Note 11.) TBD ps VPP Input Voltage Swing 400 mV tr tf Output Rise/Fall Times (20% – 80%) 40 ps P to P 150 Q, Q 11. Measured using a 400 mV source, 50% duty cycle clock source. All loading with 50 ohms to V CC–2.0 V. 12. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. http://onsemi.com 4 900 9 800 8 700 7 600 6 500 TBD 5 400 4 300 3 200 2 100 1 JITTEROUT ps (RMS) VOUTpp (mV) NBSG16 ÉÉ ÉÉ 0 0 2000 4000 6000 8000 10000 12000 FREQUENCY (MHz) Figure 3. Fmax/Jitter Q D Receiver Device Driver Device Qb Db 50 50 V TT V TT = V CC – 2.0 V Figure 4. Typical Termination for Output Driver and Device Evaluation (Refer to Application Note AND8020 – Termination of ECL Logic Devices) Resource Reference of Application Notes AN1404 – ECLinPS Circuit Performance at Non–Standard VIH Levels AN1405 – ECL Clock Distribution Techniques AN1406 – Designing with PECL (ECL at +5.0 V) AN1504 – Metastability and the ECLinPS Family AN1568 – Interfacing Between LVDS and ECL AN1650 – Using Wire–OR Ties in ECLinPS Designs AN1672 – The ECL Translator Guide AND8001 – Odd Number Counters Design AND8002 – Marking and Date Codes AND8009 – ECLinPS Plus Spice I/O Model Kit AND8020 – Termination of ECL Logic Devices For an updated list of Application Notes, please see our website at http://onsemi.com. http://onsemi.com 5 NBSG16 PACKAGE DIMENSIONS BGA–16 BA SUFFIX PLASTIC 4 X 4 BGA FLIP CHIP PACKAGE CASE 489 ISSUE O LASER MARK FOR PIN 1 IDENTIFICATION IN THIS AREA –X– D M –Y– K E M 0.20 3X e 4 3 2 FEDUCIAL FOR PIN A1 IDENTIFICATION IN THIS AREA 1 A 3 B b 16 X C D S VIEW M–M 0.15 M Z X Y 0.08 M Z 5 0.15 Z A A2 A1 16 X 4 –Z– 0.10 Z DETAIL K ROTATED 90 CLOCKWISE http://onsemi.com 6 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. DIM A A1 A2 b D E e S MILLIMETERS MIN MAX 1.40 MAX 0.25 0.35 1.20 REF 0.30 0.50 4.00 BSC 4.00 BSC 1.00 BSC 0.50 BSC NBSG16 Notes http://onsemi.com 7 NBSG16 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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