INTEGRATED CIRCUITS DATA SHEET 74AHC74; 74AHCT74 Dual D-type flip-flop with set and reset; positive-edge trigger Product specification Supersedes data of 1999 Aug 05 File under Integrated Circuits, IC06 1999 Sep 23 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V 74AHC74; 74AHCT74 QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. TYPICAL SYMBOL PARAMETER CONDITIONS tPHL/tPLH propagation delay CL = 15 pF; VCC = 5 V • Balanced propagation delays nCP to nQ, nQ • Inputs accepts voltages higher than VCC nSD, nRD to nQ, nQ • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input levels • Output capability: standard • ICC category: flip-flops • Specified from −40 to +85 and +125 °C. UNIT AHC AHCT 3.7 3.3 ns 3.7 3.7 ns 130 100 MHz fmax max. clock frequency CI input capacitance VI = VCC or GND 4.0 4.0 pF CPD power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 16 pF 12 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; DESCRIPTION The 74AHC/AHCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT74 dual positive-edge triggered, D-type flip-flops with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. FUNCTION TABLES Table 1 See note 1 INPUT OUTPUT nSD nRD nCP nD nQ nQ L H X X H L H L X X L H L L X X H H Table 2 See note 1 INPUT OUTPUT nSD nRD nCP nD nQn+1 nQn+1 H H ↑ L L H H H ↑ H H L Note to Tables 1 and 2 1. H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH CP transition; Qn+1 = state after the next LOW-to-HIGH CP transition. 1999 Sep 23 2 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74AHC74; 74AHCT74 ORDERING INFORMATION PACKAGE OUTSIDE NORTH AMERICA NORTH AMERICA TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE −40 to +85 °C 14 SO plastic SOT108-1 74AHC74D 74AHC74D 74AHC74PW 74AHC74PW DH 14 TSSOP plastic SOT402-1 74AHCT74D 74AHCT74D 14 SO plastic SOT108-1 74AHCT74PW 74AHCT74PW DH 14 TSSOP plastic SOT402-1 PINNING PIN SYMBOL DESCRIPTION 1 and 13 1RD and 2RD asynchronous reset-direct input (active LOW) 2 and 12 1D and 2D data inputs 3 and 11 1CP and 2CP clock input (LOW-to-HIGH, edge-triggered) 4 and 10 1SD and 2SD asynchronous set-direct input (active LOW) 5 and 9 1Q and 2Q true flip-flop outputs 6 and 8 1Q and 2Q complement flip-flop outputs 7 GND ground (0 V) 14 VCC DC supply voltage handbook, halfpage 1RD 1 1D 2 13 2RD 1CP 3 12 2D 1SD 4 1Q 5 10 2SD 1Q 6 9 GND 7 8 2Q 74 4 10 handbook, halfpage 14 VCC 1SD 2SD 2 12 3 11 11 2CP 2Q SD 1Q 1D Q D 2D 2Q 1CP CP 2CP FF 1Q Q 2Q RD 6 8 1RD 2RD 1 13 MNA417 Fig.1 Pin configuration. 1999 Sep 23 5 9 MNA418 Fig.2 Logic diagram. 3 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74AHC74; 74AHCT74 handbook, halfpage 4 2 handbook, halfpage 4 3 2 1 S 3 5 11 12 13 1D 1CP SD Q D FF Q 1D 5 1Q 6 RD 6 R 10 S 1Q CP C1 1 10 1SD 1RD 2SD 9 C1 1D 12 8 R 11 2D 2CP SD Q D 9 CP FF MNA419 2Q Q 2Q 8 RD 13 Fig.3 IEC logic symbol. 2RD MNA420 Fig.4 Functional diagram. handbook, full pagewidth Q C C C C C C D Q C C RD SD CP MNA421 C C Fig.5 Logic diagram (one flip-flop). 1999 Sep 23 4 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74AHC74; 74AHCT74 RECOMMENDED OPERATING CONDITIONS 74AHC SYMBOL PARAMETER 74AHCT CONDITIONS UNIT MIN. TYP. MAX. MIN. TYP. MAX. 4.5 5.0 5.5 V VCC DC supply voltage 2.0 5.0 5.5 VI input voltage 0 − 5.5 0 − 5.5 V VO output voltage 0 − VCC 0 − VCC V Tamb operating ambient temperature −40 +25 +85 −40 +25 +85 °C −40 +25 +125 −40 +25 +125 °C tr,tf (∆t/∆f) input rise and fall rates see DC and AC characteristics per device VCC = 3.3 V ±0.3 V − − 100 − − − VCC = 5 V ±0.5 V − 20 − − 20 − ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC DC supply voltage −0.5 +7.0 V VI input voltage −0.5 +7.0 V IIK DC input diode current VI < −0.5 V; note 1 − −20 mA VO < −0.5 V or VO > VCC + 0.5 V; note 1 IOK DC output diode current − ±20 mA IO DC output source or sink current −0.5 V < VO < VCC + 0.5 V − ±25 mA ICC DC VCC or GND current − ±75 mA Tstg storage temperature PD power dissipation per package for temperature range: −40 to +85 °C; note 2 −65 +150 °C − 500 Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO packages: above 70 °C the value of PD derates linearly with 8 mW/K. For TSSOP packages: above 60 °C the value of PD derates linearly with 5.5 mW/K. 1999 Sep 23 5 mW Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74AHC74; 74AHCT74 DC CHARACTERISTICS 74AHC family Over recommended operating conditions; voltage are referenced to GND (ground = 0 V). Tamb (°C) TEST CONDITIONS SYMBOL OTHER VIH VIL VOH VOL −40 to +85 25 PARAMETER HIGH-level input voltage LOW-level input voltage VCC (V) −40 to +125 UNIT MIN. TYP. MAX. MIN. MAX. MIN. MAX. 2.0 1.5 − − 1.5 − 1.5 − 3.0 2.1 − − 2.1 − 2.1 − 5.5 3.85 − − 3.85 − 3.85 − 2.0 − − 0.5 − 0.5 − 0.5 3.0 − − 0.9 − 0.9 − 0.9 5.5 − − 1.65 − 1.65 − 1.65 2.0 1.9 2.0 − 1.9 − 1.9 − 3.0 2.9 3.0 − 2.9 − 2.9 − 4.5 4.4 4.5 − 4.4 − 4.4 − V V HIGH-level output voltage; all outputs VI = VIH or VIL; IO = −50 µA V HIGH-level output voltage VI = VIH or VIL; IO = −4.0 mA 3.0 2.58 − − 2.48 − 2.40 − VI = VIH or VIL; IO = −8.0 mA 4.5 3.94 − − 3.8 − 3.70 − LOW-level output voltage; all outputs VI = VIH or VIL; IO = 50 µA 2.0 − 0 0.1 − 0.1 − 0.1 3.0 − 0 0.1 − 0.1 − 0.1 4.5 − 0 0.1 − 0.1 − 0.1 LOW-level output voltage VI = VIH or VIL; IO = 4 mA 3.0 − − 0.36 − 0.44 − 0.55 VI = VIH or VIL; IO = 8 mA 4.5 − − 0.36 − 0.44 − 0.55 − 1.0 − 2.0 ±2.5 − ±10.0 µA V V V II input leakage current VI = VCC or GND 5.5 − − 0.1 IOZ 3-state output OFF current VI = VIH or VIL; 5.5 VO = VCC or GND − − ±0.25 − ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 2.0 − 20 − 40 µA CI input capacitance − − 3 10 − 10 − 10 pF 1999 Sep 23 6 µA Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74AHC74; 74AHCT74 74AHCT family Over recommended operating conditions; voltage are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL Tamb (°C) PARAMETER −40 to +85 25 OTHER VCC (V) −40 to +125 UNIT MIN. TYP. MAX. MIN. MAX. MIN. MAX. VIH HIGH-level input voltage 4.5 to 5.5 2.0 − − 2.0 − 2.0 − V VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 − 0.8 − 0.8 V VOH HIGH-level output voltage; all outputs VI = VIH or VIL; IO = −50 µA 4.5 4.4 4.5 − 4.4 − 4.4 − V HIGH-level output voltage VI = VIH or VIL; IO = −8.0 mA 4.5 3.94 − − 3.8 − 3.70 − V LOW-level output voltage; all outputs VI = VIH or VIL; IO = 50 µA 4.5 − 0 0.1 − 0.1 − 0.1 V LOW-level output voltage VI = VIH or VIL; IO = 8 mA 4.5 − − 0.36 − 0.44 − 0.55 V II input leakage current VI = VIH or VIL 5.5 − − 0.1 − 1.0 − 2.0 µA IOZ 3-state output OFF current VI = VIH or VIL; 5.5 VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 − − ±0.25 − ±2.5 − ±10.0 µA ICC quiescent supply current VI = VCC or GND; 5.5 IO = 0 − − 2.0 − 20 − 40 µA ∆ICC additional quiescent supply current per input pin VI = VCC − 2.1 V other inputs at VCC or GND; IO = 0 4.5 to 5.5 − − 1.35 − 1.5 − 1.5 mA CI input capacitance − 3 10 − 10 − 10 pF VOL 1999 Sep 23 − 7 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74AHC74; 74AHCT74 AC CHARACTERISTICS Type 74AHC74 GND = 0 V; tr = tf ≤ 3.0 ns. Tamb (°C) TEST CONDITIONS SYMBOL −40 to +85 25 PARAMETER WAVEFORMS CL MIN. TYP. −40 to +125 UNIT MAX. MIN. MAX. MIN. MAX. VCC = 3.0 to 3.6 V; note 1 see Figs 6 and 8 15 pF − 5.2 11.9 1.0 14.0 1.0 15.0 ns propagation delay see Figs 7 and 8 nSD nRD to nQ, nQ − 5.4 12.3 1.0 14.5 1.0 15.5 ns fmax maximum clock pulse frequency 80 125 − 45 − 45 − ns tPHL/tPLH propagation delay nCP to nQ, nQ tPHL/tPLH tW propagation delay nCP to nQ, nQ see Figs 6 and 8 50 pF − 7.4 15.4 1.0 17.5 1.0 19.5 ns propagation delay see Figs 7 and 8 nSD nRD to nQ, nQ − 7.7 15.8 1.0 18.0 1.0 20.0 ns clock pulse width HIGH or LOW see Figs 6 and 8 6.0 − − 7.0 − 7.0 − ns set or reset pulse width LOW see Figs 7 and 8 6.0 − − 7.0 − 7.0 − ns 5.0 − − 5.0 − 5.0 − ns 6.0 − − 7.0 − 7.0 − ns trem removal time set or reset tsu set-up time nD to nCP th hold time nD to nCP 0.5 − − 0.5 − 0.5 − ns fmax maximum clock pulse frequency 50 75 − 70 − 70 − ns 1999 Sep 23 see Figs 6 and 8 8 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74AHC74; 74AHCT74 TEST CONDITIONS SYMBOL Tamb (°C) PARAMETER −40 to +85 25 WAVEFORMS CL MIN. TYP. −40 to +125 UNIT MAX. MIN. MAX. MIN. MAX. VCC = 4.5 to 5.5 V; note 2 see Figs 6 and 8 15 pF − 3.7 7.3 1.0 8.5 1.0 9.5 ns propagation delay see Figs 7 and 8 nSD nRD to nQ, nQ − 3.7 7.7 1.0 9.0 1.0 10.0 ns fmax maximum clock pulse frequency 130 170 − 110 − 110 − ns tPHL/tPLH propagation delay nCP to nQ, nQ see Figs 6 and 8 50 pF − 5.2 9.3 1.0 10.5 1.0 12.0 ns propagation delay nSD to nQ, nQ see Figs 7 and 8 − 5.3 9.7 1.0 11.0 1.0 12.5 ns clock pulse width HIGH or LOW see Figs 6 and 8 5.0 − − 5.0 − 5.0 − ns set or reset pulse width LOW see Figs 7 and 8 5.0 − − 5.0 − 5.0 − ns 3.0 − − 3.0 − 3.0 − ns 5.0 − − 5.0 − 5.0 − ns tPHL/tPLH tW propagation delay nCP to nQ, nQ trem removal time set or reset tsu set-up time nD to nCP th hold time nD to nCP 0.5 − − 0.5 − 0.5 − ns fmax maximum clock pulse frequency 90 115 − 75 − 75 − ns see Figs 6 and 8 Notes 1. Typical values at VCC = 3.3 V. 2. Typical values at VCC = 5.0 V. 1999 Sep 23 9 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74AHC74; 74AHCT74 Type 74AHCT74 GND = 0 V; tr = tf ≤ 3.0 ns. TEST CONDITIONS SYMBOL Tamb (°C) PARAMETER −40 to +85 25 WAVEFORMS CL MIN. TYP. −40 to +125 UNIT MAX. MIN. MAX. MIN. MAX. VCC = 4.5 to 5.5 V; note 1 see Figs 6 and 8 15 pF − 3.3 7.8 1.0 9.0 1.0 10.0 ns propagation delay see Figs 7 and 8 nSD nRD to nQ, nQ − 3.7 10.4 1.0 12.0 1.0 13.0 ns fmax maximum clock pulse frequency 100 160 − 80 − 80 − ns tPHL/tPLH propagation delay nCP to nQ, nQ tPHL/tPLH propagation delay nCP to nQ, nQ see Figs 6 and 8 50 pF − 4.8 8.8 1.0 10.0 1.0 11.0 ns propagation delay see Figs 7 and 8 nSD nRD to nQ, nQ − 5.3 11.4 1.0 13.0 1.0 14.5 ns tW clock pulse width HIGH or LOW see Figs 6 and 8 5.0 − − 5.0 − 5.0 − ns tW(st)(rst) set or reset pulse width LOW see Figs 7 and 8 5.0 − − 5.0 − 5.0 − ns trem removal time set or reset 3.5 − − 3.5 − 3.5 − ns tsu set-up time nD to nCP 5.0 − − 5.0 − 5.0 − ns th hold time nD to nCP 0 − − 0 − 0 − ns fmax maximum clock pulse frequency 80 140 − 65 − 65 − ns see Figs 6 and 8 Note 1. Typical values at VCC = 5.0 V. 1999 Sep 23 10 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74AHC74; 74AHCT74 AC WAVEFORMS VI handbook, full pagewidth VM(1) nD INPUT GND th th t su t su 1/fmax VI VM(1) nCP INPUT GND tW t PHL t PLH VOH VM(1) nQ OUTPUT VOL VOH VM(1) nQ OUTPUT VOL t PLH FAMILY VI INPUT REQUIREMENTS VM(1) INPUT t PHL MNA422 VM(1) OUTPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V 50% VCC The shaded areas indicate when the input is permitted to change for predictable output performance. Fig.6 The clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up, the nCP to nD hold times, the output transition times and the maximum clock pulse frequency. 1999 Sep 23 11 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74AHC74; 74AHCT74 VI handbook, full pagewidth VM(1) nCP INPUT GND t rem VI VM(1) nSD INPUT GND tW tW VI VM(1) nRD INPUT GND t PHL t PLH VOH VM(1) nQ OUTPUT VOL VOH VM(1) nQ OUTPUT VOL MNA423 t PHL FAMILY VI INPUT REQUIREMENTS VM(1) INPUT VM(1) OUTPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V 50% VCC Fig.7 t PLH The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths and the nRD to nCP removal time. 1999 Sep 23 12 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74AHC74; 74AHCT74 S1 handbook, full pagewidth VCC PULSE GENERATOR VI 1000 Ω VO D.U.T. CL RT MNA183 TEST S1 tPLH/tPHL open tPLZ/tPZL VCC tPHZ/tPZH GND Fig.8 Load circuitry for switching times. 1999 Sep 23 13 VCC open GND Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74AHC74; 74AHCT74 PACKAGE OUTLINES SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.050 0.028 0.024 0.01 0.01 0.004 0.028 0.012 inches 0.069 0.244 0.039 0.041 0.228 0.016 θ Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06S MS-012AB 1999 Sep 23 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-23 97-05-22 14 o 8 0o Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74AHC74; 74AHCT74 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.10 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 1999 Sep 23 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 94-07-12 95-04-04 MO-153 15 o Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger SOLDERING 74AHC74; 74AHCT74 If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Manual soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. To overcome these problems the double-wave soldering method was specifically developed. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 1999 Sep 23 16 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74AHC74; 74AHCT74 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable suitable(2) suitable suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1999 Sep 23 17 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger NOTES 1999 Sep 23 18 74AHC74; 74AHCT74 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger NOTES 1999 Sep 23 19 74AHC74; 74AHCT74 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SÃO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com SCA 68 © Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545002/02/pp20 Date of release: 1999 Sep 23 Document order number: 9397 750 06291