INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT112 Dual JK flip-flop with set and reset; negative-edge trigger Product specification Supersedes data of December 1990 File under Integrated Circuits, IC06 1998 Jun 10 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 The set and reset inputs, when LOW, set or reset the outputs as shown in the function table regardless of the levels at the other inputs. FEATURES • Asynchronous set and reset • Output capability: standard A HIGH level at the clock (nCP) input enables the nJ and nK inputs and data will be accepted. The nJ and nK inputs control the state changes of the flip-flops as shown in the function table. The nJ and nK inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Output state changes are initiated by the HIGH-to-LOW transition of nCP. • ICC category: flip-flops GENERAL DESCRIPTION The 74HC/HCT112 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. The 74HC/HCT112 are dual negative-edge triggered JK-type flip-flops featuring individual nJ, nK, clock (nCP), set (nSD) and reset (nRD) inputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay HCT CL = 15 pF; VCC = 5 V nCP to nQ, nQ 17 19 ns nSD to nQ, nQ 15 15 ns nRD to nQ, nQ 18 19 ns fmax maximum clock frequency 66 70 MHz CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per flip-flop notes 1 and 2 27 30 pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V 1998 Jun 10 2 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME 74HC112D; 74HCT112D 74HC112DB; 74HCT112DB SO16 SSOP16 74HC112N; 74HCT112N 74HC112PW; 74HCT112PW DIP16 TSSOP16 DESCRIPTION VERSION plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 13 1CP, 2CP clock input (HIGH-to-LOW, edge triggered) 2, 12 1K, 2K data inputs; flip-flops 1 and 2 3, 11 1J, 2J data inputs; flip-flops 1 and 2 4, 10 1SD, 2SD set inputs (active LOW) 5, 9 1Q, 2Q true flip-flop outputs 6, 7 1Q, 2Q complement flip-flop outputs 8 GND ground (0 V) 15, 14 1RD, 2RD reset inputs (active LOW) 16 VCC positive supply voltage Fig.1 Pin configuration. 1998 Jun 10 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 FUNCTION TABLE INPUTS OUTPUTS OPERATING MODE nSD nRD nCP nJ nK nQ nQ asynchronous set L H X X X H L asynchronous reset H L X X X L H undetermined L L X X X H L toggle H H ↓ h h q q load “0” (reset) H H ↓ l h L H load “1” (set) H H ↓ h l H L hold “no change” H H ↓ l l q q Note Fig.4 Functional diagram. 1. If nSD and nRD simultaneously go from LOW to HIGH, the output states will be unpredictable. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition L = LOW voltage level l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW CP transition X = don’t care ↓ = HIGH-to-LOW CP transition Fig.5 Logic diagram (one flip-flop). 1998 Jun 10 4 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: flip-flops 1998 Jun 10 5 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) SYMBOL 74HC PARAMETER +25 min. typ. tPHL/ tPLH propagation delay nCP to nQ tPHL/ tPLH propagation delay nCP to nQ tPHL/ tPLH propagation delay nRD to nQ, nQ tPHL/ tPLH propagation delay nSD to nQ, nQ tTHL/ tTLH output transition time tW clock pulse width HIGH or LOW tW trem trem tsu th fmax 1998 Jun 10 80 16 14 80 set or reset pulse width 16 LOW 14 80 removal time 16 nRD to nCP 14 removal time nSD to nCP set-up time nJ, nK to nCP hold time nJ, nK to nCP maximum clock pulse frequency TEST CONDITIONS max. −40 to +85 −40 to +125 min. max. min. max. 55 20 16 175 35 30 220 44 37 265 53 45 55 20 16 58 21 17 50 18 14 19 7 6 22 8 6 22 8 175 35 30 180 36 31 155 31 26 75 15 13 220 44 37 225 45 38 295 39 33 95 19 16 265 53 45 270 54 46 235 47 40 110 22 19 100 20 17 100 20 120 24 20 120 24 6 22 8 17 125 25 20 150 30 6 21 26 80 16 −19 −7 100 20 120 24 14 80 16 −6 19 7 17 100 20 20 120 24 14 0 0 6 −11 −4 17 0 0 20 0 0 0 6 30 35 −3 20 60 71 0 4.8 24 28 0 4.0 20 24 6 UNIT ns VCC (V) 2.0 4.5 6.0 ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 ns 6.0 2.0 4.5 ns ns ns ns ns WAVEFORMS Fig.6 Fig.6 Fig.7 Fig.7 Fig.6 Fig.6 Fig.7 Fig.7 6.0 ns 2.0 4.5 Fig.7 ns 6.0 2.0 4.5 Fig.6 ns 6.0 2.0 4.5 Fig.6 MHz 6.0 2.0 4.5 6.0 Fig.6 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: flip-flops Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT 1SD, 2SD 0.5 1K, 2K 0.6 1RD, 2RD 0.65 1J, 2J 1 1CP, 2CP 1 1998 Jun 10 7 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. −40 to +85 typ. max. min. max. −40 to +125 UNIT VCC (V) WAVEFORMS min. max. tPHL/ tPLH propagation delay nCP to nQ 21 35 44 53 ns 4.5 Fig.6 tPHL/ tPLH propagation delay nCP to nQ 23 40 50 60 ns 4.5 Fig.6 tPHL/ tPLH propagation delay nRD to nQ, nQ 22 37 46 56 ns 4.5 Fig.7 tPHL/ tPLH propagation delay nSD to nQ, nQ 18 32 40 48 ns 4.5 Fig.7 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6 tW clock pulse width HIGH or LOW tW 8 20 24 ns 4.5 Fig.6 set or reset pulse width 18 LOW 10 23 27 ns 4.5 Fig.7 trem removal time nRD to nCP 20 11 25 30 ns 4.5 Fig.7 trem removal time nSD to nCP 20 −8 25 30 ns 4.5 Fig.7 tsu set-up time nJ, nK to nCP 16 7 20 24 ns 4.5 Fig.6 th hold time nJ, nK to nCP 0 −7 0 0 ns 4.5 Fig.6 fmax maximum clock pulse frequency 30 64 24 20 MHz 4.5 Fig.6 1998 Jun 10 16 8 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig.6 Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nJ, nK to nCP set-up times, the nCP to nJ, nK hold times, the output transition times and the maximum clock pulse frequency. handbook, full pagewidth VM(1) nCP INPUT trem nSD INPUT VM(1) tW trem tW VM(1) nRD INPUT tPLH nQ OUTPUT tPHL VM(1) tPLH tPHL nQ OUTPUT VM(1) (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 MBK218 Waveforms showing the set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse width and the nRD and nSD to nCP removal time. 1998 Jun 10 9 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 PACKAGE OUTLINES SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.16 0.15 0.244 0.050 0.041 0.228 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.01 0.01 0.028 0.004 0.012 θ Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07S MS-012AC 1998 Jun 10 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-23 97-05-22 10 o 8 0o Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2.0 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 1998 Jun 10 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 94-01-14 95-02-04 MO-150AC 11 o Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 DIP16: plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 ME seating plane D A2 A A1 L c e Z b1 w M (e 1) b MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.7 0.51 3.7 1.40 1.14 0.53 0.38 0.32 0.23 21.8 21.4 6.48 6.20 2.54 7.62 3.9 3.4 8.25 7.80 9.5 8.3 0.254 2.2 inches 0.19 0.020 0.15 0.055 0.045 0.021 0.015 0.013 0.009 0.86 0.84 0.26 0.24 0.10 0.30 0.15 0.13 0.32 0.31 0.37 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT38-1 050G09 MO-001AE 1998 Jun 10 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-10-02 95-01-19 12 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.10 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 1998 Jun 10 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 94-07-12 95-04-04 MO-153 13 o Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 between 50 and 300 seconds depending on heating method. SOLDERING Introduction Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. WAVE SOLDERING Wave soldering can be used for all SO packages. Wave soldering is not recommended for SSOP and TSSOP packages, because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (order code 9398 652 90011). If wave soldering is used - and cannot be avoided for SSOP and TSSOP packages - the following conditions must be observed: DIP SOLDERING BY DIPPING OR BY WAVE • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. • The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Even with these conditions: • Only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). • Do not consider wave soldering TSSOP packages with 48 leads or more, that is TSSOP48 (SOT362-1) and TSSOP56 (SOT364-1). REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. REFLOW SOLDERING Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. Reflow soldering techniques are suitable for all SO, SSOP and TSSOP packages. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. SO, SSOP and TSSOP Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary 1998 Jun 10 14 Philips Semiconductors Product specification Dual JK flip-flop with set and reset; negative-edge trigger 74HC/HCT112 one operation within 2 to 5 seconds between 270 and 320 °C. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1998 Jun 10 15