INTEGRATED CIRCUITS 74LV107 Dual JK flip-flop with reset; negative-edge trigger Product specification Supersedes data of 1997 Feb 03 IC24 Data Handbook 1998 Apr 20 Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger FEATURES 74LV107 DESCRIPTION • Wide operating: 1.0 to 5.5 V • Optimized for low voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V • Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, The 74LV107 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT107. The 74LV107 is a dual negative-edge triggered JK-type flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs. Tamb = 25°C The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Tamb = 25°C The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH. • Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, • Output capability: standard • ICC category: flip-flops Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns PARAMETER SYMBOL tPHL/tPLH fmax Propagation delay nCP to nQ nCP to nQ nR to nQ, nQ CONDITIONS TYPICAL 15 15 15 CL = 15 pF; VCC = 3.3 V Maximum clock frequency CI Input capacitance CPD Power dissipation capacitance per flip-flop UNIT VI = GND to VCC1 ns 77 MHz 3.5 pF 30 pF NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in µW) PD = CPD × VCC2 × fi (CL × VCC2 fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL × VCC2 × fo) = sum of the outputs. ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. # 14-Pin Plastic DIL –40°C to +125°C 74LV107 N 74LV107 N SOT27-1 14-Pin Plastic SO –40°C to +125°C 74LV107 D 74LV107 D SOT108-1 14-Pin Plastic SSOP Type II –40°C to +125°C 74LV107 DB 74LV107 DB SOT337-1 14-Pin Plastic TSSOP Type I –40°C to +125°C 74LV107 PW 74LV107PW DH SOT402-1 PIN CONFIGURATION PIN DESCRIPTION 1J 1 14 VCC PIN NUMBER SYMBOL FUNCTION 1Q 2 13 1R 1, 8, 4, 11 1J, 2J, 1K, 2K Synchronous inputs; flip-flops 1 and 2 1Q 3 12 1CP 2, 6 1Q, 2Q Complement flip-flop outputs 1K 4 11 2K 3, 5 1Q, 2Q True flip-flop outputs 2Q 5 10 2R 2Q 6 9 2CP GND 7 8 2J 7 SV00497 12, 9 1CP, 2CP 13, 10 1R, 2R 14 1998 Apr 20 2 GND VCC Ground (0 V) Clock input (HIGH-to-LOW, edge-triggered) Asynchronous reset inputs (active LOW) Positive supply voltage 853–1904 19255 Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger LOGIC SYMBOL 74LV107 LOGIC SYMBOL (IEEE/IEC) 1 1 1J 8 2J 1J J C1 Q 1Q 3 2Q 5 4 1K 2 13 1R 12 1CP CP 9 3 12 FF 2CP 1Q 2 2Q 6 Q 4 1K 11 2K 8 2J 5 9 C1 K 11 R 2K 1R 2R 13 10 6 10 2R SV00498 SV00499 FUNCTIONAL DIAGRAM 1 1J J 1Q 3 1Q 2 2Q 5 2Q 6 Q 12 1CP CP 4 FF1 Q 1K K R 13 1R 8 2J J Q 9 2CP CP 11 FF2 Q 2K K R 10 2R SV00500 LOGIC DIAGRAM C K C C C Q J C C C Q R CP C C C SV00501 1998 Apr 20 3 Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger 74LV107 FUNCTION TABLE INPUTS OPERATING MODES OUTPUTS nR nCP nJ nK nQ nQ Asynchronous reset L X X X L H Toggle Load “0” (reset) Load “1” (set) Hold “no change” H H H H ↓ ↓ ↓ ↓ h l h l h h l l q L H q q H L q NOTES: H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition L = LOW voltage level I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW CP transition. X = don’t care ↓ = HIGH-to-LOW CP transition ABSOLUTE MAXIMUM RATINGS1, 2 In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V). SYMBOL PARAMETER VCC DC supply voltage CONDITIONS RATING UNIT –0.5 to +7.0 V IIK DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA IOK DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA IO DC output source or sink current – standard outputs –0.5V < VO < VCC + 0.5V 25 IGND, ICC Tstg PTOT DC VCC or GND current for types with – standard outputs mA 50 Storage temperature range Power dissipation per package – plastic DIL – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) mA –65 to +150 for temperature range: –40 to +125°C above +70°C derate linearly with 12 mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K 750 500 400 °C mW NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER CONDITIONS MIN TYP. See Note 1 1.0 0 0 DC supply voltage VI Input voltage VO Output voltage Tamb Operating ambient temperature range in free air tr, tf Input rise and fall times except for Schmitt-trigger inputs See DC and AC characteristics –40 –40 VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V – – – – MAX UNIT 3.3 5.5 V – VCC V – VCC V +85 +125 °C 500 200 100 50 ns/V – – – – NOTE: 1. The LV is guaranteed to function down to VCC = 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V. 1998 Apr 20 4 Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger 74LV107 DC ELECTRICAL CHARACTERISTICS Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL PARAMETER -40°C to +85°C TEST CONDITIONS TYP1 MIN VIH VIL HIGH level Input voltage LOW level Input voltage VOH VOL VOL HIGH level output voltage; g STANDARD outputs LOW level output voltage all outputs out uts voltage; LOW level output voltage; g STANDARD outputs MIN 0.9 0.9 VCC = 2.0 V 1.4 1.4 VCC = 2.7 to 3.6 V 2.0 2.0 VCC = 4.5 to 5.5 V 0.7VCC UNIT MAX V 0.7VCC VCC = 1.2 V 0.3 0.3 VCC = 2.0 V 0.6 0.6 VCC = 2.7 to 3.6 V 0.8 0.8 0.3VCC 0.3VCC VCC = 1.2 V; VI = VIH or VIL; –IO = 100µA HIGH level output voltage out uts voltage; all outputs MAX VCC = 1.2 V VCC = 4.5 to 5.5 VOH -40°C to +125°C V 1.2 VCC = 2.0 V; VI = VIH or VIL; –IO = 100µA 1.8 2.0 1.8 VCC = 2.7 V; VI = VIH or VIL; –IO = 100µA 2.5 2.7 2.5 VCC = 3.0 V; VI = VIH or VIL; –IO = 100µA 2.8 3.0 2.8 VCC = 4.5 V; VI = VIH or VIL; –IO = 100µA 4.3 4.5 4.3 VCC = 3.0 V; VI = VIH or VIL; –IO = 6mA 2.40 2.82 2.20 VCC = 4.5 V; VI = VIH or VIL; –IO = 12mA 3.60 4.20 3.50 V V VCC = 1.2 V; VI = VIH or VIL; IO = 100µA 0 VCC = 2.0 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 2.7 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 4.5 V; VI = VIH or VIL; IO = 100µA 0 0.2 0.2 VCC = 3.0 V; VI = VIH or VIL; IO = 6mA 0.25 0.40 0.50 VCC = 4.5 V; VI = VIH or VIL; IO = 12mA 0.35 0.55 0.65 V V Input leakage current VCC = 5.5 V; VI = VCC or GND 1.0 1.0 µA ICC Quiescent supply current; flip-flops VCC = 5.5V; VI = VCC or GND; IO = 0 20.0 80 µA ∆ICC Additional quiescent supply current per input VCC = 2.7 V to 3.6 V; VI = VCC – 0.6 V 500 850 µA II NOTE: 1. All typical values are measured at Tamb = 25°C. AC CHARACTERISTICS GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL PARAMETER WAVEFORM VCC(V) tPHL/tPLH Propagation delay nCP to nQ, nQ Figures 1, 2 –40 to +85 °C MIN TYP1 –40 to +125 °C MAX MIN 95 2.0 32 44 56 2.7 24 33 41 3.0 to 3.6 182 26 33 22 28 5 UNIT MAX 1.2 4.5 to 5.5 1998 Apr 20 LIMITS CONDITION ns Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger 74LV107 AC CHARACTERISTICS (Continued) GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ SYMBOL tPHL/tPLH PARAMETER Propagation delay nR to nQ, nQ WAVEFORM Figures 1, 2 –40 to +85 °C CONDITION VCC(V) MIN TYP1 tW Clock pulse width HIGH or LOW Reset pulse width LOW Figure 2 Figure 2 Removal time nR to nCP Figure 2 95 32 44 56 2.7 24 33 41 3.0 to 3.6 182 26 33 22 Set up time Set-up nJ, nK to CP Figure 1 34 14 41 2.7 25 10 30 3.0 to 3.6 20 82 24 4.5 to 5.5 15 2.0 34 14 41 2.7 25 10 30 3.0 to 3.6 20 82 24 4.5 to 5.5 15 th fmax Maximum clock pulse frequency Figure 1 Figure 1 1998 Apr 20 12 29 2.7 18 9 21 3.0 to 3.6 14 72 17 4.5 to 5.5 11 ns ns 14 40 2.0 26 14 31 2.7 19 10 23 3.0 to 3.6 15 82 18 4.5 to 5.5 12 ns 15 -10 2.0 5 2.7 3.0 to 3.6 –3 5 5 –2 5 5 –22 5 40 12 4.5 to 5.5 5 2.0 14 ns 5 2.7 19 58 16 3.0 to 3.6 24 702 20 4.5 to 5.5 30 6 ns 35 24 NOTES: 1. Unless otherwise stated, all typical values are measured at Tamb = 25°C 2. Typical values are measured at VCC = 3.3 V. ns 18 2.0 1.2 Hold time nJ, nK to CP UNIT 28 2.0 1.2 tsu MAX 2.0 1.2 trem MIN 1.2 4.5 to 5.5 tW –40 to +125 °C MAX 24 MHz Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger AC WAVEFORMS 74LV107 TEST CIRCUIT VM = 1.5 V at VCC ≥ 2.7 V and ≤ 3.6 V; VM = 0.5 × VCC at VCC < 2.7 V and ≥ 4.5 V; VOL and VOH are the typical output voltage drop that occur with the output load. Vcc VO Vl VI nJ, nK INPUT GND VI nCP INPUT PULSE GENERATOR VM D.U.T. 50pF RT t su t su th 1/f max CL RL= 1k th Test Circuit for Outputs VM DEFINITIONS RL = Load resistor GND tW CL = Load capacitance includes jig and probe capacitiance t PHL VOH nQ OUTPUT t PLH RT = Termination resistance should be equal to ZOUT of pulse generators. VM TEST VOL tPLH/tPHL VOH nQ OUTPUT VM VOL VCC VI < 2.7V VCC 2.7–3.6V 2.7V ≥ 4.5 V VCC SV00902 t PLH Figure 3. Load circuitry for switching times. t PHL The shaded areas indicate when the input is permitted to change for predictable output performance. SV00504 Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the J and K to nCP set-up and hold times and the maximum clock pulse frequency. VI nCP INPUT GND VM t rem tW VI nR INPUT GND VM t PHL VOH nQ OUTPUT VOL VM t PLH VOH nQ OUTPUT VOL SV00502 Figure 2. Reset (nR) input to output (nQ, nQ) propagation delays, the reset pulse width and the nR to nCP removal time. 1998 Apr 20 7 Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger DIP14: plastic dual in-line package; 14 leads (300 mil) 1998 Apr 20 8 74LV107 SOT27-1 Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger SO14: plastic small outline package; 14 leads; body width 3.9 mm 1998 Apr 20 9 74LV107 SOT108-1 Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm 1998 Apr 20 10 74LV107 SOT337-1 Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm 1998 Apr 20 11 74LV107 SOT402-1 Philips Semiconductors Product specification Dual JK flip-flop with reset; negative-edge trigger 74LV107 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: 1998 Apr 20 12 Date of release: 05-96 9397-750-04416