INTEGRATED CIRCUITS DATA SHEET SAA7184; SAA7185B Digital Video Encoders (DENC2-M6) Preliminary specification Supersedes data of 1995 Nov 14 File under Integrated Circuits, IC22 1996 Jul 03 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B FEATURES • CMOS 5 V device • Digital PAL/NTSC encoder • System pixel frequency 13.5 MHz • Accepts MPEG decoded data • 8-bit wide MPEG port GENERAL DESCRIPTION • Input data format Cb, Y, Cr etc. (CCIR 656) The SAA7184 and SAA7185B digital video encoders 2 (DENC2-M6) encode digital YUV video data to an NTSC or PAL CVBS or S-Video signal. • 16-bit wide YUV input port • I2C-bus control port or alternatively MPU parallel control port • Programmable horizontal sync output phase The circuit accepts CCIR compatible YUV data with 720 active pixels per line in 4 : 2 : 2 multiplexed formats, for example MPEG decoded data. The device includes a sync/clock generator and on-chip Digital-to-Analog Converters (DACs). • OVL overlay with Look-Up Tables (LUTs) 8 × 3 bytes The circuit is compatible to the DIG-TV2 chip family. • Encoder can be master or slave • Programmable horizontal and vertical input synchronization phase • Colour bar generator • Line 21 closed caption encoder • Cross-colour reduction • Macrovision revision_6 Pay-per-View copy protection system as option (SAA7184 only). Remark: This device is protected by U.S. patent numbers 4631603 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anticopy process in the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductors sales office for more information. • DACs operating at 27 MHz with 10-bit resolution • Controlled rise and fall times of output syncs and blanking • Down-mode of DACs • CVBS and S-Video output simultaneously • PLCC68 package. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA7184WP SAA7185BWP 1996 Jul 03 PLCC68 DESCRIPTION plastic leaded chip carrier; 68 leads 2 VERSION SOT188-2 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDDA analog supply voltage 4.75 5.0 5.25 V VDDD digital supply voltage 4.5 5.0 5.5 V IDDA analog supply current − 50 55 mA IDDD digital supply current − 130 170 mA Vi input signal voltage levels Vo(p-p) analog output signal voltages Y, C and CVBS without load − (peak-to-peak value) RL load resistance ILE DLE Tamb operating ambient temperature TTL compatible V 2 − V 80 − − Ω LF integral linearity error − − ±2 LSB LF differential linearity error − − ±1 LSB 0 − +70 °C BLOCK DIAGRAM KEY SEL_ED 18 MP7 to MP0 VP0 to VP7 OVL0 to OVL2 31 VDDD1 to VDDD3 RTCI 32 to 34 VDDA1 to VrefH VDDA4 IOA 47 55 48,50, 54,56 53 A 51 17,37,67 43 20 to 27 8 DATA MANAGER 9 to 16 8 OUTPUT INTERFACE ENCODER 8 8 D 49 8 internal control bus RCM1 RCM2 8 clock timing signals VSSA 46 VrefL 8 1,8,19 28,35, 42,62 63 to 66 2 to 5 CONTROL INTERFACE 68 61 59 60 SAA7184 SAA7185B 8 SYNC CLK 58 57 41 40 38 39 36 6 7 MGC679 DP0 to DP7 CSN/SA SEL_MPU A0/SDA RWN/SCL RES XTALI DTACK XTALO ll pagewidth VSSD1 to VSSD7 Fig.1 Block diagram. 1996 Jul 03 3 LLC CDIR CREF RCV2 RCV1 Y CHROMA 52 29 30 CVBS Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B PINNING SYMBOL PIN I/O DESCRIPTION 1 − 2 to 5 I/O Upper 4 bits of the data port; if pin 68 (SEL_MPU) is HIGH, the data bus of the parallel MPU interface is used. If pin 68 is LOW, then the UV lines of the video port are used. RCV1 6 I/O Raster control 1 for video port; depending on the synchronization mode, this pin receives or provides a VS/FS/FSEQ signal. RCV2 7 I/O Raster control 2 for video port; depending on the synchronization mode, this pin receives or provides an HS/HREF/CBL signal. VSSD2 8 − digital ground 2 9 to 16 I Video port; this is an input for CCIR 656 compatible multiplexed video data. If the 16-bit DIG-TV2 format is used, then Y data is input. VDDD1 17 I digital supply voltage 1 SEL_ED 18 I select encoder data; selects input data either from the MPEG port or from the video port VSSD3 19 − digital ground 3 VSSD1 DP4 to DP7 VP0 to VP7 MP7 to MP0 digital ground 1 20 to 27 I MPEG port; it is an input for CCIR 656 style multiplexed YUV data. VSSD4 28 − digital ground 4 RCM1 29 O Raster control 1 for MPEG port; this pin provides a VS/FS/FSEQ signal. RCM2 30 O Raster control 2 for MPEG port; this pin provides an HS pulse for the MPEG decoder. KEY 31 I key signal for OVL (active HIGH) 32 to 34 I on-screen display data; this is the index for the internal OVL look-up tables VSSD5 35 − digital ground 5 CDIR 36 I Clock direction; if the CDIR input is HIGH, the circuit receives a clock signal, if not LLC and CREF are generated by the internal crystal oscillator. VDDD2 37 I digital supply voltage 2 LLC 38 I/O Line-locked clock; this is the 27 MHz master clock for the encoder. The direction is set by the CDIR pin. CREF 39 I/O Clock reference signal; this is the clock qualifier for DIG-TV2 compatible signals. The polarity is programmable by software. XTALO 40 O crystal oscillator output (to crystal) XTALI 41 I Crystal oscillator input (from crystal). If the oscillator is not used, this pin should be connected to ground. VSSD6 42 − digital ground 6 RTCI 43 I Real time control Input; if the clock is provided by the SAA7151B or SAA7111, RTCI should be connected to the RTCO pin of the decoder to improve the signal quality. AP 44 − test pin (should be connected to digital ground for normal operation) SP 45 − test pin (should be connected to digital ground for normal operation) VrefL 46 I lower reference voltage input for the DACs VrefH 47 I upper reference voltage input for the DACs VDDA1 48 I analog positive supply voltage 1 for the DACs and output amplifiers OVL0 to OVL2 1996 Jul 03 4 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SYMBOL SAA7184; SAA7185B PIN I/O DESCRIPTION CHROMA 49 O VDDA2 50 I analog supply voltage 2 for the DACs and output amplifiers Y 51 O analog output of the luminance signal VSSA 52 − analog ground for the DACs and output amplifiers CVBS 53 O analog output of the CVBS signal VDDA3 54 I analog supply voltage 3 for the DACs and output amplifiers IOA 55 I current input for the output amplifiers (connected via a 15 kΩ resistor to VDDA) VDDA4 56 I analog supply voltage 4 for the DACs and output amplifiers RES 57 I Reset input, active LOW. After reset is applied, all outputs are in 3-state input mode. The I2C-bus receiver waits for the start condition. DTACK 58 O Data acknowledge output of the parallel MPU interface, active LOW, otherwise high impedance. RWN/SCL 59 I If pin 68 (SEL_MPU) is HIGH, this is the read/write signal of the parallel MPU interface. Otherwise it is the I2C-bus serial clock input. A0/SDA 60 I/O If pin 68 (SEL_MPU) is HIGH, this is the address signal of the parallel MPU interface. Otherwise it is the I2C-bus serial data input/output. CSN/SA 61 I If pin 68 (SEL_MPU) is HIGH, this is the chip select signal of the parallel MPU interface. Otherwise it is the I2C-bus slave address select pin. When LOW slave address = 88H, when HIGH slave address = 8CH. digital ground 7 analog output of the chrominance signal 62 − 63 to 66 I/O VDDD3 67 I digital supply voltage 3 SEL_MPU 68 I Select MPU interface input; if it is HIGH, the parallel MPU interface is active, if not the I2C-bus interface will be used. VSSD7 DP0 to DP3 1996 Jul 03 Lower 4 bits of the data port; if pin 68 (SEL_MPU) is HIGH, the data bus of the parallel MPU interface is used. If pin 68 is LOW, then the UV lines of the video port are used. 5 Philips Semiconductors Preliminary specification 44 AP VrefL 46 45 SP VrefH 47 48 VDDA1 49 CHROMA 50 VDDA2 51 Y SAA7184; SAA7185B 52 VSSA 53 CVBS 54 VDDA3 55 IOA 56 VDDA4 57 RES 58 DTACK 60 A0/SDA handbook, full pagewidth 59 RWN/SCL Digital Video Encoders (DENC2-M6) CSN/SA 61 43 RTCI VSSD7 62 42 VSSD6 DP0 63 41 XTALI DP1 64 40 XTALO DP2 65 39 CREF DP3 66 38 LLC VDDD3 67 37 VDDD2 SEL_MPU 68 36 CDIR SAA7184 SAA7185B VSSD1 1 35 VSSD5 DP4 2 34 OVL2 DP5 3 33 OVL1 DP6 4 32 OVL0 DP7 5 31 KEY Fig.2 Pin configuration. 1996 Jul 03 6 MP1 26 MP2 25 MP3 24 MP4 23 MP5 22 MP6 21 MP7 20 VSSD3 19 27 MP0 SEL_ED 18 9 VDDD1 17 VP0 VP7 16 28 VSSD4 VP6 15 8 VP5 14 29 RCM1 VSSD2 VP4 13 7 VP3 12 RCV2 VP2 11 30 RCM2 VP1 10 RCV1 6 MGC678 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B The IC also contains closed caption and extended data services encoding (line 21), and supports anti-taping signal generation in accordance with Macrovision. It also supports OVL via KEY and 3-bit overlay techniques using a 24 × 8 LUT. FUNCTIONAL DESCRIPTION The digital MPEG-compatible video encoder (DENC2-M6) encodes digital luminance and chrominance into analog CVBS and S-Video (Y/C) signals simultaneously. NTSC-M and PAL B/G standards and sub-standards are also supported. The IC can be programmed via the I2C-bus or via the 8-bit MPU interface, but only one interface configuration can be active at a time. If the 16-bit video port mode (VP and DP) is being used, only the I2C-bus interface can be selected. The basic encoder function consists of subcarrier generation and colour modulation plus insertion of synchronization signals. Luminance and chrominance signals are filtered in accordance with the standard requirements of RS-170-A and CCIR 624. A number of possibilities are provided for setting the different video parameters such as: black and blanking level control For ease of analog post filtering the signals are twice oversampled, with respect to the pixel clock, before digital-to-analog conversion. colour subcarrier frequency black variable burst amplitude etc. For total filter transfer characteristics see Figs 3, 4, 5 and 6. The DACs are realized with full 10-bit resolution. The encoder provides three 8-bit wide data ports that serve different applications. During reset (RES = LOW) and after reset is released, all digital I/O stages are set to the input mode. A reset forces the control interfaces to abort any running bus transfer and to set register 3AH to contents 1FH, register 61H to contents 06H, and registers 6CH and 7AH to contents 00H. All other control registers are not influenced by a reset. The MPEG port and the video port accept 8 lines multiplexed Cb-Y-Cr data. The video port is also able to accommodate DIG-TV2 family compatible 16-bit YUV signals. In this event, the data port is used for the U/V components. Data manager Real time arbitration on the data stream to be encoded is performed in the data manager. Alternatively, the data port can accommodate the data of an 8-bit wide microprocessor interface. Depending on the hardware conditions (signals on pins SEL_ED, KEY, OVL2 to OVL0, MP7 to MP0, VP7 to VP0 and DP7 to DP0) and different software programming, either data from the MP port, from the VP port or from the OVL port, is selected to be encoded to CVBS and Y/C signals. The 8-bit multiplexed Cb-Y-Cr formats are CCIR 656 (D1 format) compatible, but the SAV, EAV etc. codes are not decoded. A crystal-stable master clock (LLC) of 27 MHz, which is twice the CCIR line-locked pixel clock frequency of 13.5 MHz, needs to be supplied externally. A crystal oscillator input/output pair of pins and an on-chip clock driver are provided optionally. It is also possible to connect the Philips Digital Video Decoder (SAA7111 or SAA7151B) in conjunction with a CREF clock qualifier to the DENC2-M6 via the RETCI pin (connected to RTCO) of a decoder. Information concerning the actual subcarrier, PAL-ID and (with SAA7111) definite subcarrier phase can be inserted. Optionally, the OVL colour look-up tables located in this block can be read out in a pre-defined sequence (8 steps per active video line) thereby achieving, for example, a colour bar test pattern generator without the need for an external data source. The colour bar function is only under software control. Encoder VIDEO PATH The DENC2-M6 synthesizes all necessary internal signals, colour subcarrier frequency and synchronization signals, from that clock. The DENC2-M6 is always the timing master for the MPEG port but can also be configured as master or slave for the video port. 1996 Jul 03 The encoder generates luminance and colour subcarrier output signals, suitable for use as CVBS or separate Y/C signals, from the Y, U and V baseband signals. 7 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B The luminance gain and offset are modified (offset being programmable within a certain range to enable different black level set-ups). After the signals have been inserted, a fixed synchronization level in accordance with standard composite synchronization schemes and blanking level, (also programmable in a certain range to allow for manipulations with Macrovision anti-tapping) additional insertion of AGC super white pulses (programmable in height) is supported. It is also possible to encode closed caption data for 50 Hz field frequencies at 32 times horizontal line frequency. Output interface In the output interface, encoded Y and C signals are converted from digital to analog in a 10-bit resolution and then combined into a 10-bit CVBS signal. Also, in front of the summation point, the luminance signal can be fed through a further filter stage (optional), thereby suppressing components in the subcarrier frequency range. Thus, a type of cross colour reduction is provided, which is useful in a standard TV set with CVBS input. In order to enable easy analog post filtering, luminance is interpolated from a 13.5 MHz data rate to a 27 MHz data rate, thereby providing luminance in a 10-bit resolution. This filter is also used to define smoothed transients for synchronization pulses and blanking period. The transfer characteristics of the luminance interpolation filter are illustrated in Figs 5 and 6. The slopes of the synchronization pulses are not affected with any active cross colour reduction. Three different filter characteristics or bypass are available, see Fig.5. The chrominance gain is modified (programmable separately for U and V), a standard dependent burst is inserted before baseband colour signals are interpolated from a 6.75 MHz data rate to a 27 MHz data rate. One of the interpolation stages can be bypassed, thereby providing a higher colour bandwidth, which can be used for the Y/C output. The transfer characteristics of the chrominance interpolation filter are illustrated in Figs 3 and 4. The CVBS output occurs with the same processing delay as the Y and C outputs. Absolute amplitudes at the input of the DAC for CVBS is reduced by 15⁄16 with respect to Y and C DACs to make maximum use of conversion ranges. Outputs of all DACs can be set together, via software control, to minimum output voltage for either purpose. Synchronization The amplitude of the inserted burst is programmable within a certain range, suitable for standard signals and for special effects. Colour in a 10-bit resolution is provided on the subcarrier after the succeeding quadrature modulator. The synchronization of the DENC2 is able to operate in two modes; slave mode and master mode. In the slave mode, the circuit accepts synchronization pulses at the bidirectional RCV1 port. The timing and trigger behaviour, related to the video signal on VP (and DP, if used), can be influenced by programming the polarity and on-chip delay of RCV1. The active slope of RCV1 defines the vertical phase and, as an option, the odd/even and colour frame phase to be initialized. It can also be used to set the horizontal phase. The numeric ratio between Y and C outputs is in accordance with set standards. CLOSED CAPTION ENCODER Using the closed caption encoder circuit, data in accordance with the specification of closed caption or extended data service, delivered by the control interface, can be encoded (line 21). Two dedicated pairs of bytes (two bytes per field) are possible, each pair preceded by run-in clocks and framing code. If the horizontal phase is not to be influenced by RCV1, a horizontal pulse needs to be applied at pin RCV2. Timing and trigger behaviour can also be influenced for RCV2. If there are missing pulses at RCV1 and/or RCV2, the time base of the DENC2-M6 will become free-running, thus an arbitrary number of synchronization slopes may miss, but no additional pulses must occur (such as with wrong phase). The actual line number where data is to be encoded, can be modified within a certain range. The data clock frequency is in accordance with the definition for NTSC-M standard 32 times horizontal line frequency. If the vertical and horizontal phase is derived from RCV1, RCV2 can be used for horizontal or composite blanking input or output. Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 IRE. 1996 Jul 03 8 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B In the master mode, the time base of the circuit is continuously free-running. At the RCV1 port, the IC can output: The parallel interface is defined by: D7 to D0 data bus CS active LOW chip select signal • A vertical sync signal (VS) with 3 or 2.5 lines duration, or RW read/write signal, LOW for a write cycle • An odd/even signal which is LOW in odd fields, or DTACK 680xx style data acknowledge (handshake), active-LOW • A field sequence signal (FSEQ) which is HIGH in the first of 4 respectively 8 fields. A0 register select, LOW selects address, HIGH selects data. The IC can provide a horizontal pulse with programmable start and stop phase at the RCV2 port. This pulse can be inhibited in the vertical blanking period to build up, for example, a composite blanking signal. The parallel interface uses two registers, one auto-incremental containing the current address of a control register (equals subaddress with I2C-bus control), and one containing actual data. The currently addressed register is mapped to the corresponding control register. The phase of the output pulses at RCV1 or RCV2 are referenced to the VP port, polarity of both signals is selectable. The status byte can be read (optionally) via a read access to the address register, no other read access is provided. The DENC2-M6 is always the timing master for the source at the MP input. The IC provides two signals for synchronizing this source: Input levels and formats 1. At the RCM1 port the same signals as at RCV1 (as output) are available. DENC2-M6 accepts digital YUV data with levels (digital codes) in accordance with CCIR 601. 2. At RCM2 the IC provides a horizontal pulse with programmable start and stop phase. Deviating amplitudes in the colour difference signals can be compensated for by independent gain control setting, while the gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without set-up. The start and end of the active part can be programmed. The active part of a field always starts at the beginning of a line if the standard blanking option SBLBN is not set. The MPEG port accepts only 8-bit multiplexed CCIR 656 compatible data. Control interface If the I2C-bus interface is used, the VP port can accommodate both formats, 8-bit multiplexed Cb-Y-Cr data on the VP lines, or the 16-bit DTV2 format with the Y signal on the VP lines and the UV signal on the DP port. DENC2-M6 contains two control interfaces, an I2C-bus slave transceiver and an 8-bit parallel microprocessor interface. The interfaces cannot be used simultaneously. The I2C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are write only, except one status byte which can be read. Reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation. Two I2C-bus slave addresses can be selected (pin SEL_MPU must be LOW): 88H: pin 61 = LOW 8CH: pin 61 = HIGH. 1996 Jul 03 9 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) Table 1 CCIR signal component levels SIGNAL Y IRE DIGITAL LEVEL 0 16 50 126 100 235 bottom peak 16 colourless 128 top peak 240 Cb bottom peak 16 colourless 128 top peak 240 Cr Table 2 CODE straight binary straight binary straight binary 8-bit multiplexed format (similar to CCIR 656) TIME Sample 0 1 2 2 4 5 6 7 Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Luminance pixel number 0 1 Colour pixel number Table 3 SAA7184; SAA7185B 2 3 0 2 16-bit multiplexed format (DTV2 format) TIME Sample Y line Sample UV line Luminance pixel number Colour pixel number 1996 Jul 03 0 1 2 3 4 5 6 7 Y0 Y1 Y2 Y3 Cb0 Cr0 Cb2 Cr2 0 1 2 3 0 10 2 1996 Jul 03 3A 42 43 44 Input port control OVL LUT Y0 OVL LUT U0 OVL LUT V0 11 6C 68 Line 21 odd 1 RCV port control 67 Line 21 odd 0 6B 66 Subcarrier 3 Encoder control, CC line 65 Subcarrier 2 69 64 Subcarrier 1 6A 63 Subcarrier 0 Line 21 even 1 62 Burst amplitude SRCV11 MODIN1 L21E17 L21E07 L21O17 L21O07 FSC31 FSC23 FSC15 FSC07 DECTYP 0 0 GAINV8 GAINU8 GAINV7 GAINU7 CHPS7 OVLV77 OVLU77 OVLY77 OVLV07 OVLU07 OVLY07 CBENB 0 0 D7 SRCV10 MODIN0 L21E16 L21E06 L21O16 L21O06 FSC30 FSC22 FSC14 FSC06 BSTA6 DOWN 0 0 0 GAINV6 GAINU6 CHPS6 OVLV76 OVLU76 OVLY76 OVLV06 OVLU06 OVLY06 0 0 0 D6 TRCV2 PCREF L21E15 L21E05 L21O15 L21O05 FSC29 FSC21 FSC13 FSC05 BSTA5 INPI1 0 BLNNL5 BLCKL5 GAINV5 GAINU5 CHPS5 OVLV75 OVLU75 OVLY75 OVLV05 OVLU05 OVLY05 0 0 0 D5 ORCV1 SCCLN4 L21E14 L21E04 L21O14 L21O04 FSC28 FSC20 FSC12 FSC04 BSTA4 YGS 0 BLNNL4 BLCKL4 GAINV4 GAINU4 CHPS4 OVLV74 OVLU74 OVLY74 OVLV04 OVLU04 OVLY04 V656 0 0 D4 ↓ ↓ PRCV1 SCCLN3 L21E13 L21E03 L21O13 L21O03 FSC27 FSC19 FSC11 FSC03 BSTA3 RTCE 0 BLNNL3 BLCKL3 GAINV3 GAINU3 CHPS3 OVLV73 OVLU73 OVLY73 OVLV03 OVLU03 OVLY03 VY2C 0 0 D3 DATA BYTE (note 1) CBLF SCCLN2 L21E12 L21E02 L21O12 L21O02 FSC26 FSC18 FSC10 FSC02 BSTA2 SCBW 0 BLNNL2 BLCKL2 GAINV2 GAINU2 CHPS2 OVLV72 OVLU72 OVLY72 OVLV02 OVLU02 OVLY02 VUV2C 0 0 D2 ORCV2 SCCLN1 L21E11 L21E01 L21O11 L21O01 FSC25 FSC17 FSC09 FSC01 BSTA1 PAL 0 BLNNL1 BLCKL1 GAINV1 GAINU1 CHPS1 OVLV71 OVLU71 OVLY71 OVLV01 OVLU01 OVLY01 MY2C 0 0 D1 PRCV2 SCCLN0 L21E10 L21E00 L21O10 L21O00 FSC24 FSC16 FSC08 FSC00 BSTA0 FISE 0 BLNNL0 BLCKL0 GAINV0 GAINU0 CHPS0 OVLV70 OVLU70 OVLY70 OVLV00 OVLU00 OVLY00 MUV2C 0 0 D0 Digital Video Encoders (DENC2-M6) Line 21 even 0 60 61 5E Gain V MSB, blanking level Standard control 5D Gain U MSB, black level Null 5B 5C Chrominance phase Gain V 5A OVL LUT V7 Gain U 58 59 OVL LUT U7 57 OVL LUT Y7 ↓ 39 ↓ 00 Null Null SUB ADDRESS Slave receiver (slave address 88h or 8Ch) REGISTER FUNCTION Table 4 Bit allocation map Philips Semiconductors Preliminary specification SAA7184; SAA7185B 1996 Jul 03 77 78 79 7A Begin RCV2 output End RCV2 output MSBs RCV2 output Field length 12 0 LAL7 FAL7 0 0 ERCV7 BRCV7 0 0 0 0 EMRQ7 BMRQ7 PHRES1 HTRIG8 HTRIG7 0 D7 0 LAL6 FAL6 0 ERCV10 ERCV6 BRCV6 0 0 0 EMRQ10 EMRQ6 BMRQ6 PHRES0 HTRIG9 HTRIG6 0 D6 0 D5 LAL8 LAL5 FAL5 0 ERCV09 ERCV5 BRCV5 0 0 0 EMRQ09 EMRQ5 BMRQ5 SBLBN HTRIG10 HTRIG5 1. All bits labelled ‘0’ are reserved. They must be programmed with logic 0. Note 7D 76 Null MSBs field control 75 Null 7C 74 Null Last active line 73 MSBs MP request 7B 72 End MP request First active line 70 71 6F Horizontal trigger Begin MP request 6E fsc reset mode, Vertical trigger 6D Horizontal trigger SUB ADDRESS RCM, CC mode REGISTER FUNCTION FAL8 LAL4 FAL4 0 ERCV08 ERCV4 BRCV4 0 0 0 EMRQ08 EMRQ4 BMRQ4 VTRIG4 0 HTRIG4 0 D4 0 LAL3 FAL3 0 0 ERCV3 BRCV3 0 0 0 0 EMRQ3 BMRQ3 VTRIG3 0 HTRIG3 SRCM11 D3 DATA BYTE (note 1) 0 LAL2 FAL2 0 BRCV10 ERCV2 BRCV2 0 0 0 BMRQ10 EMRQ2 BMRQ2 VTRIG2 0 HTRIG2 SRCM10 D2 0 LAL1 FAL1 FLC1 BRCV09 ERCV1 BRCV1 0 0 0 BMRQ09 EMRQ1 BMRQ1 VTRIG1 0 HTRIG1 CCEN1 D1 0 LAL0 FAL0 FLC0 BRCV08 ERCV0 BRCV0 0 0 0 BMRQ08 EMRQ0 BMRQ0 VTRIG0 0 HTRIG0 CCEN0 D0 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B I2C-bus format Table 5 S I2C-bus address; see Table 6 SLAVE ADDRESS Table 6 ACK SUBADDRESS ACK DATA 0 ACK -------- DATA n ACK P Explanation of Table 5 PART DESCRIPTION S START condition Slave address 1 0 0 0 1 0 0 X or 1 0 0 0 1 1 0 X (note 1) ACK acknowledge, generated by the slave Subaddress (note 2) subaddress byte DATA data byte -------- continued data bytes and ACKs P STOP condition Notes 1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read, no subaddressing with read. 2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed. Slave Receiver Table 7 Subaddress 3A DATA BYTE LOGIC LEVEL MUV2C 0 Cb/Cr data at MP is two’s complement. 1 Cb/Cr data at MP is straight binary. Default after reset. MY2C VUV2C VY2C V656 CBENB 1996 Jul 03 DESCRIPTION 0 Y data at MP is two’s complement. 1 Y data at MP is straight binary. Default after reset. 0 Cb/Cr data input to VP or DP is two’s complement 1 Cb/Cr data input to VP or DP is straight binary. Default after reset. 0 Y data input to VP is two’s complement 1 Y data input to VP is straight binary. Default after reset. 0 selects YUV 422 format on VP (8 lines Y) and DP (8 lines multiplexed Cb/Cr). 1 selects CCIR 656 compatible format on VP (8 lines Cb, Y, Cr). Default after reset. 0 data from input ports is encoded. Default after reset. 1 colour bar with programmable colours (entries of OVL_LUTs) is encoded. The LUTs are read in upward order from index 0 to index 7. 13 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) Table 8 SAA7184; SAA7185B Subaddress 42 to 59 DATA BYTE(1) INDEX(2) COLOUR White Yellow Cyan OVLY OVLU OVLV 107 (6BH) 0 (00H) 0 (00H) 107 (6BH) 0 (00H) 0 (00H) 82 (52H) 144 (90H) 18 (12H) 34 (22H) 172 (ACH) 14 (0EH) 42 (2AH) 38 (26H) 144 (90H) 03 (03H) 29 (1DH) 172 (ACH) Green 17 (11H) 182 (B6H) 162 (A2H) 240 (F0H) 200 (C8H) 185 (B9H) Magenta 234 (EAH) 74 (4AH) 94 (5EH) 212 (D4H) 56 (38H) 71 (47H) 209 (D1H) 218 (DAH) 112 (70H) 193 (C1H) 227 (E3H) 84 (54H) 169 (A9H) 112 (70H) 238 (EEH) 163 (A3H) 84 (54h) 242 (F2H) 144 (90H) 0 (00H) 0 (00H) 144 (90H) 0 (00H) 0 (00H) Red Blue Black 0 1 2 3 4 5 6 7 Notes 1. Contents of OVL look-up tables. All 8 entries are 8-bits. Data representation is in accordance with CCIR 601 (Y, Cb, Cr), but two’s complement, e.g. for a 100⁄100 (upper number) or 100⁄75 (lower number) colour bar. 2. For normal colour bar with CBENB = logic 1. Table 9 Subaddress 5A DATA BYTE CHPS DESCRIPTION phase of encoded colour subcarrier (including burst) relative to horizontal sync. Can be adjusted in steps of 360/256 degrees. Table 10 Subaddress 5B and 5D DATA BYTE GAINU DESCRIPTION CONDITIONS variable gain for Cb signal; white-to-black = 92.5 input representation in GAINU = 0 accordance with GAINU = 118 (76H) “CCIR 601” white-to-black = 100 IRE(2) output subcarrier of U contribution = 0 output subcarrier of U contribution = nominal GAINU = 0 output subcarrier of U contribution = 0 GAINU = 125 (7DH) output subcarrier of U contribution = nominal Notes 1. GAINU = −2.17 × nominal to +2.16 × nominal. 2. GAINU = −2.05 × nominal to +2.04 × nominal. 1996 Jul 03 REMARKS IRE(1) 14 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B Table 11 Subaddress 5C and 5E DATA BYTE DESCRIPTION CONDITIONS GAINV variable gain for Cr signal; input representation in accordance with “CCIR 601” white-to-black = 92.5 IRE(1) GAINV = 0 REMARKS output subcarrier of V contribution = 0 GAINV = 165 (A5H) white-to-black = 100 output subcarrier of V contribution = nominal IRE(2) GAINV = 0 output subcarrier of V contribution = 0 GAINV = 175 (AFH) output subcarrier of V contribution = nominal Notes 1. GAINV = −1.55 × nominal to + 0.55 × nominal. 2. GAINV = −1.46 × nominal to + 0.46 × nominal. Table 12 Subaddress 5D DATA BYTE BLCKL DESCRIPTION variable black level; input representation in accordance with “CCIR 601” CONDITIONS REMARKS white-to-sync = 140 IRE(1) BLCKL = 0 output black level = 24 IRE BLCKL = 63 (3FH) output black level = 49 IRE white-to-sync = 143 IRE(2) BLCKL = 0 output black level = 24 IRE BLCKL = 63 (3FH) output black level = 50 IRE Notes 1. Output black level/IRE = BLCKL × 25/63 + 24; recommended value: BLCKL = 60 (3CH) normal. 2. Output black level/IRE = BLCKL × 26/63 + 24; recommended value: BLCKL = 45 (2DH) normal. Table 13 Subaddress 5E DATA BYTE BLNNL DESCRIPTION variable blanking level CONDITIONS REMARKS white-to-sync = 140 IRE(1) BLNNL = 0 output blanking level = 17 IRE BLNNL = 63 (3FH) output blanking level = 42 IRE white-to-sync = 143 IRE(2) BLNNL = 0 output blanking level = 17 IRE BLNNL = 63 (3FH) output blanking level = 43 IRE Notes 1. Output black level/IRE = BLNNL × 25/63 + 17; recommended value: BLNNL = 58 (3AH) normal. 2. Output black level/IRE = BLNNL × 26/63 + 17; recommended value: BLNNL = 63 (3FH) normal. 1996 Jul 03 15 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B Table 14 Subaddress 5F (CCRS and BLNVB; note 1) DATA BYTE FUNCTION CCRS1 CCRS0 0 0 no cross colour reduction (for overall transfer characteristic of luminance see Fig.5) 0 1 cross colour reduction #1 active (for overall transfer characteristic see Fig.5) 1 0 cross colour reduction #2 active (for overall transfer characteristic see Fig.5) 1 1 cross colour reduction #3 active (for overall transfer characteristic see Fig.5) Note 1. BLNVB = vertical blanking level during vertical blanking interval and its value is typically identical to BLNNL. Table 15 Subaddress 61 DATA BYTE LOGIC LEVEL FISE 0 864 total pixel clocks per line. Default after reset. 1 858 total pixel clocks per line 0 NTSC encoding (non-alternating V component) 1 PAL encoding (alternating V component). Default after reset. 0 enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 3 and 4) 1 standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 3 and 4). Default after reset. PAL SCBW RTCE DESCRIPTION 0 no real time control of generated subcarrier frequency. Default after reset. 1 real time control of generated subcarrier frequency through SAA7151B or SAA7111 (see Fig.9) YGS 0 luminance gain for white − black 100 IRE. Default after reset. 1 luminance gain for white − black 92.5 IRE including 7.5 IRE set-up of black INPI 0 PAL switch phase is nominal. Default after reset. 1 PAL switch phase is inverted compared to nominal 0 DACs in normal operational mode. Default after reset. 1 DACs forced to lowest output voltage DOWN 1996 Jul 03 16 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B Table 16 Subaddress 62 DATA BYTE BSTA DESCRIPTION amplitude of colour burst; input representation in accordance with CCIR 601 CONDITIONS REMARKS white-to-black = 92.5 IRE; burst = 40 IRE; NTSC encoding BSTA = 0 to 1.25 × nominal(1) white-to-black = 92.5 IRE; burst = 40 IRE; PAL encoding BSTA = 0 to 1.76 × nominal(2) white-to-black = 100 IRE; burst = 43 IRE; NTSC encoding BSTA = 0 to 1.20 × nominal(3) white-to-black = 100 IRE; burst = 43 IRE; PAL encoding BSTA = 0 to 1.67 × nominal(4) DECTYP real time control input (RTCI) logic 0 control from SAA7151B digital colour decoder logic 1 control from SAA7111 video input processor (VIP) Notes 1. Recommended value: BSTA = 102 (66H). 2. Recommended value: BSTA = 72 (48H). 3. Recommended value: BSTA = 106 (6AH). 4. Recommended value: BSTA = 75 (4BH). Table 17 Subaddress 63 to 66 (four bytes to program subcarrier frequency) DATA BYTE DESCRIPTION CONDITIONS FSC0 to FSC3 ffsc = subcarrier frequency f fsc 32 FSC = round -------- × 2 (in multiples of line f llc frequency); fllc = clock frequency (in see note 1 multiples of line frequency) Note 1. Examples: a) NTSC-M: ffsc = 227.5, fllc = 1716 → FSC = 569408543 (21F07C1FH). b) PAL-B/G: ffsc = 283.7516, fllc = 1728 → FSC = 705268427 (2A098ACBH). 1996 Jul 03 17 REMARKS FSC3 = most significant byte FSC0 = least significant byte Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B Table 18 Subaddress 67 to 6A DATA BYTE(1) DESCRIPTION L21O0 first byte of captioning data, odd field L21O1 second byte of captioning data, odd field L21E0 first byte of extended data, even field L21E1 second byte of extended data, even field Note 1. LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective bytes have to carry the parity bit, in accordance with the definition of line 21 encoding format. Table 19 Subaddress 6B DATA BYTE DESCRIPTION SCCLN selects the actual line, where closed caption or extended data is encoded; see note 1 MODIN defines video data of MP port or VP (DP) port to be encoded; see Table 20 PCREF 0 = normal polarity of CREF for DIG TV2 compatible input signals; 1 = inverted Note 1. Line = (SCCLN + 4) for M systems; line = (SCCLN + 1) for other systems. Table 20 Logic levels and function of MODIN DATA BYTE FUNCTION MODIN1 MODIN0 0 0 unconditionally from MP port 0 1 from MP port, if pin SEL_ED = HIGH; otherwise from VP port 1 0 unconditionally from VP port 1 1 from VP port, if pin SEL_ED = HIGH; otherwise from MP port 1996 Jul 03 18 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B Table 21 Subaddress 6C DATA BYTE LOGIC LEVEL PRCV2 0 polarity of RCV2 as output is active HIGH, rising edge is taken when input, respectively. Default after reset 1 polarity of RCV2 as output is active LOW, falling edge is taken when input, respectively 0 pin RCV2 is switched to input. Default after reset 1 pin RCV2 is switched to output 0 if ORCV2 = HIGH, pin RCV2 provides an HREF signal (Horizontal Reference Pulse that is defined by RCV2S and RCV2E, also during vertical blanking Interval). Default after reset ORCV2 CBLF DESCRIPTION if ORCV2 = LOW, signal input to RCV2 is used for horizontal synchronization only (if TRCV2 = 1). Default after reset 1 if ORCV2 = HIGH, pin RCV2 provides a ‘composite blanking not’ signal i.e. a reference pulse that is defined by RCV2S and RCV2E, excluding vertical blanking Interval, which is defined by FAL and LAL (PRCV2 must be LOW) if ORCV2 = LOW, signal input to RCV2 is used for horizontal synchronization (if TRCV2 = 1) and as an internal blanking signal PRCV1 ORCV1 TRCV2 SRCV1 0 polarity of RCV1 as output is active HIGH, rising edge is taken when input, respectively. Default after reset 1 polarity of RCV1 as output is active LOW, falling edge is taken when input, respectively 0 pin RCV1 is switched to input. Default after reset 1 pin RCV1 is switched to output 0 horizontal synchronization is taken from RCV1 port. Default after reset 1 horizontal synchronization is taken from RCV2 port − defines signal type on pin RCV1; see Table 22 Table 22 Logic levels and function of SRCV1 DATA BYTE AS OUTPUT AS INPUT 0 VS VS vertical sync each field. Default after reset 1 FS FS frame sync (odd/even) 1 0 FSEQ FSEQ 1 1 not applicable not applicable SRCV11 SRCV10 0 0 FUNCTION field sequence, vertical sync every fourth field (PAL = 0) or eighth field (PAL = 1) Table 23 Subaddress 6D DATA BYTE DESCRIPTION CCEN enables individual line 21 encoding; see Table 24 SRCM defines signal type on pin RCM1; see Table 25 1996 Jul 03 19 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B Table 24 Logic levels and function of CCEN DATA BYTE FUNCTION CCEN1 CCEN0 0 0 line 21 encoding OFF 0 1 enables encoding in field 1 (odd) 1 0 enables encoding in field 2 (even) 1 1 enables encoding in both fields Table 25 Logic levels and function of SRCM DATA BYTE AS OUTPUT FUNCTION SRCM1 SRCM0 0 0 VS vertical sync each field 0 1 FS frame sync (odd/even) 1 0 FSEQ 1 1 not applicable field sequence, vertical sync every fourth field (FISE = 1) or eighth field (FISE = 0) Table 26 Subaddress 6E to 6F DATA BYTE HTRIG DESCRIPTION sets the horizontal trigger phase related to signal on RCV1 or RCV2 input values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed increasing HTRIG decreases delays of all internally generated timing signals reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV used for triggering at HTRIG = 037H Table 27 Subaddress 70 DATA BYTE LOGIC LEVEL VTRIG − DESCRIPTION sets the vertical trigger phase related to signal on RCV1 input increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines variation range of VTRIG = 0 to 31 (1FH) SBLBN PHRES 0 vertical blanking is defined by programming of FAL and LAL 1 vertical blanking is forced in accordance with CCIR-624 (50 Hz) or RS170A (60 Hz); note 1 − selects the phase reset mode of the colour subcarrier generator; see Table 28 Note 1. If cross-colour reduction is programmed, it is active between FAL and LAL in both events. 1996 Jul 03 20 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B Table 28 Logic levels and function of PHRES DATA BYTE FUNCTION PHRES1 PHRES0 0 0 no reset or reset via RTCI from SAA7111 if bit RTCE = 1 0 1 reset every two lines 1 0 reset every eight fields 1 1 reset every four fields Table 29 Subaddress 71 to 73 DATA BYTE BMRQ DESCRIPTION beginning of MP request signal (RCM2) values above 1715 (FISE = 1) or 1727 [FISE = 0] are not allowed first active pixel at analog outputs (corresponding input pixel coinciding with RCM2) at BMRQ = 0F9H [117H] EMRQ end of MP request signal (RCM2) values above 1715 (FISE = 1) or 1727 [FISE = 0] are not allowed last active pixel at analog outputs (corresponding input pixel coinciding with RCM2) at EMRQ = 683H [691H] Table 30 Subaddress 77 to 79 DATA BYTE BRCV DESCRIPTION beginning of output signal on RCV2 pin values above 1715 (FISE = 1) or 1727 [FISE = 0] are not allowed first active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at BRCV = 0F9H [117H] ERCV end of output signal on RCV2 pin values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed last active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at ERCV = 683H [691H] 1996 Jul 03 21 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B Table 31 Subaddress 7A DATA BYTE DESCRIPTION FLC1 FLC0 0 0 field length control interlaced 312.5 lines/fields at 50 Hz, 262.5 lines/fields at 60 Hz (reset default) 0 1 field length control non-interlaced 312 lines/fields at 50 Hz, 262 lines/fields at 60 Hz 1 0 field length control non-interlaced 313 lines/fields at 50 Hz, 262 lines/fields at 60 Hz 1 1 field length control non-interlaced 313 lines/fields at 50 Hz, 262 lines/fields at 60 Hz Table 32 Subaddress 7B to 7D DATA BYTE DESCRIPTION FAL first active line = FAL + 4 for M systems; = FAL + 1 for other systems, measured in lines LAL last active line = LAL + 3 for M systems; = LAL for other systems, measured in lines FAL = 0 coincides with the first field synchronization pulse LAL = 0 coincides with the first field synchronization pulse Slave Transmitter Table 33 Slave Transmitter (slave address 89H or 8DH) REGISTER FUNCTION DATA BYTE SUBADDRESS − Status byte D7 D6 D5 VER2 VER1 VER0 D4 D3 CCRDO CCRDE D2 D1 D0 FSQ2 FSQ1 FSQ0 Table 34 No subaddress DATA BYTE VER CCRDO DESCRIPTION Version identification of the device. It will be changed with all versions of the IC that have different programming models. Current version is 100 binary. 1 = closed caption bytes of the odd field have been encoded. 0 = the bit is reset after information has been written to the subaddresses 67 and 68. It is set immediately after the data have been encoded. CCRDE 1 = closed caption bytes of the even field have been encoded. 0 = the bit is reset after information has been written to the subaddresses 69 and 6A. It is set immediately after the data have been encoded. FSQ State of the internal field sequence counter. Bit 0 (FSQ0) gives the odd/even information; odd = LOW, even = HIGH. 1996 Jul 03 22 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B MBE737 handbook, full 6 pagewidth Gv (dB) 0 −6 −12 −18 −24 (1) (2) −30 −36 −42 −48 −54 0 2 4 6 8 10 (1) SCBW = 1. (2) SCBW = 0. Fig.3 Chrominance transfer characteristic 1. MBE735 handbook, halfpage 2 Gv (dB) 0 (1) (2) −2 −4 −6 0 0.4 0.8 1.2 f (MHz) 1.6 (1) SCBW = 1. (2) SCBW = 0. Fig.4 Chrominance transfer characteristic 2. 1996 Jul 03 23 12 f (MHz) 14 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B MBE738 6 Gv full pagewidth handbook, (dB) (4) 0 (2) (3) −6 −12 −18 −24 (1) −30 −36 −42 −48 −54 0 (1) (2) (3) (4) 2 4 6 8 10 CCRS1 = 0; CCRS0 = 1. CCRS1 = 1; CCRS0 = 0. CCRS1 = 1; CCRS0 = 1. CCRS1 = 0; CCRS0 = 0. Fig.5 Luminance transfer characteristic 1. MBE736 handbook, halfpage 1 Gv (dB) 0 −1 −2 −3 −4 −5 0 2 4 f (MHz) 6 CCRS1 = 0; CCRS0 = 0. Fig.6 Luminance transfer characteristic 2. 1996 Jul 03 24 12 f (MHz) 14 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B CHARACTERISTICS VDDD = 4.5 to 5.5 V; Tamb = 0 to 70 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Supply VDDD digital supply voltage 4.5 5.5 V VDDA analog supply voltage 4.75 5.25 V IDDD digital supply current note 1 − 170 mA IDDA analog supply current note 1 − 55 mA V Inputs VIL LOW level input voltage (except SDA, SCL, AP, SP and XTALI) −0.5 +0.8 VIH HIGH level input voltage (except LLC, SDA, SCL, AP, SP and XTALI) 2.0 VDDD + 0.5 V HIGH level input voltage (LLC) 2.4 VDDD + 0.5 V ILI input leakage current − 1 µA CI input capacitance clocks operating − 10 pF data available − 8 pF I/Os at high impedance − 8 pF V Outputs VOL LOW level output voltage (except SDA and XTALO) note 2 0 0.6 VOH HIGH level output voltage (except LLC, SDA, DTACK and XTALO) note 2 2.4 VDDD + 0.5 V HIGH level output voltage (LLC) note 2 2.6 VDDD + 0.5 V I2C-bus; SDA and SCL VIL LOW level input voltage −0.5 +1.5 VIH HIGH level input voltage 3.0 VDDD + 0.5 V II input current VI = LOW or HIGH −10 +10 µA VOL LOW level output voltage (SDA) IOL = 3 mA − 0.4 V IO output current during acknowledge 3 − mA V Clock timing (LLC) TLLC cycle time note 3 34 41 ns δ duty factor tHIGH/TLLC note 4 40 60 % tr rise time note 3 − 5 ns tf fall time note 3 − 6 ns Input timing tSU input data set-up time (any other except SEL_MPU, CDIR, RW/SCL, A0/SDA, CS/SA, RES, AP and SP) 6 − ns tHD input data hold time (any other except SEL_MPU, CDIR, RW/SCL, A0/SDA, CS/SA, RES, AP and SP) 3 − ns 1996 Jul 03 25 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SYMBOL SAA7184; SAA7185B PARAMETER CONDITIONS MIN. MAX. UNIT Crystal oscillator fn nominal frequency (usually 27 MHz) 3rd harmonic − 30 MHz ∆f/fn permissible deviation of nominal frequency note 5 −50 +50 10−6 CRYSTAL SPECIFICATION Tamb operating ambient temperature 0 70 °C CL load capacitance 8 − pF RS series resistance − 80 Ω C1 motional capacitance (typical) 1.5 −20% 1.5 +20% fF C0 parallel capacitance (typical) 3.5 −20% 3.5 +20% pF MPU interface timing 9 − ns 0 − ns 9 − ns 0 − ns 75 142 ns notes 7 and 8 38 105 ns tAS address set-up time tAH address hold time note 6 tRWS read/write set-up time tRWH read/write hold time tDD data bus floating from CS (read) notes 7, 8 and 9 tDF data valid from CS (read) note 6 tDS data bus set-up time (write) note 6 9 − ns tDH data bus hold time (write) note 6 9 − ns tACS acknowledge delay from CS notes 7 and 8 112 180 ns tCSD CS HIGH from acknowledge 0 − ns tDAT DTACK floating from CS HIGH 75 142 ns notes 7 and 8; n = 7 Data and reference signal output timing CL output load capacitance 7.5 40 pF tOH output hold time 4 − ns tOD output delay time CREF in output mode − 25 ns note 10 1.9 2.1 V Chroma, Y and CVBS outputs Vo(p-p) output signal voltage (peak-to-peak value) RI internal series resistance 18 35 Ω RL output load resistance 80 − Ω B output signal bandwidth of DACs 10 − MHz ILE LF integral linearity error of DACs − ±2 LSB DLE LF differential linearity error of DACs − ±1 LSB 1996 Jul 03 −3 dB 26 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B Notes to the Characteristics 1. At maximum supply voltage with highly active input signals. 2. The levels have to be measured with load circuits of 1.2 kΩ to 3.0 V (standard TTL load) and CL = 25 pF. 3. The data is for both input and output direction. 4. With LLC in input mode. In output mode, with a crystal connected to XTALO/XTALI duty factor is typically 50%. 5. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency. 6. The value is calculated via equation t = t SU + t HD 7. The value depends on the clock frequency. The numbers given are calculated with fLLC = 27 MHz. 8. The values given are calculated via equation t dmax = t OD + n × t LLC + t LLC + t SU and t dmin = t OH + n × t LLC + t LLC – t HD 9. The falling edge of DTACK will always occur 1 × LLC after data is valid. 10. For full digital range, without load, VDDA = 5.0 V. The typical voltage swing is 2.0 V, the typical minimum output voltage (digital zero at DAC) is 0.2 V. handbook, full pagewidth TLLC tHIGH 2.6 V 1.5 V 0.6 V LLC clock output tHD; DAT tf tr TLLC tHIGH 2.4 V 1.5 V 0.8 V LLC clock input tSU; DAT tHD; DAT tf tr 2.0 V input data valid not valid valid 0.8 V tHD; DAT td 2.4 V output data valid not valid valid 0.6 V MBE742 Fig.7 Clock data timing. 1996 Jul 03 27 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B handbook, full pagewidth LLC CREF VP(n) Y(0) Y(1) Y(2) Y(3) Y(4) DP(n) Cb(0) Cr(0) Cb(2) Cr(2) Cb(4) RCV2 MBE739 The data demultiplexing phase is coupled to the internal horizontal phase. The CREF signal applies only for the 16 lines digital TV format, because these signals are only valid in 13.5 MHz. The phase of the RCV2 signal is programmed to tbf (tbf for 50 Hz) in this example in output mode (BRCV2). Fig.8 Digital TV timing. handbook, full pagewidth H/L transition count start 128 HPLL increment 13 4 bits reserved 0 5 bits reserved 21 sequence bit (1) reserved (2) 0 RTCI not used in DENC2 valid invalid sample sample (1) Sequence bit: PAL = logic 0 then (R − Y) line normal; PAL = logic 1 then (R − Y) line inverted. NTSC = logic 0 then no change. (2) Reserved bits: 235 with 50 Hz systems; 232 with 60 Hz systems. (3) Only from SAA7111 decoder. (4) SAA7111 provides (22:0) bits, resulting in 3 reserved bits before sequence bit. Fig.9 RTCI timing. 1996 Jul 03 28 8/LLC MBE743 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B handbook, full pagewidth A0 tAS tAH tRWS tRWH CSN RWN D(7 to 0) tDF tDD DTACK tACS tCSD tDAT MBE740 Fig.10 MPU interface timing (READ cycle). handbook, full pagewidth A0 tAS tAH tRWS tRWH CSN RWN D(7 to 0) tDF tDS DTACK tACS tCSD tDAT Fig.11 MPU interface timing (WRITE cycle). 1996 Jul 03 29 MBE741 1996 Jul 03 VDDD1 17 XTAL0 40 41 10 pF XTAL1 3rd harmonic 10 pF X1 27.0 MHz 0.1 µF 0.1 µF 0.1 µF 67 30 VSSD VSSD VSSD 56 VrefL VSSD1 to VSSD7 VSSA 52 35 Ω (1) 53 35 Ω (1) 49 VSSA DAC1 48 VDDA1 VSSA VSSA 35 Ω (1) 51 50 VDDA2 0.1 µF 0.1 µF 0.1 µF DAC2 DAC3 55 47 54 IOA VDDA3 VrefH 46 0.1 µF 0.1 µF 15 kΩ 1, 8, 19, 28, 35, 42, 62 VDDA4 VSSA VSSA + 5 V analog Fig.12 Application environment of the DENC2-M6. SAA7184 SAA7185B 37 VDDD2 VDDD3 + 5 V digital VSSA Y CVBS 1.23 V (p-p)(2) VSSA 1.0 V (p-p) (2) VSSA CHROMA 0.62 V (p-p) (2) MGC680 75 Ω 12 Ω 75 Ω 20 Ω 75 Ω 20 Ω Digital Video Encoders (DENC2-M6) (1) Typical value. (2) For 100/100 colour bar. digital inputs and outputs 1 nF 10 µH handbook, full pagewidth VSSD Philips Semiconductors Preliminary specification SAA7184; SAA7185B APPLICATION INFORMATION Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B PACKAGE OUTLINE PLCC68: plastic leaded chip carrier; 68 leads SOT188-2 eD eE y X 60 A 44 43 Z E 61 bp b1 w M 68 1 HE E pin 1 index A e A4 A1 (A 3) β 9 k1 27 Lp k detail X 10 26 e v M A ZD D B HD v M B 0 5 10 mm scale DIMENSIONS (millimetre dimensions are derived from the original inch dimensions) UNIT A A1 min. A3 A4 max. bp b1 mm 4.57 4.19 0.51 0.25 3.30 0.53 0.33 0.81 0.66 0.180 inches 0.020 0.01 0.165 D (1) E (1) e eD eE HD HE k 24.33 24.33 23.62 23.62 25.27 25.27 1.22 1.27 24.13 24.13 22.61 22.61 25.02 25.02 1.07 k1 max. Lp v w y 0.51 1.44 1.02 0.18 0.18 0.10 Z D(1) Z E (1) max. max. 2.16 β 2.16 45 o 0.930 0.930 0.995 0.995 0.048 0.057 0.021 0.032 0.958 0.958 0.020 0.05 0.007 0.007 0.004 0.085 0.085 0.13 0.890 0.890 0.985 0.985 0.042 0.040 0.013 0.026 0.950 0.950 Note 1. Plastic or metal protrusions of 0.01 inches maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT188-2 112E10 MO-047AC 1996 Jul 03 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-03-11 31 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B SOLDERING Wave soldering Introduction Wave soldering techniques can be used for all PLCC packages if the following conditions are observed: There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. • The longitudinal axis of the package footprint must be parallel to the solder flow. • The package footprint must incorporate solder thieves at the downstream corners. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all PLCC packages. Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. The choice of heating method may be influenced by larger PLCC packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9398 510 63011). A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. 1996 Jul 03 32 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1996 Jul 03 33 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B NOTES 1996 Jul 03 34 Philips Semiconductors Preliminary specification Digital Video Encoders (DENC2-M6) SAA7184; SAA7185B NOTES 1996 Jul 03 35 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 2A Akademika Koroleva str., Office 165, 252148 KIEV, Tel. +380 44 476 0297/1642, Fax. +380 44 476 6991 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 708 296 8556 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 825 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com/ps/ (1) SAA7184_85B_2 June 26, 1996 11:51 am © Philips Electronics N.V. 1996 SCA50 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 657021/1200/02/pp36 Date of release: 1996 Jul 03 Document order number: 9397 750 00439